Merge tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
The Freescale arm64 device tree updates for 4.8: - Update address-cells and reg properties of cpu nodes, considering MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a and ls2080a - Adds the cache nodes and next-level-cache property for ls1043a and ls2080a to get cacheinfo work on these platforms - Add dma-coherent for ls1043a PCI nodes to utilize the hardware capability on data coherency - Add dis_rxdet_inp3_quirk property for USB3 device to disable rx detection in P3 PHY mode * tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: ls2080a: Add cache nodes for cacheinfo support arm64: dts: ls1043a: Add cache nodes for cacheinfo support arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes bindings: PCI: layerscape: Add 'dma-coherent' property arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node arm64: dts: fsl: Update address-cells and reg properties of cpu nodes Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
@@ -24,6 +24,9 @@ Required properties:
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The first entry must be a link to the SCFG device node
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The second entry must be '0' or '1' based on physical PCIe controller index.
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This is used to get SCFG PEXN registers
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- dma-coherent: Indicates that the hardware IP block can ensure the coherency
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of the data transferred from/to the IP block. This can avoid the software
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cache flush/invalid actions, and improve the performance significantly.
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Example:
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@@ -38,6 +41,7 @@ Example:
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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@@ -51,7 +51,7 @@
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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@@ -63,29 +63,37 @@
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x0>;
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x1>;
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x2>;
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reg = <0x2>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x0 0x3>;
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reg = <0x3>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&l2>;
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};
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l2: l2-cache {
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compatible = "cache";
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};
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};
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@@ -422,6 +430,7 @@
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interrupts = <0 60 0x4>;
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,dis_rxdet_inp3_quirk;
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};
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usb1: usb3@3000000 {
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@@ -430,6 +439,7 @@
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interrupts = <0 61 0x4>;
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,dis_rxdet_inp3_quirk;
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};
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usb2: usb3@3100000 {
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@@ -438,6 +448,7 @@
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interrupts = <0 63 0x4>;
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,dis_rxdet_inp3_quirk;
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};
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sata: sata@3200000 {
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@@ -479,6 +490,7 @@
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-lanes = <4>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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@@ -503,6 +515,7 @@
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-lanes = <2>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
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@@ -527,6 +540,7 @@
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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num-lanes = <2>;
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
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@@ -51,7 +51,7 @@
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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@@ -65,57 +65,81 @@
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x1>;
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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next-level-cache = <&cluster0_l2>;
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};
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cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x100>;
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reg = <0x100>;
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clocks = <&clockgen 1 1>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x101>;
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reg = <0x101>;
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clocks = <&clockgen 1 1>;
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next-level-cache = <&cluster1_l2>;
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};
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x200>;
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reg = <0x200>;
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clocks = <&clockgen 1 2>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x201>;
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reg = <0x201>;
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clocks = <&clockgen 1 2>;
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next-level-cache = <&cluster2_l2>;
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};
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cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x300>;
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reg = <0x300>;
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clocks = <&clockgen 1 3>;
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next-level-cache = <&cluster3_l2>;
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};
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cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0 0x301>;
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reg = <0x301>;
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clocks = <&clockgen 1 3>;
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next-level-cache = <&cluster3_l2>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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};
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cluster2_l2: l2-cache2 {
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compatible = "cache";
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};
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cluster3_l2: l2-cache3 {
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compatible = "cache";
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};
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};
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@@ -672,6 +696,7 @@
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interrupts = <0 80 0x4>; /* Level high type */
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,dis_rxdet_inp3_quirk;
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};
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usb1: usb3@3110000 {
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@@ -681,6 +706,7 @@
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interrupts = <0 81 0x4>; /* Level high type */
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dr_mode = "host";
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snps,quirk-frame-length-adjustment = <0x20>;
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snps,dis_rxdet_inp3_quirk;
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};
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ccn@4000000 {
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