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Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes"

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This reverts commit afcbe252e9.

The commit in question caused my sc7280-herobrine-herobrine-r1 board
not to boot anymore. This shouldn't be too surprising since the driver
is relying on the name "cqhci".

The issue seems to be that someone decided to change the names of
things when the binding moved from .txt to .yaml. We should go back to
the names that the bindings have historically specified.

For some history, see commit d3392339ca ("mmc: cqhci: Update cqhci
memory ioresource name") and commit d79100c91a ("dt-bindings: mmc:
sdhci-msm: Add CQE reg map").

Fixes: afcbe252e9 ("arm64: dts: qcom: Fix 'reg-names' for sdhci nodes")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220706144706.1.I48f35820bf3670d54940110462555c2d0a6d5eb2@changeid
This commit is contained in:
Douglas Anderson
2022-07-06 14:47:33 -07:00
committed by Bjorn Andersson
parent 713aa4efbc
commit 21857088fa
6 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@@ -809,7 +809,7 @@
sdcc1: mmc@7804000 {
compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
reg-names = "hc_mem", "cqe_mem";
reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@@ -697,7 +697,7 @@
compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x7c4000 0 0x1000>,
<0 0x07c5000 0 0x1000>;
reg-names = "hc_mem", "cqe_mem";
reg-names = "hc", "cqhci";
iommus = <&apps_smmu 0x60 0x0>;
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,

2
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@@ -866,7 +866,7 @@
reg = <0 0x007c4000 0 0x1000>,
<0 0x007c5000 0 0x1000>;
reg-names = "hc_mem", "cqe_mem";
reg-names = "hc", "cqhci";
iommus = <&apps_smmu 0xc0 0x0>;
interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,

4
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@@ -1280,7 +1280,7 @@
sdhc_2: mmc@c084000 {
compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5";
reg = <0x0c084000 0x1000>;
reg-names = "hc_mem";
reg-names = "hc";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
@@ -1335,7 +1335,7 @@
reg = <0x0c0c4000 0x1000>,
<0x0c0c5000 0x1000>,
<0x0c0c8000 0x8000>;
reg-names = "hc_mem", "cqe_mem", "ice_mem";
reg-names = "hc", "cqhci", "ice";
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;

4
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@@ -458,7 +458,7 @@
sdhc_1: mmc@4744000 {
compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
reg-names = "hc_mem", "core_mem";
reg-names = "hc", "core";
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -482,7 +482,7 @@
sdhc_2: mmc@4784000 {
compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
reg = <0x04784000 0x1000>;
reg-names = "hc_mem";
reg-names = "hc";
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;

2
arch/arm64/boot/dts/qcom/sm6350.dtsi
View File

@@ -477,7 +477,7 @@
reg = <0 0x007c4000 0 0x1000>,
<0 0x007c5000 0 0x1000>,
<0 0x007c8000 0 0x8000>;
reg-names = "hc_mem", "cqe_mem", "ice_mem";
reg-names = "hc", "cqhci", "ice";
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;