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LoongArch: extable: Also recognize ABI names of registers

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When the kernel is compiled with LLVM, the register names being handled
during exception fixup building are ABI names instead of bare $rNN
style. Add mapping for the ABI names for LLVM compatibility.

Signed-off-by: WANG Rui <wangrui@loongson.cn>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
This commit is contained in:
WANG Rui
2023-06-29 20:58:43 +08:00
committed by Huacai Chen
parent 414cefc798
commit 24da0249d9
1 changed files with 30 additions and 0 deletions
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30
arch/loongarch/include/asm/gpr-num.h
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@@ -9,6 +9,22 @@
.equ .L__gpr_num_$r\num, \num
.endr
/* ABI names of registers */
.equ .L__gpr_num_$ra, 1
.equ .L__gpr_num_$tp, 2
.equ .L__gpr_num_$sp, 3
.irp num,0,1,2,3,4,5,6,7
.equ .L__gpr_num_$a\num, 4 + \num
.endr
.irp num,0,1,2,3,4,5,6,7,8
.equ .L__gpr_num_$t\num, 12 + \num
.endr
.equ .L__gpr_num_$s9, 22
.equ .L__gpr_num_$fp, 22
.irp num,0,1,2,3,4,5,6,7,8
.equ .L__gpr_num_$s\num, 23 + \num
.endr
#else /* __ASSEMBLY__ */
#define __DEFINE_ASM_GPR_NUMS \
@@ -16,6 +32,20 @@
" .irp num,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31\n" \
" .equ .L__gpr_num_$r\\num, \\num\n" \
" .endr\n" \
" .equ .L__gpr_num_$ra, 1\n" \
" .equ .L__gpr_num_$tp, 2\n" \
" .equ .L__gpr_num_$sp, 3\n" \
" .irp num,0,1,2,3,4,5,6,7\n" \
" .equ .L__gpr_num_$a\\num, 4 + \\num\n" \
" .endr\n" \
" .irp num,0,1,2,3,4,5,6,7,8\n" \
" .equ .L__gpr_num_$t\\num, 12 + \\num\n" \
" .endr\n" \
" .equ .L__gpr_num_$s9, 22\n" \
" .equ .L__gpr_num_$fp, 22\n" \
" .irp num,0,1,2,3,4,5,6,7,8\n" \
" .equ .L__gpr_num_$s\\num, 23 + \\num\n" \
" .endr\n" \
#endif /* __ASSEMBLY__ */