staging: comedi: addi_apci_3120: introduce apci3120_clr_timer2_interrupt()
A dummy read of APCI3120_CTR0_REG clears the timer 2 interrupt. Introduce a helper function to clarify this. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Greg Kroah-Hartman
parent
b17d390661
commit
24e18c85e5
@@ -130,7 +130,6 @@ This program is distributed in the hope that it will be useful, but WITHOUT ANY
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#define APCI3120_DISABLE_TIMER_INT (~APCI3120_ENABLE_TIMER_INT)
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#define APCI3120_WRITE_MODE_SELECT 0x0e
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#define APCI3120_TIMER_STATUS_REGISTER 0x0d
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#define APCI3120_RD_STATUS 0x02
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#define APCI3120_ENABLE_WATCHDOG 0x20
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#define APCI3120_DISABLE_WATCHDOG (~APCI3120_ENABLE_WATCHDOG)
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@@ -691,8 +690,8 @@ static int apci3120_cyclic_ai(int mode,
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/* Set the scan stop count (not sure about the -2) */
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apci3120_timer_write(dev, 2, cmd->stop_arg - 2);
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/* (2) Reset FC_TIMER BIT Clearing timer status register */
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inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER);
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apci3120_clr_timer2_interrupt(dev);
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/* enable timer counter and disable watch dog */
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devpriv->b_ModeSelectRegister =
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(devpriv->
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@@ -1067,7 +1066,6 @@ static irqreturn_t apci3120_interrupt(int irq, void *d)
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unsigned short int_daq;
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unsigned int int_amcc, ui_Check, i;
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unsigned short us_TmpValue;
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unsigned char b_DummyRead;
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ui_Check = 1;
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@@ -1087,8 +1085,8 @@ static irqreturn_t apci3120_interrupt(int irq, void *d)
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apci3120_exttrig_enable(dev, false);
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devpriv->b_ExttrigEnable = APCI3120_DISABLE;
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}
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/* clear the timer 2 interrupt */
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inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER);
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apci3120_clr_timer2_interrupt(dev);
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if (int_amcc & MASTER_ABORT_INT)
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dev_err(dev->class_dev, "AMCC IRQ - MASTER DMA ABORT!\n");
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@@ -1194,8 +1192,7 @@ static irqreturn_t apci3120_interrupt(int irq, void *d)
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}
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b_DummyRead = inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER);
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apci3120_clr_timer2_interrupt(dev);
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}
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if ((int_daq & 0x4) && (devpriv->b_InterruptMode == APCI3120_DMA_MODE)) {
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@@ -1205,8 +1202,8 @@ static irqreturn_t apci3120_interrupt(int irq, void *d)
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outl(APCI3120_CLEAR_WRITE_TC_INT,
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devpriv->amcc + APCI3120_AMCC_OP_REG_INTCSR);
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/* Clears the timer status register */
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inw(dev->iobase + APCI3120_TIMER_STATUS_REGISTER);
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apci3120_clr_timer2_interrupt(dev);
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/* do some data transfer */
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apci3120_interrupt_dma(irq, d);
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} else {
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@@ -1318,9 +1315,8 @@ static int apci3120_write_insn_timer(struct comedi_device *dev,
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switch (data[0]) {
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case APCI3120_START:
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apci3120_clr_timer2_interrupt(dev);
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/* Reset FC_TIMER BIT */
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inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER);
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if (devpriv->b_Timer2Mode == APCI3120_TIMER) { /* start timer */
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/* Enable Timer */
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devpriv->b_ModeSelectRegister =
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@@ -1382,9 +1378,7 @@ static int apci3120_write_insn_timer(struct comedi_device *dev,
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apci3120_timer_enable(dev, 2, false);
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/* Reset FC_TIMER BIT */
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inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER);
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apci3120_clr_timer2_interrupt(dev);
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break;
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case 2: /* write new value to Timer */
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@@ -1434,10 +1428,8 @@ static int apci3120_read_insn_timer(struct comedi_device *dev,
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us_StatusValue = inw(dev->iobase + APCI3120_RD_STATUS);
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us_StatusValue =
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((us_StatusValue & APCI3120_FC_TIMER) >> 12) & 1;
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if (us_StatusValue == 1) {
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/* RESET FC_TIMER BIT */
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inb(dev->iobase + APCI3120_TIMER_STATUS_REGISTER);
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}
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if (us_StatusValue == 1)
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apci3120_clr_timer2_interrupt(dev);
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data[0] = us_StatusValue; /* when data[0] = 1 then the watch dog has rundown */
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}
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return insn->n;
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@@ -155,6 +155,12 @@ static unsigned int apci3120_ns_to_timer(struct comedi_device *dev,
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return divisor;
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}
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static void apci3120_clr_timer2_interrupt(struct comedi_device *dev)
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{
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/* a dummy read of APCI3120_CTR0_REG clears the timer 2 interrupt */
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inb(dev->iobase + APCI3120_CTR0_REG);
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}
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static void apci3120_timer_write(struct comedi_device *dev,
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unsigned int timer, unsigned int val)
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{
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