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arm64: dts: qcom: sa8540p-ride: enable pcie2a node

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Add the pcie2a, pcie2a_phy, and respective tlmm nodes that are needed to
get pcie 2a controller enabled on Qdrive3.

This patch enables 4GB 64bit memory space for PCIE_2A to have BAR
allocations of 64bit pref mem needed on this Qdrive3 platform with dual
SoCs for root port and switch NT-EP. Hence this ranges property is
overridden in sa8540p-ride.dts only.

Moved tlmm node at the end as it tends to become rahter long.

Link: https://lore.kernel.org/lkml/Y49k1k8ayI9%2FrK+R@hovoldconsulting.com/
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213095922.11649-1-quic_shazhuss@quicinc.com
This commit is contained in:
Shazad Hussain
2022-12-13 15:29:21 +05:30
committed by Bjorn Andersson
parent 3bd21131d8
commit 2eb4cdcd5a
1 changed files with 71 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

96
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
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@@ -146,6 +146,27 @@
};
};
&pcie2a {
ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
<0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2a_default>;
status = "okay";
};
&pcie2a_phy {
vdda-phy-supply = <&vreg_l11a>;
vdda-pll-supply = <&vreg_l3a>;
status = "okay";
};
&pcie3a {
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
@@ -186,31 +207,6 @@
status = "okay";
};
&tlmm {
pcie3a_default: pcie3a-default-state {
perst-pins {
pins = "gpio151";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio150";
function = "pcie3a_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio56";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&ufs_mem_hc {
reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
@@ -268,3 +264,53 @@
&xo_board_clk {
clock-frequency = <38400000>;
};
/* PINCTRL */
&tlmm {
pcie2a_default: pcie2a-default-state {
perst-pins {
pins = "gpio143";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio142";
function = "pcie2a_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio145";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie3a_default: pcie3a-default-state {
perst-pins {
pins = "gpio151";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio150";
function = "pcie3a_clkreq";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio56";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};