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clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments

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The multipliers for PLL2 and PLL4 as listed in the comments for
the cpg_pll_configs[] array are incorrect.  Fix them.

Note that the actual values in the tables were correct.

Fixes: f077cab34d ("clk: renesas: cpg-mssr: Add support for R-Car V4M")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
2024-06-12 09:25:16 +02:00
parent f92d44a00b
commit 362951fef4
1 changed files with 3 additions and 3 deletions
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6
drivers/clk/renesas/r8a779h0-cpg-mssr.c
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@@ -242,10 +242,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
* 14 13 (MHz)
* ------------------------------------------------------------------------
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
* 0 0 16.66 / 1 x192 x240 x192 x240 x192 x168 /16
* 0 1 20 / 1 x160 x200 x160 x200 x160 x140 /19
* 1 0 Prohibited setting
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
* 1 1 33.33 / 2 x192 x240 x192 x240 x192 x168 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))