Merge tag 'imx-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 device tree change for 5.18: - New support for a number of i.MX8M Mini based boards: Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, Gateworks GW7903. - A series from Adam Ford to enable GPC, USB and display support for i.MX8M Nano. - Enable G1 and G2 video decoder devices for i.MX8MM and i.MX8MQ. - Enable PCIe support on imx8mm-beacon, tqma8mqml, imx8mm-evk, imx8mq-evk and imx8mm-venice board. - A series from Hugo Villeneuve to add PCA6416 interrupt controller configuration, GPIO line names and i2C5 support for imx8mp-evk board. - Correct I2C3 pad-ctrl and add internal display support for mnt-reform2 board. - Improve fsl-ls1028a-qds overlay support by dropping syntax hard coding and using overlay target for build. - Add overlay support for serial modes and imx219 rpi v2 camera on Gateworks imx8mm-venice devices. - A set of patches from Teresa Remmet to update phyCORE-i.MX8MP SoM device tree, including drive strength updates of different interfaces and PMIC configuration changes. - Device additions on various boards and some small random changes. * tag 'imx-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits) arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMC arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4 arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltage arm64: dts: imx8mp-phycore-som: Update WDOG muxing arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx lines arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strength arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phy arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 camera arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 camera arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modes arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modes arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts support arm64: dts: ls1028a: add efuse node arm64: dts: imx8mp-evk: add support for I2C5 arm64: dts: imx8mp-evk: add PCA6416 gpio line names arm64: dts: imx8qm: added more serial alias to dts arm64: dts: imx8qm: add compatible string for usdhc3 arm64: dts: imx8mq-evk: Add second PCIe port support arm64: dts: imx8mm-beacon: Enable PCIe arm64: dts: freescale: add initial support for verdin imx8m mini ... Link: https://lore.kernel.org/r/20220222075226.160187-5-shawnguo@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -1,14 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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# required for overlay support
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DTC_FLAGS_fsl-ls1028a-qds := -@
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DTC_FLAGS_fsl-ls1028a-qds-13bb := -@
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DTC_FLAGS_fsl-ls1028a-qds-65bb := -@
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DTC_FLAGS_fsl-ls1028a-qds-7777 := -@
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DTC_FLAGS_fsl-ls1028a-qds-85bb := -@
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DTC_FLAGS_fsl-ls1028a-qds-899b := -@
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DTC_FLAGS_fsl-ls1028a-qds-9999 := -@
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
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@@ -21,12 +12,6 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
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@@ -49,9 +34,24 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb
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fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo
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fsl-ls1028a-qds-65bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-65bb.dtbo
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fsl-ls1028a-qds-7777-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-7777.dtbo
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fsl-ls1028a-qds-85bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-85bb.dtbo
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fsl-ls1028a-qds-899b-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-899b.dtbo
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fsl-ls1028a-qds-9999-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-9999.dtbo
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb
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@@ -63,6 +63,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb
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@@ -94,6 +99,24 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
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imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo
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imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo
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imx8mm-venice-gw72xx-0x-rs422-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo
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imx8mm-venice-gw72xx-0x-rs485-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo
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imx8mm-venice-gw73xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo
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imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo
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imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo
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imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-imx219.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb
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dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
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dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
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dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
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@@ -12,102 +12,80 @@
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/dts-v1/;
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/plugin/;
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/ {
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fragment@0 {
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target = <&mdio_slot1>;
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&mdio_slot1 {
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#address-cells = <1>;
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#size-cells = <0>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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slot1_sgmii: ethernet-phy@2 {
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/* AQR112 */
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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};
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fragment@1 {
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target = <&enetc_port0>;
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__overlay__ {
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phy-handle = <&slot1_sgmii>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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status = "okay";
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};
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};
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fragment@2 {
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target = <&mdio_slot2>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 4 ports on AQR412 */
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slot2_qxgmii0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii2: ethernet-phy@2 {
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii3: ethernet-phy@3 {
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reg = <0x3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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};
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fragment@3 {
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target = <&mscc_felix_ports>;
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__overlay__ {
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port@0 {
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status = "okay";
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phy-handle = <&slot2_qxgmii0>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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port@1 {
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status = "okay";
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phy-handle = <&slot2_qxgmii1>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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port@2 {
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status = "okay";
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phy-handle = <&slot2_qxgmii2>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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port@3 {
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status = "okay";
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phy-handle = <&slot2_qxgmii3>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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};
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};
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fragment@4 {
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target = <&mscc_felix>;
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__overlay__ {
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status = "okay";
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};
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slot1_sgmii: ethernet-phy@2 {
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/* AQR112 */
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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&enetc_port0 {
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phy-handle = <&slot1_sgmii>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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status = "okay";
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};
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&mdio_slot2 {
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#address-cells = <1>;
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#size-cells = <0>;
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/* 4 ports on AQR412 */
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slot2_qxgmii0: ethernet-phy@0 {
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reg = <0x0>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii1: ethernet-phy@1 {
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reg = <0x1>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii2: ethernet-phy@2 {
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reg = <0x2>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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slot2_qxgmii3: ethernet-phy@3 {
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reg = <0x3>;
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compatible = "ethernet-phy-ieee802.3-c45";
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};
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};
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|
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&mscc_felix_ports {
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port@0 {
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status = "okay";
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phy-handle = <&slot2_qxgmii0>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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port@1 {
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status = "okay";
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phy-handle = <&slot2_qxgmii1>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
|
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};
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port@2 {
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status = "okay";
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phy-handle = <&slot2_qxgmii2>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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};
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port@3 {
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status = "okay";
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phy-handle = <&slot2_qxgmii3>;
|
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phy-mode = "usxgmii";
|
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managed = "in-band-status";
|
||||
};
|
||||
};
|
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|
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&mscc_felix {
|
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status = "okay";
|
||||
};
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|
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@@ -11,98 +11,76 @@
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/dts-v1/;
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/plugin/;
|
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/ {
|
||||
fragment@0 {
|
||||
target = <&mdio_slot1>;
|
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&mdio_slot1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
slot1_sgmii: ethernet-phy@2 {
|
||||
/* AQR112 */
|
||||
reg = <0x2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&enetc_port0>;
|
||||
|
||||
__overlay__ {
|
||||
phy-handle = <&slot1_sgmii>;
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&mdio_slot2>;
|
||||
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 4 ports on VSC8514 */
|
||||
slot2_qsgmii0: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
|
||||
slot2_qsgmii1: ethernet-phy@9 {
|
||||
reg = <0x9>;
|
||||
};
|
||||
|
||||
slot2_qsgmii2: ethernet-phy@a {
|
||||
reg = <0xa>;
|
||||
};
|
||||
|
||||
slot2_qsgmii3: ethernet-phy@b {
|
||||
reg = <0xb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@3 {
|
||||
target = <&mscc_felix_ports>;
|
||||
|
||||
__overlay__ {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii0>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii1>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii2>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii3>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@4 {
|
||||
target = <&mscc_felix>;
|
||||
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
slot1_sgmii: ethernet-phy@2 {
|
||||
/* AQR112 */
|
||||
reg = <0x2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
};
|
||||
|
||||
&enetc_port0 {
|
||||
phy-handle = <&slot1_sgmii>;
|
||||
phy-mode = "2500base-x";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio_slot2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 4 ports on VSC8514 */
|
||||
slot2_qsgmii0: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
|
||||
slot2_qsgmii1: ethernet-phy@9 {
|
||||
reg = <0x9>;
|
||||
};
|
||||
|
||||
slot2_qsgmii2: ethernet-phy@a {
|
||||
reg = <0xa>;
|
||||
};
|
||||
|
||||
slot2_qsgmii3: ethernet-phy@b {
|
||||
reg = <0xb>;
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix_ports {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii0>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii1>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii2>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii3>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -12,71 +12,58 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
fragment@0 {
|
||||
target = <&mdio_slot1>;
|
||||
&mdio_slot1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 4 ports on AQR412 */
|
||||
slot1_sxgmii0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
|
||||
slot1_sxgmii1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
|
||||
slot1_sxgmii2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
|
||||
slot1_sxgmii3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
};
|
||||
/* 4 ports on AQR412 */
|
||||
slot1_sxgmii0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&mscc_felix_ports>;
|
||||
|
||||
__overlay__ {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sxgmii0>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sxgmii1>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sxgmii2>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sxgmii3>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
};
|
||||
slot1_sxgmii1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&mscc_felix>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
slot1_sxgmii2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
|
||||
slot1_sxgmii3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix_ports {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sxgmii0>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sxgmii1>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sxgmii2>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sxgmii3>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -11,97 +11,75 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
fragment@0 {
|
||||
target = <&mdio_slot1>;
|
||||
&mdio_slot1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
slot1_sgmii: ethernet-phy@1c {
|
||||
/* 1st port on VSC8234 */
|
||||
reg = <0x1c>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&enetc_port0>;
|
||||
|
||||
__overlay__ {
|
||||
phy-handle = <&slot1_sgmii>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&mdio_slot2>;
|
||||
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 4 ports on VSC8514 */
|
||||
slot2_qsgmii0: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
|
||||
slot2_qsgmii1: ethernet-phy@9 {
|
||||
reg = <0x9>;
|
||||
};
|
||||
|
||||
slot2_qsgmii2: ethernet-phy@a {
|
||||
reg = <0xa>;
|
||||
};
|
||||
|
||||
slot2_qsgmii3: ethernet-phy@b {
|
||||
reg = <0xb>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@3 {
|
||||
target = <&mscc_felix_ports>;
|
||||
|
||||
__overlay__ {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii0>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii1>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii2>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii3>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fragment@4 {
|
||||
target = <&mscc_felix>;
|
||||
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
slot1_sgmii: ethernet-phy@1c {
|
||||
/* 1st port on VSC8234 */
|
||||
reg = <0x1c>;
|
||||
};
|
||||
};
|
||||
|
||||
&enetc_port0 {
|
||||
phy-handle = <&slot1_sgmii>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio_slot2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* 4 ports on VSC8514 */
|
||||
slot2_qsgmii0: ethernet-phy@8 {
|
||||
reg = <0x8>;
|
||||
};
|
||||
|
||||
slot2_qsgmii1: ethernet-phy@9 {
|
||||
reg = <0x9>;
|
||||
};
|
||||
|
||||
slot2_qsgmii2: ethernet-phy@a {
|
||||
reg = <0xa>;
|
||||
};
|
||||
|
||||
slot2_qsgmii3: ethernet-phy@b {
|
||||
reg = <0xb>;
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix_ports {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii0>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii1>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii2>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot2_qsgmii3>;
|
||||
phy-mode = "qsgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -11,65 +11,51 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
fragment@0 {
|
||||
target = <&mdio_slot1>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_slot1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* VSC8234 */
|
||||
slot1_sgmii0: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
slot1_sgmii1: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
slot1_sgmii2: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
slot1_sgmii3: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
/* VSC8234 */
|
||||
slot1_sgmii0: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&enetc_port0>;
|
||||
__overlay__ {
|
||||
phy-handle = <&slot1_sgmii0>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
slot1_sgmii1: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&mscc_felix_ports>;
|
||||
__overlay__ {
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii1>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii2>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
};
|
||||
slot1_sgmii2: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
fragment@3 {
|
||||
target = <&mscc_felix>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
slot1_sgmii3: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
&enetc_port0 {
|
||||
phy-handle = <&slot1_sgmii0>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix_ports {
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii1>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii2>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -11,69 +11,58 @@
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
/ {
|
||||
fragment@0 {
|
||||
target = <&mdio_slot1>;
|
||||
__overlay__ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
&mdio_slot1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* VSC8234 */
|
||||
slot1_sgmii0: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
slot1_sgmii1: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
slot1_sgmii2: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
slot1_sgmii3: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
/* VSC8234 */
|
||||
slot1_sgmii0: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
fragment@1 {
|
||||
target = <&mscc_felix_ports>;
|
||||
__overlay__ {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii0>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii1>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii2>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii3>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
};
|
||||
slot1_sgmii1: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
fragment@2 {
|
||||
target = <&mscc_felix>;
|
||||
__overlay__ {
|
||||
status = "okay";
|
||||
};
|
||||
slot1_sgmii2: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
slot1_sgmii3: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix_ports {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii0>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii1>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii2>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
status = "okay";
|
||||
phy-handle = <&slot1_sgmii3>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -107,6 +107,30 @@
|
||||
reg = <5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio_slot1: mdio@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
mdio_slot2: mdio@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
mdio_slot3: mdio@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
};
|
||||
|
||||
mdio_slot4: mdio@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -224,6 +224,17 @@
|
||||
little-endian;
|
||||
};
|
||||
|
||||
efuse@1e80000 {
|
||||
compatible = "fsl,ls1028a-sfp";
|
||||
reg = <0x0 0x1e80000 0x0 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ls1028a_uid: unique-id@1c {
|
||||
reg = <0x1c 0x8>;
|
||||
};
|
||||
};
|
||||
|
||||
scfg: syscon@1fc0000 {
|
||||
compatible = "fsl,ls1028a-scfg", "syscon";
|
||||
reg = <0x0 0x1fc0000 0x0 0x10000>;
|
||||
|
||||
@@ -141,6 +141,22 @@ lsio_subsys: bus@5d000000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lsio_mu5: mailbox@5d200000 {
|
||||
reg = <0x5d200000 0x10000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <2>;
|
||||
power-domains = <&pd IMX_SC_R_MU_5A>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lsio_mu6: mailbox@5d210000 {
|
||||
reg = <0x5d210000 0x10000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#mbox-cells = <2>;
|
||||
power-domains = <&pd IMX_SC_R_MU_6A>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lsio_mu13: mailbox@5d280000 {
|
||||
reg = <0x5d280000 0x10000>;
|
||||
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
@@ -3,6 +3,8 @@
|
||||
* Copyright 2020 Compass Electronics Group, LLC
|
||||
*/
|
||||
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
|
||||
/ {
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
@@ -34,6 +36,19 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
pcie0_refclk_gated: pcie0-refclk-gated {
|
||||
compatible = "gpio-gate-clock";
|
||||
clocks = <&pcie0_refclk>;
|
||||
#clock-cells = <0>;
|
||||
enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
reg_audio: regulator-audio {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3v3_aud";
|
||||
@@ -64,6 +79,16 @@
|
||||
startup-delay-us = <100000>;
|
||||
};
|
||||
|
||||
reg_pcie0: regulator-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pci_pwr_en";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <100000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
@@ -202,6 +227,32 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,tx-deemph-gen1 = <0x2d>;
|
||||
fsl,tx-deemph-gen2 = <0xf>;
|
||||
fsl,clkreq-unsupported;
|
||||
clocks = <&pcie0_refclk_gated>;
|
||||
clock-names = "ref";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk_gated>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
vpcie-supply = <®_pcie0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai3>;
|
||||
@@ -308,6 +359,12 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai3: sai3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
|
||||
|
||||
23
arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts
Normal file
23
arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts
Normal file
@@ -0,0 +1,23 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 or MIT)
|
||||
//
|
||||
// Copyright (c) 2021 emtrion GmbH
|
||||
// Author: Frank Erdrich <frank.erdrich@emtrion.com>
|
||||
//
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mm-emcon.dtsi"
|
||||
#include "imx8mm-emcon-avari.dtsi"
|
||||
|
||||
/ {
|
||||
model = "emtrion SoM emCON-MX8M mini on Avari";
|
||||
compatible = "emtrion,emcon-mx8mm-avari", "fsl,imx8mm";
|
||||
};
|
||||
|
||||
&lvds_backlight {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
139
arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi
Normal file
139
arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi
Normal file
@@ -0,0 +1,139 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 or MIT)
|
||||
//
|
||||
// Copyright (C) 2021 emtrion GmbH
|
||||
// Author: Frank Erdrich <frank.erdrich@emtrion.com>
|
||||
//
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
boardid = &boardID;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
reg_wall_5p0: regulator-wall5p0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "Main-Supply";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_base3p3: regulator-base3p3 {
|
||||
compatible = "regulator-fixed";
|
||||
vin-supply = <®_wall_5p0>;
|
||||
regulator-name = "3V3-avari";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_base1p5: regulator-base1p5 {
|
||||
compatible = "regulator-fixed";
|
||||
vin-supply = <®_base3p3>;
|
||||
regulator-name = "1V5-avari";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
reg_usb_otg: regulator-otgvbus {
|
||||
compatible = "regulator-fixed";
|
||||
vin-supply = <®_wall_5p0>;
|
||||
regulator-name = "OTG_VBUS";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
clk_codec: clock-codec {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "SGTL5000-Card";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,bitclock-master = <&codec_dai>;
|
||||
simple-audio-card,frame-master = <&codec_dai>;
|
||||
simple-audio-card,widgets = "Headphone", "Headphone Jack";
|
||||
simple-audio-card,routing = "Headphone Jack", "HP_OUT";
|
||||
|
||||
cpu_dai: simple-audio-card,cpu {
|
||||
sound-dai = <&sai2>;
|
||||
};
|
||||
|
||||
codec_dai: simple-audio-card,codec {
|
||||
sound-dai = <&sgtl5000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
sgtl5000: audio-codec@a {
|
||||
compatible = "fsl,sgtl5000";
|
||||
reg = <0x0a>;
|
||||
#sound-dai-cells = <0>;
|
||||
clocks = <&clk_codec>;
|
||||
VDDA-supply = <®_base3p3>;
|
||||
VDDIO-supply = <®_base3p3>;
|
||||
};
|
||||
|
||||
boardID: gpio@3a {
|
||||
compatible = "nxp,pca8574";
|
||||
reg = <0x3a>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
status = "okay";
|
||||
};
|
||||
627
arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi
Normal file
627
arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi
Normal file
@@ -0,0 +1,627 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 or MIT)
|
||||
//
|
||||
// Copyright 2018 NXP
|
||||
// Copyright (C) 2021 emtrion GmbH
|
||||
//
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
som_leds: leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_led>;
|
||||
|
||||
green {
|
||||
label = "som:green";
|
||||
gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
red {
|
||||
label = "som:red";
|
||||
gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
lvds_backlight: lvds-backlight {
|
||||
compatible = "pwm-backlight";
|
||||
enable-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
|
||||
pwms = <&pwm1 0 50000 0>;
|
||||
brightness-levels = <
|
||||
0 4 8 16 32 64 80 96 112
|
||||
128 144 160 176 250
|
||||
>;
|
||||
default-brightness-level = <9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
reg_usdhc1_vmmc: regulator-emmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "eMMC";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "sdcard_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2_reg>;
|
||||
};
|
||||
|
||||
&ecspi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
|
||||
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
|
||||
<&gpio5 13 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
fsl,magic-packet;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
reset-assert-us = <10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&flexspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexspi0>;
|
||||
pinctrl-1 = <&pinctrl_flexspi1>;
|
||||
status = "okay";
|
||||
|
||||
flash0: spi-flash@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
pinctrl_csi_pwn: csi-pwn-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1: ecspi1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
|
||||
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
|
||||
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ecspi1_cs: ecspi1-cs {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000
|
||||
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec1: fec1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexspi0: flexspi0-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
|
||||
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
|
||||
MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexspi1: flexspi1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x1c2
|
||||
MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_led: gpio-led-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19
|
||||
MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lvds: lvds-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x06
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
|
||||
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmic-irq {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
|
||||
MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6
|
||||
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
|
||||
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spdif1: spdif1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
|
||||
MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
|
||||
/* rts and cts */
|
||||
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
|
||||
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_gpio: usdhc1-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x41
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
/* no reset for sdhc2 interface */
|
||||
pinctrl_usdhc2_gpio: usdhc2-gpio-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
|
||||
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdog-grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
bd71847: pmic@4b {
|
||||
compatible = "rohm,bd71847";
|
||||
reg = <0x4b>;
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
|
||||
rohm,reset-snvs-powered;
|
||||
|
||||
regulators {
|
||||
buck1_reg: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
buck2_reg: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
rohm,dvs-run-voltage = <1000000>;
|
||||
rohm,dvs-idle-voltage = <900000>;
|
||||
};
|
||||
|
||||
buck3_reg: BUCK3 {
|
||||
// BUCK5 in datasheet
|
||||
regulator-name = "BUCK3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck4_reg: BUCK4 {
|
||||
// BUCK6 in datasheet
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck5_reg: BUCK5 {
|
||||
// BUCK7 in datasheet
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
buck6_reg: BUCK6 {
|
||||
// BUCK8 in datasheet
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo6_reg: LDO6 {
|
||||
regulator-name = "LDO6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rv1805: rtc@69 {
|
||||
compatible = "abracon,ab1805";
|
||||
reg = <0x69>;
|
||||
};
|
||||
};
|
||||
|
||||
&mu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
#sound-dai-cells = <0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai2>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
|
||||
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <12000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&spdif1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spdif1>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
|
||||
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <24576000>;
|
||||
clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
|
||||
<&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
|
||||
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
|
||||
<&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
|
||||
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
|
||||
<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
|
||||
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
|
||||
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&uart1 { /* console */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_UART1>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_UART2>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_UART4>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
dr_mode = "otg";
|
||||
over-current-active-low;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
|
||||
bus-width = <8>;
|
||||
vmmc-supply = <®_usdhc1_vmmc>;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
@@ -30,6 +31,23 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
reg_pcie0: regulator-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0_reg>;
|
||||
regulator-name = "MPCIE_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-usdhc2 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
@@ -296,6 +314,30 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,tx-deemph-gen1 = <0x2d>;
|
||||
fsl,tx-deemph-gen2 = <0xf>;
|
||||
clocks = <&pcie0_refclk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
vpcie-supply = <®_pcie0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai3>;
|
||||
@@ -413,6 +455,19 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
|
||||
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0_reg: pcie0reggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicirqgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
|
||||
|
||||
@@ -248,6 +248,7 @@
|
||||
#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x130 0x398 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11 0x130 0x398 0x000 0x7 0x0
|
||||
#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x134 0x39C 0x000 0x0 0x0
|
||||
#define MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x134 0x39C 0x000 0x2 0x0
|
||||
#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x134 0x39C 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12 0x134 0x39C 0x000 0x7 0x0
|
||||
#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x138 0x3A0 0x000 0x0 0x0
|
||||
@@ -279,7 +280,7 @@
|
||||
#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
|
||||
#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
|
||||
#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
|
||||
#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0
|
||||
#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53C 0x4 0x0
|
||||
#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
|
||||
#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
|
||||
@@ -486,7 +487,7 @@
|
||||
#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
|
||||
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0
|
||||
#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
|
||||
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2
|
||||
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2
|
||||
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0
|
||||
#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
|
||||
@@ -494,7 +495,7 @@
|
||||
#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
|
||||
#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
|
||||
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0
|
||||
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3
|
||||
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3
|
||||
#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
|
||||
#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
|
||||
#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0
|
||||
|
||||
304
arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts
Normal file
304
arch/arm64/boot/dts/freescale/imx8mm-prt8mm.dts
Normal file
@@ -0,0 +1,304 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2020 Protonic Holland
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/usb/pd.h>
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Protonic PRT8MM";
|
||||
compatible = "prt,prt8mm", "fsl,imx8mm";
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart4;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0x40000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
|
||||
debug-led0 {
|
||||
label = "DEBUG_LED0";
|
||||
gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
|
||||
debug-led1 {
|
||||
label = "DEBUG_LED1";
|
||||
gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "cpu";
|
||||
};
|
||||
};
|
||||
|
||||
sound-ssm2518 {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "ssm2518-audio";
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,frame-master = <&cpudai>;
|
||||
simple-audio-card,bitclock-master = <&cpudai>;
|
||||
|
||||
cpudai: simple-audio-card,cpu {
|
||||
sound-dai = <&sai3>;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&ssm2518>;
|
||||
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
ssm2518: audio-codec@34 {
|
||||
compatible = "adi,ssm2518";
|
||||
reg = <0x34>;
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
regulator@60 {
|
||||
compatible = "fcs,fan53555";
|
||||
reg = <0x60>;
|
||||
regulator-name = "0V9_CORE";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <980000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf85363";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
touchscreeen@5d {
|
||||
compatible = "goodix,gt911";
|
||||
reg = <0x5d>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_touchscreen>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <8 IRQ_TYPE_NONE>;
|
||||
irq-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
temp-sense@70 {
|
||||
compatible = "ti,tmp103";
|
||||
reg = <0x70>;
|
||||
};
|
||||
};
|
||||
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai3>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
|
||||
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
fsl,sai-mclk-direction-output;
|
||||
fsl,sai-asynchronous;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usbotg1>;
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
power-active-high;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
no-sdio;
|
||||
no-sd;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_gpio_leds: ledsgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x00
|
||||
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c3
|
||||
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai3: sai3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
|
||||
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_touchscreen: tsgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x80
|
||||
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x80
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart4: uart4grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
|
||||
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usbotg1: usbotg1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x000
|
||||
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
#include "imx8mm-tqma8mqml.dtsi"
|
||||
#include "mba8mx.dtsi"
|
||||
|
||||
@@ -58,6 +59,24 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
clocks = <&pcie0_refclk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sai3 {
|
||||
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
|
||||
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
|
||||
|
||||
@@ -227,6 +227,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
|
||||
@@ -5,6 +5,7 @@
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
@@ -33,6 +34,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
pps {
|
||||
compatible = "pps-gpio";
|
||||
pinctrl-names = "default";
|
||||
@@ -61,6 +68,20 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
|
||||
"", "dio1", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
@@ -87,6 +108,28 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
clocks = <&pcie0_refclk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GPS */
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
@@ -148,6 +191,12 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pps: ppsgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
|
||||
|
||||
@@ -0,0 +1,93 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Gateworks Corporation
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "imx8mm-pinfunc.h"
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&{/} {
|
||||
compatible = "gw,imx8mm-gw72xx-0x", "fsl,imx8mm";
|
||||
|
||||
reg_cam: regulator-cam {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_cam>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "reg_cam";
|
||||
gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
cam24m: cam24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "cam24m";
|
||||
};
|
||||
};
|
||||
|
||||
&csi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
imx219: sensor@10 {
|
||||
compatible = "sony,imx219";
|
||||
reg = <0x10>;
|
||||
clocks = <&cam24m>;
|
||||
VDIG-supply = <®_cam>;
|
||||
|
||||
port {
|
||||
/* MIPI CSI-2 bus endpoint */
|
||||
imx219_to_mipi_csi2: endpoint {
|
||||
remote-endpoint = <&imx8mm_mipi_csi_in>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies = /bits/ 64 <456000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_csi {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
imx8mm_mipi_csi_in: endpoint {
|
||||
remote-endpoint = <&imx219_to_mipi_csi2>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
imx8mm_mipi_csi_out: endpoint {
|
||||
remote-endpoint = <&csi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_reg_cam: regcamgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,53 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Gateworks Corporation
|
||||
*
|
||||
* GW72xx RS232 with RTS/CTS hardware flow control:
|
||||
* - GPIO4_0 rs485_en needs to be driven low (in-active)
|
||||
* - UART4_TX becomes RTS
|
||||
* - UART4_RX becomes CTS
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "imx8mm-pinfunc.h"
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&{/} {
|
||||
compatible = "gw,imx8mm-gw72xx-0x";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
rs485_en {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "rs485_en";
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
|
||||
cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
|
||||
MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,61 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Gateworks Corporation
|
||||
*
|
||||
* GW72xx RS422 (RS485 full duplex):
|
||||
* - GPIO1_0 rs485_term selects on-chip termination
|
||||
* - GPIO4_0 rs485_en needs to be driven high (active)
|
||||
* - GPIO4_2 rs485_hd needs to be driven low (in-active)
|
||||
* - UART4_TX is DE for RS485 transmitter
|
||||
* - RS485_EN needs to be pulled high
|
||||
* - RS485_HALF needs to be low
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "imx8mm-pinfunc.h"
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&{/} {
|
||||
compatible = "gw,imx8mm-gw72xx-0x";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
rs485_en {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "rs485_en";
|
||||
};
|
||||
|
||||
rs485_hd {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "rs485_hd";
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,61 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Gateworks Corporation
|
||||
*
|
||||
* GW72xx RS485 HD:
|
||||
* - GPIO1_0 rs485_term selects on-chip termination
|
||||
* - GPIO4_0 rs485_en needs to be driven high (active)
|
||||
* - GPIO4_2 rs485_hd needs to be driven high (active)
|
||||
* - UART4_TX is DE for RS485 transmitter
|
||||
* - RS485_EN needs to be pulled high
|
||||
* - RS485_HALF needs to be pulled high
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "imx8mm-pinfunc.h"
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&{/} {
|
||||
compatible = "gw,imx8mm-gw72xx-0x";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
rs485_en {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "rs485_en";
|
||||
};
|
||||
|
||||
rs485_hd {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "rs485_hd";
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -5,9 +5,11 @@
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet1 = ð1;
|
||||
usb0 = &usbotg1;
|
||||
usb1 = &usbotg2;
|
||||
};
|
||||
@@ -33,6 +35,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
pps {
|
||||
compatible = "pps-gpio";
|
||||
pinctrl-names = "default";
|
||||
@@ -80,6 +88,22 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
|
||||
"", "", "pci_usb_sel", "dio0",
|
||||
"", "dio1", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
|
||||
"mipi_gpio1", "", "", "pci_wdis#",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
@@ -106,6 +130,54 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
clocks = <&pcie0_refclk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcie@1,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcie@2,3 {
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eth1: pcie@5,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* off-board header */
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
@@ -198,6 +270,12 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pps: ppsgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
|
||||
|
||||
@@ -0,0 +1,93 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Gateworks Corporation
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "imx8mm-pinfunc.h"
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&{/} {
|
||||
compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm";
|
||||
|
||||
reg_cam: regulator-cam {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_cam>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "reg_cam";
|
||||
gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
cam24m: cam24m {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "cam24m";
|
||||
};
|
||||
};
|
||||
|
||||
&csi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
imx219: sensor@10 {
|
||||
compatible = "sony,imx219";
|
||||
reg = <0x10>;
|
||||
clocks = <&cam24m>;
|
||||
VDIG-supply = <®_cam>;
|
||||
|
||||
port {
|
||||
/* MIPI CSI-2 bus endpoint */
|
||||
imx219_to_mipi_csi2: endpoint {
|
||||
remote-endpoint = <&imx8mm_mipi_csi_in>;
|
||||
clock-lanes = <0>;
|
||||
data-lanes = <1 2>;
|
||||
link-frequencies = /bits/ 64 <456000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_csi {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
imx8mm_mipi_csi_in: endpoint {
|
||||
remote-endpoint = <&imx219_to_mipi_csi2>;
|
||||
data-lanes = <1 2>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
imx8mm_mipi_csi_out: endpoint {
|
||||
remote-endpoint = <&csi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_reg_cam: regcamgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x41
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,53 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Gateworks Corporation
|
||||
*
|
||||
* GW73xx RS232 with RTS/CTS hardware flow control:
|
||||
* - GPIO4_0 rs485_en needs to be driven low (in-active)
|
||||
* - UART4_TX becomes RTS
|
||||
* - UART4_RX becomes CTS
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "imx8mm-pinfunc.h"
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&{/} {
|
||||
compatible = "gw,imx8mm-gw73xx-0x";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
rs485_en {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "rs485_en";
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
rts-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
|
||||
cts-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
|
||||
MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x140
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,61 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2021 Gateworks Corporation
|
||||
*
|
||||
* GW73xx RS422 (RS485 full duplex):
|
||||
* - GPIO1_0 rs485_term selects on-chip termination
|
||||
* - GPIO4_0 rs485_en needs to be driven high (active)
|
||||
* - GPIO4_2 rs485_hd needs to be driven low (in-active)
|
||||
* - UART4_TX is DE for RS485 transmitter
|
||||
* - RS485_EN needs to be pulled high
|
||||
* - RS485_HALF needs to be low
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "imx8mm-pinfunc.h"
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&{/} {
|
||||
compatible = "gw,imx8mm-gw73xx-0x";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
rs485_en {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "rs485_en";
|
||||
};
|
||||
|
||||
rs485_hd {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "rs485_hd";
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,61 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2021 Gateworks Corporation
|
||||
*
|
||||
* GW73xx RS485 HD:
|
||||
* - GPIO1_0 rs485_term selects on-chip termination
|
||||
* - GPIO4_0 rs485_en needs to be driven high (active)
|
||||
* - GPIO4_2 rs485_hd needs to be driven high (active)
|
||||
* - UART4_TX is DE for RS485 transmitter
|
||||
* - RS485_EN needs to be pulled high
|
||||
* - RS485_HALF needs to be pulled high
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "imx8mm-pinfunc.h"
|
||||
|
||||
/dts-v1/;
|
||||
/plugin/;
|
||||
|
||||
&{/} {
|
||||
compatible = "gw,imx8mm-gw73xx-0x";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
rs485_en {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "rs485_en";
|
||||
};
|
||||
|
||||
rs485_hd {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "rs485_hd";
|
||||
};
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
rts-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x140
|
||||
>;
|
||||
};
|
||||
};
|
||||
@@ -5,9 +5,11 @@
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet1 = ð1;
|
||||
usb0 = &usbotg1;
|
||||
usb1 = &usbotg2;
|
||||
};
|
||||
@@ -33,6 +35,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
pps {
|
||||
compatible = "pps-gpio";
|
||||
pinctrl-names = "default";
|
||||
@@ -100,6 +108,22 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
|
||||
"", "", "pci_usb_sel", "dio0",
|
||||
"", "dio1", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
|
||||
"mipi_gpio1", "", "", "pci_wdis#",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
@@ -126,6 +150,54 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
clocks = <&pcie0_refclk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcie@1,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pcie@2,4 {
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eth1: pcie@6,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* off-board header */
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
@@ -241,6 +313,12 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pcie0grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pps: ppsgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
|
||||
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
@@ -179,6 +180,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
@@ -286,6 +293,29 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
|
||||
"", "uart1_rs232#", "dig1_in", "dig1_out",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names = "", "", "", "",
|
||||
"", "", "uart3_rs232#", "uart3_rs422#",
|
||||
"uart3_rs485#", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
|
||||
"", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpu_2d {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -644,6 +674,28 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
clocks = <&pcie0_refclk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pgc_gpu {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -820,6 +872,13 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pciegrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
|
||||
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
|
||||
|
||||
@@ -9,6 +9,7 @@
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/net/ti-dp83867.h>
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
@@ -17,6 +18,7 @@
|
||||
compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
|
||||
|
||||
aliases {
|
||||
ethernet1 = ð1;
|
||||
usb0 = &usbotg1;
|
||||
usb1 = &usbotg2;
|
||||
};
|
||||
@@ -128,6 +130,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
pps {
|
||||
compatible = "pps-gpio";
|
||||
pinctrl-names = "default";
|
||||
@@ -252,6 +260,43 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names = "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "m2_reset", "", "m2_wdis#",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-line-names = "", "", "", "", "", "", "", "",
|
||||
"uart2_en#", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names = "", "", "", "", "", "", "", "",
|
||||
"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
|
||||
"", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
|
||||
"", "uart1_term", "uart1_half", "app_gpio2",
|
||||
"mipi_gpio1", "", "", "";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
gpio-line-names = "", "", "", "mipi_gpio4",
|
||||
"mipi_gpio3", "mipi_gpio2", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
@@ -547,6 +592,42 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
clocks = <&clk IMX8MM_CLK_DUMMY>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
status = "okay";
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
eth1: pcie@1,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* off-board header */
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
@@ -647,7 +728,7 @@
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
|
||||
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
|
||||
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
|
||||
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
|
||||
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
|
||||
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
|
||||
@@ -737,6 +818,12 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pciegrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
|
||||
|
||||
836
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
Normal file
836
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
Normal file
@@ -0,0 +1,836 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright 2022 Gateworks Corporation
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/linux-event-codes.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gateworks Venice GW7903 i.MX8MM board";
|
||||
compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &fec1;
|
||||
usb0 = &usbotg1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart2;
|
||||
};
|
||||
|
||||
memory@40000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x40000000 0 0x80000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
user-pb {
|
||||
label = "user_pb";
|
||||
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <BTN_0>;
|
||||
};
|
||||
|
||||
user-pb1x {
|
||||
label = "user_pb1x";
|
||||
linux,code = <BTN_1>;
|
||||
interrupt-parent = <&gsc>;
|
||||
interrupts = <0>;
|
||||
};
|
||||
|
||||
key-erased {
|
||||
label = "key_erased";
|
||||
linux,code = <BTN_2>;
|
||||
interrupt-parent = <&gsc>;
|
||||
interrupts = <1>;
|
||||
};
|
||||
|
||||
eeprom-wp {
|
||||
label = "eeprom_wp";
|
||||
linux,code = <BTN_3>;
|
||||
interrupt-parent = <&gsc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
switch-hold {
|
||||
label = "switch_hold";
|
||||
linux,code = <BTN_5>;
|
||||
interrupt-parent = <&gsc>;
|
||||
interrupts = <7>;
|
||||
};
|
||||
};
|
||||
|
||||
led-controller {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_leds>;
|
||||
|
||||
led-0 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
label = "led01_red";
|
||||
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-1 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
label = "led01_grn";
|
||||
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-2 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
label = "led02_red";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-3 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
label = "led02_grn";
|
||||
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-4 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
label = "led03_red";
|
||||
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-5 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
label = "led03_grn";
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-6 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
label = "led04_red";
|
||||
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-7 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
label = "led04_grn";
|
||||
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-8 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
label = "led05_red";
|
||||
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-9 {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
label = "led05_grn";
|
||||
gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-a {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
label = "led06_red";
|
||||
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led-b {
|
||||
function = LED_FUNCTION_STATUS;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
label = "led06_grn";
|
||||
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "3P3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
&A53_0 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_1 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_2 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&A53_3 {
|
||||
cpu-supply = <&buck2>;
|
||||
};
|
||||
|
||||
&ddrc {
|
||||
operating-points-v2 = <&ddrc_opp_table>;
|
||||
|
||||
ddrc_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-25M {
|
||||
opp-hz = /bits/ 64 <25000000>;
|
||||
};
|
||||
|
||||
opp-100M {
|
||||
opp-hz = /bits/ 64 <100000000>;
|
||||
};
|
||||
|
||||
opp-750M {
|
||||
opp-hz = /bits/ 64 <750000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fec1>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <ðphy0>;
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
rx-internal-delay-ps = <2000>;
|
||||
tx-internal-delay-ps = <2500>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names = "", "", "", "", "", "", "", "",
|
||||
"", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
|
||||
"dig1_out#", "dig1_in", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
|
||||
"sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
status = "okay";
|
||||
|
||||
gsc: gsc@20 {
|
||||
compatible = "gw,gsc";
|
||||
reg = <0x20>;
|
||||
pinctrl-0 = <&pinctrl_gsc>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
adc {
|
||||
compatible = "gw,gsc-adc";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
channel@6 {
|
||||
gw,mode = <0>;
|
||||
reg = <0x06>;
|
||||
label = "temp";
|
||||
};
|
||||
|
||||
channel@8 {
|
||||
gw,mode = <1>;
|
||||
reg = <0x08>;
|
||||
label = "vdd_bat";
|
||||
};
|
||||
|
||||
channel@82 {
|
||||
gw,mode = <2>;
|
||||
reg = <0x82>;
|
||||
label = "vin";
|
||||
gw,voltage-divider-ohms = <22100 1000>;
|
||||
gw,voltage-offset-microvolt = <700000>;
|
||||
};
|
||||
|
||||
channel@84 {
|
||||
gw,mode = <2>;
|
||||
reg = <0x84>;
|
||||
label = "vdd_5p0";
|
||||
gw,voltage-divider-ohms = <10000 10000>;
|
||||
};
|
||||
|
||||
channel@86 {
|
||||
gw,mode = <2>;
|
||||
reg = <0x86>;
|
||||
label = "vdd_3p3";
|
||||
gw,voltage-divider-ohms = <10000 10000>;
|
||||
};
|
||||
|
||||
channel@88 {
|
||||
gw,mode = <2>;
|
||||
reg = <0x88>;
|
||||
label = "vdd_0p9";
|
||||
};
|
||||
|
||||
channel@8c {
|
||||
gw,mode = <2>;
|
||||
reg = <0x8c>;
|
||||
label = "vdd_soc";
|
||||
};
|
||||
|
||||
channel@8e {
|
||||
gw,mode = <2>;
|
||||
reg = <0x8e>;
|
||||
label = "vdd_arm";
|
||||
};
|
||||
|
||||
channel@90 {
|
||||
gw,mode = <2>;
|
||||
reg = <0x90>;
|
||||
label = "vdd_1p8";
|
||||
};
|
||||
|
||||
channel@92 {
|
||||
gw,mode = <2>;
|
||||
reg = <0x92>;
|
||||
label = "vdd_dram";
|
||||
};
|
||||
|
||||
channel@a2 {
|
||||
gw,mode = <2>;
|
||||
reg = <0xa2>;
|
||||
label = "vdd_gsc";
|
||||
gw,voltage-divider-ohms = <10000 10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio: gpio@23 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x23>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-parent = <&gsc>;
|
||||
interrupts = <4>;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
eeprom@51 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x51>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
eeprom@53 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x53>;
|
||||
pagesize = <16>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1672";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
pmic@4b {
|
||||
compatible = "rohm,bd71847";
|
||||
reg = <0x4b>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
|
||||
rohm,reset-snvs-powered;
|
||||
#clock-cells = <0>;
|
||||
clocks = <&osc_32k 0>;
|
||||
clock-output-names = "clk-32k-out";
|
||||
|
||||
regulators {
|
||||
/* vdd_soc: 0.805-0.900V (typ=0.8V) */
|
||||
BUCK1 {
|
||||
regulator-name = "buck1";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
};
|
||||
|
||||
/* vdd_arm: 0.805-1.0V (typ=0.9V) */
|
||||
buck2: BUCK2 {
|
||||
regulator-name = "buck2";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <1250>;
|
||||
rohm,dvs-run-voltage = <1000000>;
|
||||
rohm,dvs-idle-voltage = <900000>;
|
||||
};
|
||||
|
||||
/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
|
||||
BUCK3 {
|
||||
regulator-name = "buck3";
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdd_3p3 */
|
||||
BUCK4 {
|
||||
regulator-name = "buck4";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdd_1p8 */
|
||||
BUCK5 {
|
||||
regulator-name = "buck5";
|
||||
regulator-min-microvolt = <1605000>;
|
||||
regulator-max-microvolt = <1995000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdd_dram */
|
||||
BUCK6 {
|
||||
regulator-name = "buck6";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* nvcc_snvs_1p8 */
|
||||
LDO1 {
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdd_snvs_0p8 */
|
||||
LDO2 {
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdda_1p8 */
|
||||
LDO3 {
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
LDO4 {
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
LDO6 {
|
||||
regulator-name = "ldo6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
accelerometer@19 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_accel>;
|
||||
compatible = "st,lis2de12";
|
||||
reg = <0x19>;
|
||||
st,drdy-int-pin = <1>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
|
||||
interrupt-names = "INT1";
|
||||
};
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
|
||||
fsl,clkreq-unsupported;
|
||||
clocks = <&pcie0_refclk>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie0>;
|
||||
reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_bus";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
|
||||
<&clk IMX8MM_CLK_PCIE1_CTRL>;
|
||||
assigned-clock-rates = <10000000>, <250000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
|
||||
<&clk IMX8MM_SYS_PLL2_250M>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pgc_mipi {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* off-board RS232/RS485/RS422 */
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
|
||||
dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
||||
dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
|
||||
uart-has-rtscts;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* console */
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* microSD */
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&usdhc3 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog>;
|
||||
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
|
||||
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
|
||||
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
|
||||
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
|
||||
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
|
||||
MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
|
||||
MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
|
||||
MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
|
||||
MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
|
||||
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
|
||||
MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_accel: accelgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
|
||||
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gsc: gscgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_leds: gpioledgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
|
||||
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
|
||||
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
|
||||
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
|
||||
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
|
||||
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
|
||||
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
|
||||
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
|
||||
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie0: pciegrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
|
||||
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
|
||||
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
150
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
Normal file
150
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
Normal file
@@ -0,0 +1,150 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/ {
|
||||
sound_card: sound-card {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,bitclock-master = <&dailink_master>;
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,frame-master = <&dailink_master>;
|
||||
simple-audio-card,name = "imx8mm-wm8904";
|
||||
simple-audio-card,routing =
|
||||
"Headphone Jack", "HPOUTL",
|
||||
"Headphone Jack", "HPOUTR",
|
||||
"IN2L", "Line In Jack",
|
||||
"IN2R", "Line In Jack",
|
||||
"Headphone Jack", "MICBIAS",
|
||||
"IN1L", "Headphone Jack";
|
||||
simple-audio-card,widgets =
|
||||
"Microphone", "Headphone Jack",
|
||||
"Headphone", "Headphone Jack",
|
||||
"Line", "Line In Jack";
|
||||
|
||||
dailink_master: simple-audio-card,codec {
|
||||
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
|
||||
sound-dai = <&wm8904_1a>;
|
||||
};
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&sai2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin SPI_1 */
|
||||
&ecspi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* EEPROM on display adapter boards */
|
||||
&eeprom_display_adapter {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* EEPROM on Verdin Development board */
|
||||
&eeprom_carrier_board {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin QSPI_1 */
|
||||
&flexspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Current measurement into module VCC */
|
||||
&hwmon {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hwmon_temp {
|
||||
vs-supply = <®_1p8v>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin I2C_1 */
|
||||
&i2c4 {
|
||||
status = "okay";
|
||||
|
||||
/* Audio Codec */
|
||||
wm8904_1a: audio-codec@1a {
|
||||
compatible = "wlf,wm8904";
|
||||
AVDD-supply = <®_3p3v>;
|
||||
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
|
||||
clock-names = "mclk";
|
||||
CPVDD-supply = <®_3p3v>;
|
||||
DBVDD-supply = <®_3p3v>;
|
||||
DCVDD-supply = <®_3p3v>;
|
||||
MICVDD-supply = <®_3p3v>;
|
||||
reg = <0x1a>;
|
||||
#sound-dai-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin PCIE_1 */
|
||||
&pcie0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin PWM_3_DSI */
|
||||
&pwm1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin PWM_1 */
|
||||
&pwm2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin PWM_2 */
|
||||
&pwm3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* VERDIN I2S_1 */
|
||||
&sai2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin UART_3 */
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin UART_1 */
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin UART_2 */
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin USB_1 */
|
||||
&usbotg1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin USB_2 */
|
||||
&usbotg2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin SD_1 */
|
||||
&usdhc2 {
|
||||
status = "okay";
|
||||
};
|
||||
67
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
Normal file
67
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
Normal file
@@ -0,0 +1,67 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
#include "imx8mm-verdin-dahlia.dtsi"
|
||||
|
||||
/ {
|
||||
sound_card: sound-card {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,bitclock-master = <&dailink_master>;
|
||||
simple-audio-card,format = "i2s";
|
||||
simple-audio-card,frame-master = <&dailink_master>;
|
||||
simple-audio-card,name = "imx8mm-nau8822";
|
||||
simple-audio-card,routing =
|
||||
"Headphones", "LHP",
|
||||
"Headphones", "RHP",
|
||||
"Speaker", "LSPK",
|
||||
"Speaker", "RSPK",
|
||||
"Line Out", "AUXOUT1",
|
||||
"Line Out", "AUXOUT2",
|
||||
"LAUX", "Line In",
|
||||
"RAUX", "Line In",
|
||||
"LMICP", "Mic In",
|
||||
"RMICP", "Mic In";
|
||||
simple-audio-card,widgets =
|
||||
"Headphones", "Headphones",
|
||||
"Line Out", "Line Out",
|
||||
"Speaker", "Speaker",
|
||||
"Microphone", "Mic In",
|
||||
"Line", "Line In";
|
||||
|
||||
dailink_master: simple-audio-card,codec {
|
||||
clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
|
||||
sound-dai = <&nau8822_1a>;
|
||||
};
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&sai2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio_expander_21 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Verdin I2C_1 */
|
||||
&i2c4 {
|
||||
/* Audio Codec */
|
||||
nau8822_1a: audio-codec@1a {
|
||||
compatible = "nuvoton,nau8822";
|
||||
reg = <0x1a>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Verdin UART_1, connector X50 through RS485 transceiver */
|
||||
&uart2 {
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rts-active-low;
|
||||
rs485-rx-during-tx;
|
||||
};
|
||||
|
||||
/* Limit frequency on dev board due to long traces and bad signal integrity */
|
||||
&usdhc2 {
|
||||
max-frequency = <100000000>;
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mm-verdin.dtsi"
|
||||
#include "imx8mm-verdin-nonwifi.dtsi"
|
||||
#include "imx8mm-verdin-dahlia.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Verdin iMX8M Mini on Dahlia Board";
|
||||
compatible = "toradex,verdin-imx8mm-nonwifi-dahlia",
|
||||
"toradex,verdin-imx8mm-nonwifi",
|
||||
"toradex,verdin-imx8mm",
|
||||
"fsl,imx8mm";
|
||||
};
|
||||
18
arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts
Normal file
18
arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-dev.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mm-verdin.dtsi"
|
||||
#include "imx8mm-verdin-nonwifi.dtsi"
|
||||
#include "imx8mm-verdin-dev.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Verdin iMX8M Mini on Verdin Development Board";
|
||||
compatible = "toradex,verdin-imx8mm-nonwifi-dev",
|
||||
"toradex,verdin-imx8mm-nonwifi",
|
||||
"toradex,verdin-imx8mm",
|
||||
"fsl,imx8mm";
|
||||
};
|
||||
75
arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
Normal file
75
arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi.dtsi
Normal file
@@ -0,0 +1,75 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
&gpio3 {
|
||||
gpio-line-names = "SODIMM_52",
|
||||
"SODIMM_54",
|
||||
"SODIMM_64",
|
||||
"SODIMM_21",
|
||||
"SODIMM_206",
|
||||
"SODIMM_76",
|
||||
"SODIMM_56",
|
||||
"SODIMM_58",
|
||||
"SODIMM_60",
|
||||
"SODIMM_62",
|
||||
"SODIMM_162",
|
||||
"SODIMM_164",
|
||||
"SODIMM_166",
|
||||
"SODIMM_168",
|
||||
"SODIMM_66",
|
||||
"SODIMM_17",
|
||||
"",
|
||||
"SODIMM_156",
|
||||
"SODIMM_160",
|
||||
"SODIMM_244",
|
||||
"",
|
||||
"SODIMM_48",
|
||||
"SODIMM_44",
|
||||
"SODIMM_42",
|
||||
"SODIMM_46";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names = "SODIMM_102",
|
||||
"SODIMM_90",
|
||||
"SODIMM_92",
|
||||
"SODIMM_94",
|
||||
"SODIMM_96",
|
||||
"SODIMM_100",
|
||||
"SODIMM_148",
|
||||
"SODIMM_152",
|
||||
"SODIMM_154",
|
||||
"SODIMM_174",
|
||||
"SODIMM_120",
|
||||
"SODIMM_104",
|
||||
"SODIMM_106",
|
||||
"SODIMM_108",
|
||||
"SODIMM_112",
|
||||
"SODIMM_114",
|
||||
"SODIMM_116",
|
||||
"SODIMM_150",
|
||||
"SODIMM_118",
|
||||
"",
|
||||
"SODIMM_88",
|
||||
"SODIMM_149",
|
||||
"SODIMM_147",
|
||||
"SODIMM_36",
|
||||
"SODIMM_32",
|
||||
"SODIMM_30",
|
||||
"SODIMM_34",
|
||||
"SODIMM_38",
|
||||
"SODIMM_252",
|
||||
"SODIMM_133",
|
||||
"SODIMM_135",
|
||||
"SODIMM_129";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
||||
};
|
||||
18
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts
Normal file
18
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mm-verdin.dtsi"
|
||||
#include "imx8mm-verdin-wifi.dtsi"
|
||||
#include "imx8mm-verdin-dahlia.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Verdin iMX8M Mini WB on Dahlia Board";
|
||||
compatible = "toradex,verdin-imx8mm-wifi-dahlia",
|
||||
"toradex,verdin-imx8mm-wifi",
|
||||
"toradex,verdin-imx8mm",
|
||||
"fsl,imx8mm";
|
||||
};
|
||||
18
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts
Normal file
18
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dev.dts
Normal file
@@ -0,0 +1,18 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx8mm-verdin.dtsi"
|
||||
#include "imx8mm-verdin-wifi.dtsi"
|
||||
#include "imx8mm-verdin-dev.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Toradex Verdin iMX8M Mini WB on Verdin Development Board";
|
||||
compatible = "toradex,verdin-imx8mm-wifi-dev",
|
||||
"toradex,verdin-imx8mm-wifi",
|
||||
"toradex,verdin-imx8mm",
|
||||
"fsl,imx8mm";
|
||||
};
|
||||
94
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
Normal file
94
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi
Normal file
@@ -0,0 +1,94 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
/*
|
||||
* Copyright 2022 Toradex
|
||||
*/
|
||||
|
||||
/ {
|
||||
reg_wifi_en: regulator-wifi-en {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wifi_pwr_en>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-name = "PDn_AW-CM276NF";
|
||||
startup-delay-us = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* On-module Wi-Fi */
|
||||
&usdhc3 {
|
||||
bus-width = <4>;
|
||||
keep-power-in-suspend;
|
||||
non-removable;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>;
|
||||
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>;
|
||||
vmmc-supply = <®_wifi_en>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
gpio-line-names = "SODIMM_52",
|
||||
"SODIMM_54",
|
||||
"SODIMM_64",
|
||||
"SODIMM_21",
|
||||
"SODIMM_206",
|
||||
"SODIMM_76",
|
||||
"SODIMM_56",
|
||||
"SODIMM_58",
|
||||
"SODIMM_60",
|
||||
"SODIMM_62",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"SODIMM_66",
|
||||
"SODIMM_17",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"SODIMM_244",
|
||||
"",
|
||||
"SODIMM_48",
|
||||
"SODIMM_44",
|
||||
"SODIMM_42",
|
||||
"SODIMM_46";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names = "SODIMM_102",
|
||||
"SODIMM_90",
|
||||
"SODIMM_92",
|
||||
"SODIMM_94",
|
||||
"SODIMM_96",
|
||||
"SODIMM_100",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"",
|
||||
"SODIMM_120",
|
||||
"SODIMM_104",
|
||||
"SODIMM_106",
|
||||
"SODIMM_108",
|
||||
"SODIMM_112",
|
||||
"SODIMM_114",
|
||||
"SODIMM_116",
|
||||
"",
|
||||
"SODIMM_118",
|
||||
"",
|
||||
"SODIMM_88",
|
||||
"SODIMM_149",
|
||||
"SODIMM_147",
|
||||
"SODIMM_36",
|
||||
"SODIMM_32",
|
||||
"SODIMM_30",
|
||||
"SODIMM_34",
|
||||
"SODIMM_38",
|
||||
"SODIMM_252",
|
||||
"SODIMM_133",
|
||||
"SODIMM_135",
|
||||
"SODIMM_129";
|
||||
};
|
||||
1264
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
Normal file
1264
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
Normal file
File diff suppressed because it is too large
Load Diff
@@ -548,7 +548,7 @@
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@30340000 {
|
||||
compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
|
||||
compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
|
||||
reg = <0x30340000 0x10000>;
|
||||
};
|
||||
|
||||
@@ -1211,6 +1211,19 @@
|
||||
reg = <0x32e50200 0x200>;
|
||||
};
|
||||
|
||||
pcie_phy: pcie-phy@32f00000 {
|
||||
compatible = "fsl,imx8mm-pcie-phy";
|
||||
reg = <0x32f00000 0x10000>;
|
||||
clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
|
||||
clock-names = "ref";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
|
||||
assigned-clock-rates = <100000000>;
|
||||
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
|
||||
resets = <&src IMX8MQ_RESET_PCIEPHY>;
|
||||
reset-names = "pciephy";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dma_apbh: dma-controller@33000000 {
|
||||
@@ -1242,6 +1255,37 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie0: pcie@33800000 {
|
||||
compatible = "fsl,imx8mm-pcie";
|
||||
reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
|
||||
reg-names = "dbi", "config";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
bus-range = <0x00 0xff>;
|
||||
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
|
||||
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
|
||||
num-lanes = <1>;
|
||||
num-viewport = <4>;
|
||||
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "msi";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,max-link-speed = <2>;
|
||||
linux,pci-domain = <0>;
|
||||
power-domains = <&pgc_pcie>;
|
||||
resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
|
||||
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
|
||||
reset-names = "apps", "turnoff";
|
||||
phys = <&pcie_phy>;
|
||||
phy-names = "pcie-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu_3d: gpu@38000000 {
|
||||
compatible = "vivante,gc";
|
||||
reg = <0x38000000 0x8000>;
|
||||
@@ -1273,6 +1317,22 @@
|
||||
power-domains = <&pgc_gpu>;
|
||||
};
|
||||
|
||||
vpu_g1: video-codec@38300000 {
|
||||
compatible = "nxp,imx8mm-vpu-g1";
|
||||
reg = <0x38300000 0x10000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
|
||||
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
|
||||
};
|
||||
|
||||
vpu_g2: video-codec@38310000 {
|
||||
compatible = "nxp,imx8mq-vpu-g2";
|
||||
reg = <0x38310000 0x10000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
|
||||
power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
|
||||
};
|
||||
|
||||
vpu_blk_ctrl: blk-ctrl@38330000 {
|
||||
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
|
||||
reg = <0x38330000 0x100>;
|
||||
@@ -1283,6 +1343,12 @@
|
||||
<&clk IMX8MM_CLK_VPU_G2_ROOT>,
|
||||
<&clk IMX8MM_CLK_VPU_H1_ROOT>;
|
||||
clock-names = "g1", "g2", "h1";
|
||||
assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
|
||||
<&clk IMX8MM_CLK_VPU_G2>;
|
||||
assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
|
||||
<&clk IMX8MM_VPU_PLL_OUT>;
|
||||
assigned-clock-rates = <600000000>,
|
||||
<600000000>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
@@ -220,6 +220,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
&disp_blk_ctrl {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* off-board header */
|
||||
&ecspi2 {
|
||||
pinctrl-names = "default";
|
||||
@@ -251,6 +255,47 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names = "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "m2_reset", "", "m2_wdis#",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-line-names = "", "", "", "", "", "", "", "",
|
||||
"uart2_en#", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
gpio-line-names = "", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "app_gpio1", "", "uart1_rs485",
|
||||
"", "uart1_term", "uart1_half", "app_gpio2",
|
||||
"mipi_gpio1", "", "", "";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
gpio-line-names = "", "", "", "mipi_gpio4",
|
||||
"mipi_gpio3", "mipi_gpio2", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
@@ -546,6 +591,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pgc_gpumix {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* off-board header */
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
@@ -633,7 +682,7 @@
|
||||
pinctrl_hog: hoggrp {
|
||||
fsl,pins = <
|
||||
MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
|
||||
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
|
||||
MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
|
||||
MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
|
||||
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
|
||||
MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
|
||||
|
||||
@@ -4,6 +4,8 @@
|
||||
*/
|
||||
|
||||
#include <dt-bindings/clock/imx8mn-clock.h>
|
||||
#include <dt-bindings/power/imx8mn-power.h>
|
||||
#include <dt-bindings/reset/imx8mq-reset.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
@@ -640,6 +642,53 @@
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
gpc: gpc@303a0000 {
|
||||
compatible = "fsl,imx8mn-gpc";
|
||||
reg = <0x303a0000 0x10000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pgc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pgc_hsiomix: power-domain@0 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>;
|
||||
clocks = <&clk IMX8MN_CLK_USB_BUS>;
|
||||
};
|
||||
|
||||
pgc_otg1: power-domain@1 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MN_POWER_DOMAIN_OTG1>;
|
||||
power-domains = <&pgc_hsiomix>;
|
||||
};
|
||||
|
||||
pgc_gpumix: power-domain@2 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MN_POWER_DOMAIN_GPUMIX>;
|
||||
clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>,
|
||||
<&clk IMX8MN_CLK_GPU_SHADER>,
|
||||
<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
|
||||
<&clk IMX8MN_CLK_GPU_AHB>;
|
||||
resets = <&src IMX8MQ_RESET_GPU_RESET>;
|
||||
};
|
||||
|
||||
pgc_dispmix: power-domain@3 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MN_POWER_DOMAIN_DISPMIX>;
|
||||
clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_APB_ROOT>;
|
||||
};
|
||||
|
||||
pgc_mipi: power-domain@4 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8MN_POWER_DOMAIN_MIPI>;
|
||||
power-domains = <&pgc_dispmix>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
aips2: bus@30400000 {
|
||||
@@ -989,6 +1038,34 @@
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
disp_blk_ctrl: blk-ctrl@32e28000 {
|
||||
compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
|
||||
reg = <0x32e28000 0x100>;
|
||||
power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
|
||||
<&pgc_dispmix>, <&pgc_mipi>,
|
||||
<&pgc_mipi>;
|
||||
power-domain-names = "bus", "isi",
|
||||
"lcdif", "mipi-dsi",
|
||||
"mipi-csi";
|
||||
clocks = <&clk IMX8MN_CLK_DISP_AXI>,
|
||||
<&clk IMX8MN_CLK_DISP_APB>,
|
||||
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_AXI_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_APB_ROOT>,
|
||||
<&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
|
||||
<&clk IMX8MN_CLK_DSI_CORE>,
|
||||
<&clk IMX8MN_CLK_DSI_PHY_REF>,
|
||||
<&clk IMX8MN_CLK_CSI1_PHY_REF>,
|
||||
<&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
|
||||
clock-names = "disp_axi", "disp_apb",
|
||||
"disp_axi_root", "disp_apb_root",
|
||||
"lcdif-axi", "lcdif-apb", "lcdif-pix",
|
||||
"dsi-pclk", "dsi-ref",
|
||||
"csi-aclk", "csi-pclk";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
usbotg1: usb@32e40000 {
|
||||
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
|
||||
reg = <0x32e40000 0x200>;
|
||||
@@ -999,6 +1076,7 @@
|
||||
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
|
||||
phys = <&usbphynop1>;
|
||||
fsl,usbmisc = <&usbmisc1 0>;
|
||||
power-domains = <&pgc_otg1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -1038,6 +1116,32 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpu: gpu@38000000 {
|
||||
compatible = "vivante,gc";
|
||||
reg = <0x38000000 0x8000>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MN_CLK_GPU_AHB>,
|
||||
<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
|
||||
<&clk IMX8MN_CLK_GPU_CORE_ROOT>,
|
||||
<&clk IMX8MN_CLK_GPU_SHADER>;
|
||||
clock-names = "reg", "bus", "core", "shader";
|
||||
assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
|
||||
<&clk IMX8MN_CLK_GPU_SHADER>,
|
||||
<&clk IMX8MN_CLK_GPU_AXI>,
|
||||
<&clk IMX8MN_CLK_GPU_AHB>,
|
||||
<&clk IMX8MN_GPU_PLL>;
|
||||
assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
|
||||
<&clk IMX8MN_GPU_PLL_OUT>,
|
||||
<&clk IMX8MN_SYS_PLL1_800M>,
|
||||
<&clk IMX8MN_SYS_PLL1_800M>;
|
||||
assigned-clock-rates = <400000000>,
|
||||
<400000000>,
|
||||
<800000000>,
|
||||
<400000000>,
|
||||
<1200000000>;
|
||||
power-domains = <&pgc_gpumix>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@38800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0x38800000 0x10000>,
|
||||
|
||||
@@ -294,9 +294,46 @@
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pca6416_int>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
|
||||
gpio-line-names = "EXT_PWREN1",
|
||||
"EXT_PWREN2",
|
||||
"CAN1/I2C5_SEL",
|
||||
"PDM/CAN2_SEL",
|
||||
"FAN_EN",
|
||||
"PWR_MEAS_IO1",
|
||||
"PWR_MEAS_IO2",
|
||||
"EXP_P0_7",
|
||||
"EXP_P1_0",
|
||||
"EXP_P1_1",
|
||||
"EXP_P1_2",
|
||||
"EXP_P1_3",
|
||||
"EXP_P1_4",
|
||||
"EXP_P1_5",
|
||||
"EXP_P1_6",
|
||||
"EXP_P1_7";
|
||||
};
|
||||
};
|
||||
|
||||
/* I2C on expansion connector J22. */
|
||||
&i2c5 {
|
||||
clock-frequency = <100000>; /* Lower clock speed for external bus. */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c5>;
|
||||
status = "disabled"; /* can1 pins conflict with i2c5 */
|
||||
|
||||
/* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
|
||||
* LOW: CAN1 (default, pull-down)
|
||||
* HIGH: I2C5
|
||||
* You need to set it to high to enable I2C5 (for example, add gpio-hog
|
||||
* in pca6416 node).
|
||||
*/
|
||||
};
|
||||
|
||||
&snvs_pwrkey {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -442,12 +479,25 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c5: i2c5grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
|
||||
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pca6416_int: pca6416_int_grp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
|
||||
|
||||
@@ -60,6 +60,7 @@
|
||||
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
|
||||
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
|
||||
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
|
||||
ti,min-output-impedance;
|
||||
enet-phy-lane-no-swap;
|
||||
};
|
||||
};
|
||||
@@ -113,6 +114,8 @@
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
nxp,dvs-run-voltage = <950000>;
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
};
|
||||
|
||||
buck4: BUCK4 {
|
||||
@@ -167,14 +170,14 @@
|
||||
regulator-compatible = "LDO4";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo5: LDO5 {
|
||||
regulator-compatible = "LDO5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -194,6 +197,8 @@
|
||||
|
||||
/* eMMC */
|
||||
&usdhc3 {
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
|
||||
assigned-clock-rates = <400000000>;
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc3>;
|
||||
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
||||
@@ -221,12 +226,12 @@
|
||||
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
|
||||
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
|
||||
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
|
||||
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
|
||||
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
|
||||
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
|
||||
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
|
||||
MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
|
||||
>;
|
||||
};
|
||||
@@ -298,21 +303,21 @@
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xe6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -958,6 +958,7 @@
|
||||
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3_1: usb@32f10108 {
|
||||
|
||||
@@ -27,6 +27,17 @@
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
reg_pcie1: regulator-pcie {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie1_reg>;
|
||||
regulator-name = "MPCIE_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
reg_usdhc2_vmmc: regulator-vsd-3v3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_usdhc2>;
|
||||
@@ -123,6 +134,7 @@
|
||||
|
||||
&ddrc {
|
||||
operating-points-v2 = <&ddrc_opp_table>;
|
||||
status = "okay";
|
||||
|
||||
ddrc_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
@@ -327,6 +339,20 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie1>;
|
||||
reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
|
||||
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
|
||||
<&clk IMX8MQ_CLK_PCIE2_AUX>,
|
||||
<&clk IMX8MQ_CLK_PCIE2_PHY>,
|
||||
<&pcie0_refclk>;
|
||||
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
|
||||
vpcie-supply = <®_pcie1>;
|
||||
vph-supply = <&vgen5_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pgc_gpu {
|
||||
power-supply = <&sw1a_reg>;
|
||||
};
|
||||
@@ -482,6 +508,19 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie1: pcie1grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
|
||||
MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcie1_reg: pcie1reggrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
|
||||
|
||||
@@ -278,6 +278,7 @@
|
||||
|
||||
&ddrc {
|
||||
operating-points-v2 = <&ddrc_opp_table>;
|
||||
status = "okay";
|
||||
|
||||
ddrc_opp_table: opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
@@ -14,6 +14,30 @@
|
||||
compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
|
||||
chassis-type = "laptop";
|
||||
|
||||
backlight: backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_backlight>;
|
||||
pwms = <&pwm2 0 10000>;
|
||||
power-supply = <®_main_usb>;
|
||||
enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||
brightness-levels = <0 32 64 128 160 200 255>;
|
||||
default-brightness-level = <6>;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "innolux,n125hce-gn1", "simple-panel";
|
||||
power-supply = <®_main_3v3>;
|
||||
backlight = <&backlight>;
|
||||
no-hpd;
|
||||
|
||||
port {
|
||||
panel_in: endpoint {
|
||||
remote-endpoint = <&edp_bridge_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie1_refclk: clock-pcie1-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
@@ -42,6 +66,22 @@
|
||||
vin-supply = <®_main_5v>;
|
||||
};
|
||||
|
||||
reg_main_1v8: regulator-main-1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1V8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <®_main_3v3>;
|
||||
};
|
||||
|
||||
reg_main_1v2: regulator-main-1v2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1V2";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
vin-supply = <®_main_5v>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx-audio-wm8960";
|
||||
audio-cpu = <&sai2>;
|
||||
@@ -61,6 +101,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
&dphy {
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
|
||||
assigned-clock-rates = <25000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -84,6 +131,67 @@
|
||||
};
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c4>;
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
edp_bridge: bridge@2c {
|
||||
compatible = "ti,sn65dsi86";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_edp_bridge>;
|
||||
reg = <0x2c>;
|
||||
enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
|
||||
vccio-supply = <®_main_1v8>;
|
||||
vpll-supply = <®_main_1v8>;
|
||||
vcca-supply = <®_main_1v2>;
|
||||
vcc-supply = <®_main_1v2>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
edp_bridge_in: endpoint {
|
||||
remote-endpoint = <&mipi_dsi_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
edp_bridge_out: endpoint {
|
||||
remote-endpoint = <&panel_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
|
||||
/delete-property/assigned-clock-rates;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
|
||||
mipi_dsi_out: endpoint {
|
||||
remote-endpoint = <&edp_bridge_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcie1>;
|
||||
@@ -96,6 +204,13 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
®_1p8v {
|
||||
vin-supply = <®_main_5v>;
|
||||
};
|
||||
@@ -169,10 +284,29 @@
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_backlight: backlightgrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_edp_bridge: edpbridgegrp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
|
||||
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000022
|
||||
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000022
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c4: i2c4grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000022
|
||||
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000022
|
||||
>;
|
||||
};
|
||||
|
||||
@@ -182,6 +316,12 @@
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
|
||||
|
||||
@@ -272,10 +272,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vpu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Attention: wdog reset forcing POR needs baseboard support */
|
||||
&wdog1 {
|
||||
status = "okay";
|
||||
|
||||
@@ -737,7 +737,21 @@
|
||||
pgc_vpu: power-domain@6 {
|
||||
#power-domain-cells = <0>;
|
||||
reg = <IMX8M_POWER_DOMAIN_VPU>;
|
||||
clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
|
||||
clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>,
|
||||
<&clk IMX8MQ_CLK_VPU_G1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_VPU_G2_ROOT>;
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
|
||||
<&clk IMX8MQ_CLK_VPU_G2>,
|
||||
<&clk IMX8MQ_CLK_VPU_BUS>,
|
||||
<&clk IMX8MQ_VPU_PLL_BYPASS>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
|
||||
<&clk IMX8MQ_VPU_PLL_OUT>,
|
||||
<&clk IMX8MQ_SYS1_PLL_800M>,
|
||||
<&clk IMX8MQ_VPU_PLL>;
|
||||
assigned-clock-rates = <600000000>,
|
||||
<600000000>,
|
||||
<800000000>,
|
||||
<0>;
|
||||
};
|
||||
|
||||
pgc_disp: power-domain@7 {
|
||||
@@ -1457,30 +1471,31 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vpu: video-codec@38300000 {
|
||||
compatible = "nxp,imx8mq-vpu";
|
||||
reg = <0x38300000 0x10000>,
|
||||
<0x38310000 0x10000>,
|
||||
<0x38320000 0x10000>;
|
||||
reg-names = "g1", "g2", "ctrl";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "g1", "g2";
|
||||
vpu_g1: video-codec@38300000 {
|
||||
compatible = "nxp,imx8mq-vpu-g1";
|
||||
reg = <0x38300000 0x10000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>;
|
||||
power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
|
||||
};
|
||||
|
||||
vpu_g2: video-codec@38310000 {
|
||||
compatible = "nxp,imx8mq-vpu-g2";
|
||||
reg = <0x38310000 0x10000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>;
|
||||
power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
|
||||
};
|
||||
|
||||
vpu_blk_ctrl: blk-ctrl@38320000 {
|
||||
compatible = "fsl,imx8mq-vpu-blk-ctrl";
|
||||
reg = <0x38320000 0x100>;
|
||||
power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
|
||||
power-domain-names = "bus", "g1", "g2";
|
||||
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
|
||||
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
|
||||
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
|
||||
clock-names = "g1", "g2", "bus";
|
||||
assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
|
||||
<&clk IMX8MQ_CLK_VPU_G2>,
|
||||
<&clk IMX8MQ_CLK_VPU_BUS>,
|
||||
<&clk IMX8MQ_VPU_PLL_BYPASS>;
|
||||
assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
|
||||
<&clk IMX8MQ_VPU_PLL_OUT>,
|
||||
<&clk IMX8MQ_SYS1_PLL_800M>,
|
||||
<&clk IMX8MQ_VPU_PLL>;
|
||||
assigned-clock-rates = <600000000>, <600000000>,
|
||||
<800000000>, <0>;
|
||||
power-domains = <&pgc_vpu>;
|
||||
<&clk IMX8MQ_CLK_VPU_G2_ROOT>;
|
||||
clock-names = "g1", "g2";
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
pcie0: pcie@33800000 {
|
||||
@@ -1579,6 +1594,7 @@
|
||||
<&clk IMX8MQ_DRAM_PLL_OUT>,
|
||||
<&clk IMX8MQ_CLK_DRAM_ALT>,
|
||||
<&clk IMX8MQ_CLK_DRAM_APB>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ddr-pmu@3d800000 {
|
||||
|
||||
@@ -19,3 +19,7 @@
|
||||
&usdhc2 {
|
||||
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
|
||||
};
|
||||
|
||||
&usdhc3 {
|
||||
compatible = "fsl,imx8qm-usdhc", "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
|
||||
};
|
||||
|
||||
@@ -56,6 +56,14 @@
|
||||
compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
|
||||
};
|
||||
|
||||
&lsio_mu5 {
|
||||
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
|
||||
};
|
||||
|
||||
&lsio_mu6 {
|
||||
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
|
||||
};
|
||||
|
||||
&lsio_mu13 {
|
||||
compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
|
||||
};
|
||||
|
||||
@@ -20,6 +20,9 @@
|
||||
mmc1 = &usdhc2;
|
||||
mmc2 = &usdhc3;
|
||||
serial0 = &lpuart0;
|
||||
serial1 = &lpuart1;
|
||||
serial2 = &lpuart2;
|
||||
serial3 = &lpuart3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
@@ -54,7 +57,7 @@
|
||||
|
||||
A53_0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
@@ -68,7 +71,7 @@
|
||||
|
||||
A53_1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
@@ -82,7 +85,7 @@
|
||||
|
||||
A53_2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
@@ -96,7 +99,7 @@
|
||||
|
||||
A53_3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0x8000>;
|
||||
@@ -110,7 +113,7 @@
|
||||
|
||||
A72_0: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xC000>;
|
||||
@@ -124,7 +127,7 @@
|
||||
|
||||
A72_1: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72", "arm,armv8";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
next-level-cache = <&A72_L2>;
|
||||
@@ -201,6 +204,9 @@
|
||||
compatible = "fsl,imx8qm-iomuxc";
|
||||
};
|
||||
|
||||
rtc: rtc {
|
||||
compatible = "fsl,imx8qxp-sc-rtc";
|
||||
};
|
||||
};
|
||||
|
||||
/* sorted in register address */
|
||||
|
||||
@@ -5,19 +5,19 @@
|
||||
*/
|
||||
|
||||
&lpuart0 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
compatible = "fsl,imx8qxp-lpuart";
|
||||
};
|
||||
|
||||
&lpuart1 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
compatible = "fsl,imx8qxp-lpuart";
|
||||
};
|
||||
|
||||
&lpuart2 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
compatible = "fsl,imx8qxp-lpuart";
|
||||
};
|
||||
|
||||
&lpuart3 {
|
||||
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
|
||||
compatible = "fsl,imx8qxp-lpuart";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
|
||||
@@ -56,6 +56,14 @@
|
||||
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
|
||||
};
|
||||
|
||||
&lsio_mu5 {
|
||||
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
|
||||
};
|
||||
|
||||
&lsio_mu6 {
|
||||
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
|
||||
};
|
||||
|
||||
&lsio_mu13 {
|
||||
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
|
||||
};
|
||||
|
||||
@@ -66,6 +66,12 @@
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_refclk: pcie0-refclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
reg_hub_vbus: regulator-hub-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "MBA8MX_HUB_VBUS";
|
||||
|
||||
Reference in New Issue
Block a user