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drm/msm/dpu: convert vsync source defines to the enum

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Add enum dpu_vsync_source instead of a series of defines. Use this enum
to pass vsync information.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/598743/
Link: https://lore.kernel.org/r/20240613-dpu-handle-te-signal-v2-2-67a0116b5366@linaro.org
This commit is contained in:
Dmitry Baryshkov
2024-06-13 20:05:05 +03:00
parent ec66abb42d
commit 548eb2bcea
5 changed files with 18 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
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@@ -747,7 +747,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
if (disp_info->is_te_using_watchdog_timer)
vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
else
vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_GPIO_0;
hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
View File

@@ -477,7 +477,7 @@ static int dpu_hw_intf_get_vsync_info(struct dpu_hw_intf *intf,
}
static void dpu_hw_intf_vsync_sel(struct dpu_hw_intf *intf,
u32 vsync_source)
enum dpu_vsync_source vsync_source)
{
struct dpu_hw_blk_reg_map *c;

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
View File

@@ -108,7 +108,7 @@ struct dpu_hw_intf_ops {
int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external_te);
void (*vsync_sel)(struct dpu_hw_intf *intf, u32 vsync_source);
void (*vsync_sel)(struct dpu_hw_intf *intf, enum dpu_vsync_source vsync_source);
/**
* Disable autorefresh if enabled

26
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
View File

@@ -54,18 +54,20 @@
#define DPU_BLEND_BG_INV_MOD_ALPHA (1 << 12)
#define DPU_BLEND_BG_TRANSP_EN (1 << 13)
#define DPU_VSYNC0_SOURCE_GPIO 0
#define DPU_VSYNC1_SOURCE_GPIO 1
#define DPU_VSYNC2_SOURCE_GPIO 2
#define DPU_VSYNC_SOURCE_INTF_0 3
#define DPU_VSYNC_SOURCE_INTF_1 4
#define DPU_VSYNC_SOURCE_INTF_2 5
#define DPU_VSYNC_SOURCE_INTF_3 6
#define DPU_VSYNC_SOURCE_WD_TIMER_4 11
#define DPU_VSYNC_SOURCE_WD_TIMER_3 12
#define DPU_VSYNC_SOURCE_WD_TIMER_2 13
#define DPU_VSYNC_SOURCE_WD_TIMER_1 14
#define DPU_VSYNC_SOURCE_WD_TIMER_0 15
enum dpu_vsync_source {
DPU_VSYNC_SOURCE_GPIO_0,
DPU_VSYNC_SOURCE_GPIO_1,
DPU_VSYNC_SOURCE_GPIO_2,
DPU_VSYNC_SOURCE_INTF_0 = 3,
DPU_VSYNC_SOURCE_INTF_1,
DPU_VSYNC_SOURCE_INTF_2,
DPU_VSYNC_SOURCE_INTF_3,
DPU_VSYNC_SOURCE_WD_TIMER_4 = 11,
DPU_VSYNC_SOURCE_WD_TIMER_3,
DPU_VSYNC_SOURCE_WD_TIMER_2,
DPU_VSYNC_SOURCE_WD_TIMER_1,
DPU_VSYNC_SOURCE_WD_TIMER_0,
};
enum dpu_hw_blk_type {
DPU_HW_BLK_TOP = 0,

2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
View File

@@ -64,7 +64,7 @@ struct dpu_vsync_source_cfg {
u32 pp_count;
u32 frame_rate;
u32 ppnumber[PINGPONG_MAX];
u32 vsync_source;
enum dpu_vsync_source vsync_source;
};
/**