mirror/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge tag 'v6.11-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt

Browse Source 
One new board, the pretty interesting Rock 5 ITX, some improvements
for the Lunzn Fastrhino R6xS boards, allowing dma on uarts connected
to bluetooth modules and an update for the gpu operating points on
rk356x. As well as some minor fixes for missing power-dmains and
ethernet phy binding adherence.

* tag 'v6.11-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: add ROCK 5 ITX board
  dt-bindings: arm: rockchip: Add ROCK 5 ITX board
  arm64: dts: rockchip: Add dma-names to uart1 on Pine64 rk3566 devices
  arm64: dts: rockchip: Add avdd supplies to hdmi on rock64
  arm64: dts: rockchip: fixes PHY reset for Lunzn Fastrhino R68S
  arm64: dts: rockchip: disable display subsystem for Lunzn Fastrhino R6xS
  arm64: dts: rockchip: remove unused usb2 nodes for Lunzn Fastrhino R6xS
  arm64: dts: rockchip: fix pmu_io supply for Lunzn Fastrhino R6xS
  arm64: dts: rockchip: fix usb regulator for Lunzn Fastrhino R6xS
  arm64: dts: rockchip: fix regulator name for Lunzn Fastrhino R6xS
  arm64: dts: rockchip: Add dma-names to uart1 on quartz64-b
  arm64: dts: rockchip: Update GPU OPP voltages in RK356x SoC dtsi
  arm64: dts: rockchip: Add GPU OPP voltage ranges to RK356x SoC dtsi
  arm64: dts: rockchip: Drop ethernet-phy-ieee802.3-c22 from PHY compatible string on all RK3588 boards
  arm64: dts: rockchip: Add missing power-domains for rk356x vop_mmu

Link: https://lore.kernel.org/r/1998182.CrzyxZ31qj@diego
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-07-08 17:47:25 +02:00
parent 31f6b5a651 31390eb8ff
commit 6355edbb3d
14 changed files with 1227 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/arm/rockchip.yaml
View File

@@ -816,6 +816,11 @@ properties:
- const: radxa,rock-3c
- const: rockchip,rk3566
- description: Radxa ROCK 5 ITX
items:
- const: radxa,rock-5-itx
- const: rockchip,rk3588
- description: Radxa ROCK 5A
items:
- const: radxa,rock-5a

1
arch/arm64/boot/dts/rockchip/Makefile
View File

@@ -128,6 +128,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ok3588-c.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5-itx.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo

2
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
View File

@@ -154,6 +154,8 @@
};
&hdmi {
avdd-0v9-supply = <&vdd_10>;
avdd-1v8-supply = <&vcc_18>;
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
View File

@@ -674,6 +674,7 @@
};
&uart1 {
dma-names = "tx", "rx";
pinctrl-0 = <&uart1m0_ctsn>, <&uart1m0_rtsn>, <&uart1m0_xfer>;
pinctrl-names = "default";
uart-has-rtscts;

1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
View File

@@ -738,6 +738,7 @@
};
&uart1 {
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "okay";

1
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
View File

@@ -652,6 +652,7 @@
};
&uart1 {
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
status = "okay";

1
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
View File

@@ -614,6 +614,7 @@
};
&uart1 {
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
uart-has-rtscts;

4
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
View File

@@ -11,6 +11,10 @@
};
};
&pmu_io_domains {
vccio3-supply = <&vccio_sd>;
};
&sdmmc0 {
bus-width = <4>;
cap-mmc-highspeed;

48
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
View File

@@ -39,9 +39,9 @@
};
};
dc_12v: dc-12v-regulator {
vcc12v_dcin: vcc12v-dcin-regulator {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-name = "vcc12v_dcin";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
@@ -65,7 +65,7 @@
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_sys: vcc5v0-sys-regulator {
@@ -75,16 +75,7 @@
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
vcc5v0_usb_host: vcc5v0-usb-host-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_usb_host";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
@@ -94,8 +85,9 @@
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_usb_otg_en>;
regulator-name = "vcc5v0_usb_otg";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc5v0_sys>;
};
};
@@ -123,6 +115,10 @@
cpu-supply = <&vdd_cpu>;
};
&display_subsystem {
status = "disabled";
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@@ -405,8 +401,8 @@
&pmu_io_domains {
pmuio1-supply = <&vcc3v3_pmu>;
pmuio2-supply = <&vcc3v3_pmu>;
vccio1-supply = <&vccio_acodec>;
vccio3-supply = <&vccio_sd>;
vccio1-supply = <&vcc_3v3>;
vccio2-supply = <&vcc_1v8>;
vccio4-supply = <&vcc_1v8>;
vccio5-supply = <&vcc_3v3>;
vccio6-supply = <&vcc_1v8>;
@@ -429,28 +425,12 @@
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
&usb_host0_xhci {
dr_mode = "host";
extcon = <&usb2phy0>;
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usb_host1_xhci {
status = "okay";
};
@@ -460,7 +440,7 @@
};
&usb2phy0_host {
phy-supply = <&vcc5v0_usb_host>;
phy-supply = <&vcc5v0_sys>;
status = "okay";
};

16
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
View File

@@ -39,7 +39,7 @@
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
@@ -61,7 +61,7 @@
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus>;
snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 15ms, 50ms for rtl8211f */
snps,reset-delays-us = <0 15000 50000>;
@@ -71,18 +71,18 @@
};
&mdio0 {
rgmii_phy0: ethernet-phy@0 {
rgmii_phy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
};
};
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
rgmii_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reg = <0x1>;
pinctrl-0 = <&eth_phy1_reset_pin>;
pinctrl-names = "default";
};
@@ -102,6 +102,10 @@
};
};
&pmu_io_domains {
vccio3-supply = <&vcc_3v3>;
};
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;

13
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View File

@@ -195,32 +195,32 @@
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <825000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <825000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <825000>;
opp-microvolt = <850000 850000 1000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <825000>;
opp-microvolt = <900000 900000 1000000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
opp-microvolt = <900000>;
opp-microvolt = <950000 950000 1000000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1000000>;
opp-microvolt = <1000000 1000000 1000000>;
};
};
@@ -790,6 +790,7 @@
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3568_PD_VO>;
status = "disabled";
};

6
arch/arm64/boot/dts/rockchip/rk3588-ok3588-c.dts
View File

@@ -261,8 +261,7 @@
&mdio0 {
rgmii_phy0: ethernet-phy@1 {
/* RTL8211F */
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_0_rst>;
@@ -275,8 +274,7 @@
&mdio1 {
rgmii_phy1: ethernet-phy@2 {
/* RTL8211F */
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id001c.c916";
reg = <0x2>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_1_rst>;

1177
arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts Normal file
View File

File diff suppressed because it is too large Load Diff

3
arch/arm64/boot/dts/rockchip/rk3588-turing-rk1.dtsi
View File

@@ -198,8 +198,7 @@
&mdio1 {
rgmii_phy: ethernet-phy@1 {
/* RTL8211F */
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
compatible = "ethernet-phy-id001c.c916";
reg = <0x1>;
pinctrl-names = "default";
pinctrl-0 = <&rtl8211f_rst>;