Merge tag 'mmp-dt-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp into arm/dt
ARM: Marvell MMP Device Tree patches for v5.5 This tag includes binding documentation for various hardware found on Marvell MMP3 SoC along a DTS file for said hardware. * tag 'mmp-dt-for-v5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp: ARM: dts: mmp3: Add MMP3 SoC dts file dt-bindings: phy-mmp3-usb: Add bindings dt-bindings: mrvl,intc: Add a MMP3 interrupt controller dt-bindings: arm: mrvl: Document MMP3 compatible string dt-bindings: arm: Convert Marvell MMP board/soc bindings to json-schema dt-bindings: arm: cpu: Add Marvell MMP3 SMP enable method Link: https://lore.kernel.org/r/d4897c4a92319527c46147244282803cd9f5a1ff.camel@v3.sk Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
@@ -189,6 +189,7 @@ properties:
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- marvell,armada-390-smp
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- marvell,armada-xp-smp
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- marvell,98dx3236-smp
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- marvell,mmp3-smp
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- mediatek,mt6589-smp
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- mediatek,mt81xx-tz-smp
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- qcom,gcc-msm8660
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@@ -1,14 +0,0 @@
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Marvell Platforms Device Tree Bindings
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----------------------------------------------------
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PXA168 Aspenite Board
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Required root node properties:
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- compatible = "mrvl,pxa168-aspenite", "mrvl,pxa168";
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PXA910 DKB Board
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Required root node properties:
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- compatible = "mrvl,pxa910-dkb";
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MMP2 Brownstone Board
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Required root node properties:
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- compatible = "mrvl,mmp2-brownstone", "mrvl,mmp2";
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35
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
Normal file
35
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
Normal file
@@ -0,0 +1,35 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/mrvl/mrvl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Platforms Device Tree Bindings
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maintainers:
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- Lubomir Rintel <lkundrak@v3.sk>
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properties:
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$nodename:
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const: '/'
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compatible:
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oneOf:
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- description: PXA168 Aspenite Board
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items:
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- enum:
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- mrvl,pxa168-aspenite
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- const: mrvl,pxa168
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- description: PXA910 DKB Board
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items:
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- enum:
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- mrvl,pxa910-dkb
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- const: mrvl,pxa910
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- description: MMP2 based boards
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items:
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- enum:
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- mrvl,mmp2-brownstone
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- const: mrvl,mmp2
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- description: MMP3 based boards
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items:
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- const: mrvl,mmp3
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...
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@@ -1,13 +1,17 @@
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* Marvell MMP Interrupt controller
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Required properties:
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- compatible : Should be "mrvl,mmp-intc", "mrvl,mmp2-intc" or
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"mrvl,mmp2-mux-intc"
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- compatible : Should be
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"mrvl,mmp-intc" on Marvel MMP,
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"mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
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"marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
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- reg : Address and length of the register set of the interrupt controller.
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If the interrupt controller is intc, address and length means the range
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of the whole interrupt controller. If the interrupt controller is mux-intc,
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address and length means one register. Since address of mux-intc is in the
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range of intc. mux-intc is secondary interrupt controller.
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of the whole interrupt controller. The "marvell,mmp3-intc" controller
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also has a secondary range for the second CPU core. If the interrupt
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controller is mux-intc, address and length means one register. Since
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address of mux-intc is in the range of intc. mux-intc is secondary
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interrupt controller.
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- reg-names : Name of the register set of the interrupt controller. It's
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only required in mux-intc interrupt controller.
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- interrupts : Should be the port interrupt shared by mux interrupts. It's
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13
Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
Normal file
13
Documentation/devicetree/bindings/phy/phy-mmp3-usb.txt
Normal file
@@ -0,0 +1,13 @@
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Marvell MMP3 USB PHY
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--------------------
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Required properties:
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- compatible: must be "marvell,mmp3-usb-phy"
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- #phy-cells: must be 0
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Example:
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usb-phy: usb-phy@d4207000 {
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compatible = "marvell,mmp3-usb-phy";
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reg = <0xd4207000 0x40>;
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#phy-cells = <0>;
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};
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527
arch/arm/boot/dts/mmp3.dtsi
Normal file
527
arch/arm/boot/dts/mmp3.dtsi
Normal file
@@ -0,0 +1,527 @@
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
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*/
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#include <dt-bindings/clock/marvell,mmp2.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,mmp3-smp";
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cpu@0 {
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compatible = "marvell,pj4b";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <0>;
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};
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cpu@1 {
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compatible = "marvell,pj4b";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <1>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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axi@d4200000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xd4200000 0x00200000>;
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ranges;
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interrupt-controller@d4282000 {
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compatible = "marvell,mmp3-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xd4282000 0x1000>,
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<0xd4284000 0x100>;
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mrvl,intc-nr-irqs = <64>;
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};
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pmic_mux: interrupt-controller@d4282150 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x150 0x4>, <0x168 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <4>;
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};
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rtc_mux: interrupt-controller@d4282154 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x154 0x4>, <0x16c 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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};
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hsi3_mux: interrupt-controller@d42821bc {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1bc 0x4>, <0x1a4 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <3>;
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};
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gpu_mux: interrupt-controller@d42821c0 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1c0 0x4>, <0x1a8 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <3>;
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};
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twsi_mux: interrupt-controller@d4282158 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x158 0x4>, <0x170 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <5>;
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};
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hsi2_mux: interrupt-controller@d42821c4 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1c4 0x4>, <0x1ac 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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};
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dxo_mux: interrupt-controller@d42821c8 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1c8 0x4>, <0x1b0 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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};
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misc1_mux: interrupt-controller@d428215c {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x15c 0x4>, <0x174 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <31>;
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};
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ci_mux: interrupt-controller@d42821cc {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1cc 0x4>, <0x1b4 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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};
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ssp_mux: interrupt-controller@d4282160 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x160 0x4>, <0x178 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <2>;
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};
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hsi1_mux: interrupt-controller@d4282184 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x184 0x4>, <0x17c 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <4>;
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};
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misc2_mux: interrupt-controller@d4282188 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x188 0x4>, <0x180 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <20>;
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};
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hsi0_mux: interrupt-controller@d42821d0 {
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compatible = "mrvl,mmp2-mux-intc";
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x1d0 0x4>, <0x1b8 0x4>;
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reg-names = "mux status", "mux mask";
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mrvl,intc-nr-irqs = <5>;
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};
|
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|
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usb_otg_phy0: usb-otg-phy@d4207000 {
|
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compatible = "marvell,mmp3-usb-phy";
|
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reg = <0xd4207000 0x40>;
|
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#phy-cells = <0>;
|
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status = "disabled";
|
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};
|
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|
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usb_otg0: usb-otg@d4208000 {
|
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compatible = "marvell,pxau2o-ehci";
|
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reg = <0xd4208000 0x200>;
|
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
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clocks = <&soc_clocks MMP2_CLK_USB>;
|
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clock-names = "USBCLK";
|
||||
phys = <&usb_otg_phy0>;
|
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phy-names = "usb";
|
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status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@d4280000 {
|
||||
compatible = "mrvl,pxav3-mmc";
|
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reg = <0xd4280000 0x120>;
|
||||
clocks = <&soc_clocks MMP2_CLK_SDH0>;
|
||||
clock-names = "io";
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc2: mmc@d4280800 {
|
||||
compatible = "mrvl,pxav3-mmc";
|
||||
reg = <0xd4280800 0x120>;
|
||||
clocks = <&soc_clocks MMP2_CLK_SDH1>;
|
||||
clock-names = "io";
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc3: mmc@d4281000 {
|
||||
compatible = "mrvl,pxav3-mmc";
|
||||
reg = <0xd4281000 0x120>;
|
||||
clocks = <&soc_clocks MMP2_CLK_SDH2>;
|
||||
clock-names = "io";
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc4: mmc@d4281800 {
|
||||
compatible = "mrvl,pxav3-mmc";
|
||||
reg = <0xd4281800 0x120>;
|
||||
clocks = <&soc_clocks MMP2_CLK_SDH3>;
|
||||
clock-names = "io";
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
camera0: camera@d420a000 {
|
||||
compatible = "marvell,mmp2-ccic";
|
||||
reg = <0xd420a000 0x800>;
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clocks MMP2_CLK_CCIC0>;
|
||||
clock-names = "axi";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
camera1: camera@d420a800 {
|
||||
compatible = "marvell,mmp2-ccic";
|
||||
reg = <0xd420a800 0x800>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clocks MMP2_CLK_CCIC1>;
|
||||
clock-names = "axi";
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
apb@d4000000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xd4000000 0x00200000>;
|
||||
ranges;
|
||||
|
||||
timer: timer@d4014000 {
|
||||
compatible = "mrvl,mmp-timer";
|
||||
reg = <0xd4014000 0x100>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TIMER>;
|
||||
};
|
||||
|
||||
uart1: uart@d4030000 {
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4030000 0x1000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clocks MMP2_CLK_UART0>;
|
||||
resets = <&soc_clocks MMP2_CLK_UART0>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: uart@d4017000 {
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4017000 0x1000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clocks MMP2_CLK_UART1>;
|
||||
resets = <&soc_clocks MMP2_CLK_UART1>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: uart@d4018000 {
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4018000 0x1000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clocks MMP2_CLK_UART2>;
|
||||
resets = <&soc_clocks MMP2_CLK_UART2>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: uart@d4016000 {
|
||||
compatible = "mrvl,mmp-uart";
|
||||
reg = <0xd4016000 0x1000>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clocks MMP2_CLK_UART3>;
|
||||
resets = <&soc_clocks MMP2_CLK_UART3>;
|
||||
reg-shift = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio: gpio@d4019000 {
|
||||
compatible = "marvell,mmp2-gpio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0xd4019000 0x1000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "gpio_mux";
|
||||
clocks = <&soc_clocks MMP2_CLK_GPIO>;
|
||||
resets = <&soc_clocks MMP2_CLK_GPIO>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ranges;
|
||||
|
||||
gcb0: gpio@d4019000 {
|
||||
reg = <0xd4019000 0x4>;
|
||||
};
|
||||
|
||||
gcb1: gpio@d4019004 {
|
||||
reg = <0xd4019004 0x4>;
|
||||
};
|
||||
|
||||
gcb2: gpio@d4019008 {
|
||||
reg = <0xd4019008 0x4>;
|
||||
};
|
||||
|
||||
gcb3: gpio@d4019100 {
|
||||
reg = <0xd4019100 0x4>;
|
||||
};
|
||||
|
||||
gcb4: gpio@d4019104 {
|
||||
reg = <0xd4019104 0x4>;
|
||||
};
|
||||
|
||||
gcb5: gpio@d4019108 {
|
||||
reg = <0xd4019108 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
twsi1: i2c@d4011000 {
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4011000 0x1000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TWSI0>;
|
||||
resets = <&soc_clocks MMP2_CLK_TWSI0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mrvl,i2c-fast-mode;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
twsi2: i2c@d4031000 {
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4031000 0x1000>;
|
||||
interrupt-parent = <&twsi_mux>;
|
||||
interrupts = <0>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TWSI1>;
|
||||
resets = <&soc_clocks MMP2_CLK_TWSI1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
twsi3: i2c@d4032000 {
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4032000 0x1000>;
|
||||
interrupt-parent = <&twsi_mux>;
|
||||
interrupts = <1>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TWSI2>;
|
||||
resets = <&soc_clocks MMP2_CLK_TWSI2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
twsi4: i2c@d4033000 {
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4033000 0x1000>;
|
||||
interrupt-parent = <&twsi_mux>;
|
||||
interrupts = <2>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TWSI3>;
|
||||
resets = <&soc_clocks MMP2_CLK_TWSI3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
twsi5: i2c@d4033800 {
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4033800 0x1000>;
|
||||
interrupt-parent = <&twsi_mux>;
|
||||
interrupts = <3>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TWSI4>;
|
||||
resets = <&soc_clocks MMP2_CLK_TWSI4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
twsi6: i2c@d4034000 {
|
||||
compatible = "mrvl,mmp-twsi";
|
||||
reg = <0xd4034000 0x1000>;
|
||||
interrupt-parent = <&twsi_mux>;
|
||||
interrupts = <4>;
|
||||
clocks = <&soc_clocks MMP2_CLK_TWSI5>;
|
||||
resets = <&soc_clocks MMP2_CLK_TWSI5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@d4010000 {
|
||||
compatible = "mrvl,mmp-rtc";
|
||||
reg = <0xd4010000 0x1000>;
|
||||
interrupts = <1 0>;
|
||||
interrupt-names = "rtc 1Hz", "rtc alarm";
|
||||
interrupt-parent = <&rtc_mux>;
|
||||
clocks = <&soc_clocks MMP2_CLK_RTC>;
|
||||
resets = <&soc_clocks MMP2_CLK_RTC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp1: spi@d4035000 {
|
||||
compatible = "marvell,mmp2-ssp";
|
||||
reg = <0xd4035000 0x1000>;
|
||||
clocks = <&soc_clocks MMP2_CLK_SSP0>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp2: spi@d4036000 {
|
||||
compatible = "marvell,mmp2-ssp";
|
||||
reg = <0xd4036000 0x1000>;
|
||||
clocks = <&soc_clocks MMP2_CLK_SSP1>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp3: spi@d4037000 {
|
||||
compatible = "marvell,mmp2-ssp";
|
||||
reg = <0xd4037000 0x1000>;
|
||||
clocks = <&soc_clocks MMP2_CLK_SSP2>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssp4: spi@d4039000 {
|
||||
compatible = "marvell,mmp2-ssp";
|
||||
reg = <0xd4039000 0x1000>;
|
||||
clocks = <&soc_clocks MMP2_CLK_SSP3>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
l2: l2-cache-controller@d0020000 {
|
||||
compatible = "marvell,tauros3-cache", "arm,pl310-cache";
|
||||
reg = <0xd0020000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
soc_clocks: clocks {
|
||||
compatible = "marvell,mmp2-clock";
|
||||
reg = <0xd4050000 0x1000>,
|
||||
<0xd4282800 0x400>,
|
||||
<0xd4015000 0x1000>;
|
||||
reg-names = "mpmu", "apmu", "apbc";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
#power-domain-cells = <1>;
|
||||
};
|
||||
|
||||
snoop-control-unit@e0000000 {
|
||||
compatible = "arm,arm11mp-scu";
|
||||
reg = <0xe0000000 0x100>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@e0001000 {
|
||||
compatible = "arm,arm11mp-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0xe0001000 0x1000>,
|
||||
<0xe0000100 0x100>;
|
||||
};
|
||||
|
||||
local-timer@e0000600 {
|
||||
compatible = "arm,arm11mp-twd-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_EDGE_RISING)>;
|
||||
reg = <0xe0000600 0x20>;
|
||||
};
|
||||
|
||||
watchdog@2c000620 {
|
||||
compatible = "arm,arm11mp-twd-wdt";
|
||||
reg = <0xe0000620 0x20>;
|
||||
interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_EDGE_RISING)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user