mirror/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

arm64: dts: mediatek: add power domain support for mt8365 SoC

Browse Source 
The following power domain are added to the SoC dts:
- MM (MultiMedia)
- CONN (Connectivity)
- MFG (MFlexGraphics)
- Audio
- Cam (Camera)
- DSP (Digital Signal Processor)
- Vdec (Video decoder)
- Venc (Video encoder)
- APU (AI Processor Unit)

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230207-iommu-support-v6-4-24453c8625b3@baylibre.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Alexandre Mergnat
2023-09-25 20:17:38 +02:00
committed by Matthias Brugger
parent b9b9f1e2bf
commit c70ca9a2d0
1 changed files with 110 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

110
arch/arm64/boot/dts/mediatek/mt8365.dtsi
View File

@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mediatek,mt8365-power.h>
/ {
compatible = "mediatek,mt8365";
@@ -298,6 +299,115 @@
reg = <0 0x10005000 0 0x1000>;
};
scpsys: syscon@10006000 {
compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8365-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8365_POWER_DOMAIN_MM {
reg = <MT8365_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&mmsys CLK_MM_MM_SMI_COMMON>,
<&mmsys CLK_MM_MM_SMI_COMM0>,
<&mmsys CLK_MM_MM_SMI_COMM1>,
<&mmsys CLK_MM_MM_SMI_LARB0>;
clock-names = "mm", "mm-0", "mm-1",
"mm-2", "mm-3";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
mediatek,infracfg-nao = <&infracfg_nao>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@MT8365_POWER_DOMAIN_CAM {
reg = <MT8365_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB2>,
<&camsys CLK_CAM_SENIF>,
<&camsys CLK_CAMSV0>,
<&camsys CLK_CAMSV1>,
<&camsys CLK_CAM_FDVT>,
<&camsys CLK_CAM_WPE>;
clock-names = "cam-0", "cam-1",
"cam-2", "cam-3",
"cam-4", "cam-5";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_VDEC {
reg = <MT8365_POWER_DOMAIN_VDEC>;
#power-domain-cells = <0>;
};
power-domain@MT8365_POWER_DOMAIN_VENC {
reg = <MT8365_POWER_DOMAIN_VENC>;
#power-domain-cells = <0>;
};
power-domain@MT8365_POWER_DOMAIN_APU {
reg = <MT8365_POWER_DOMAIN_APU>;
clocks = <&infracfg CLK_IFR_APU_AXI>,
<&apu CLK_APU_IPU_CK>,
<&apu CLK_APU_AXI>,
<&apu CLK_APU_JTAG>,
<&apu CLK_APU_IF_CK>,
<&apu CLK_APU_EDMA>,
<&apu CLK_APU_AHB>;
clock-names = "apu", "apu-0",
"apu-1", "apu-2",
"apu-3", "apu-4",
"apu-5";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
power-domain@MT8365_POWER_DOMAIN_CONN {
reg = <MT8365_POWER_DOMAIN_CONN>;
clocks = <&topckgen CLK_TOP_CONN_32K>,
<&topckgen CLK_TOP_CONN_26M>;
clock-names = "conn", "conn1";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_MFG {
reg = <MT8365_POWER_DOMAIN_MFG>;
clocks = <&topckgen CLK_TOP_MFG_SEL>;
clock-names = "mfg";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_AUDIO {
reg = <MT8365_POWER_DOMAIN_AUDIO>;
clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&infracfg CLK_IFR_AUDIO>,
<&infracfg CLK_IFR_AUD_26M_BK>;
clock-names = "audio", "audio1", "audio2";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_DSP {
reg = <MT8365_POWER_DOMAIN_DSP>;
clocks = <&topckgen CLK_TOP_DSP_SEL>,
<&topckgen CLK_TOP_DSP_26M>;
clock-names = "dsp", "dsp1";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;