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arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs

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Arm heterogeneous configurations should have separate PMU nodes for each
CPU uarch as the uarch specific events can be different. The
"arm,armv8-pmuv3" compatible is also intended for s/w models rather than
specific uarch implementations.

All the kryo CPUs are missing PMU compatibles, so they can't be fixed.

Signed-off-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20240417204247.3216703-1-robh@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Rob Herring (Arm)
2024-04-17 15:42:46 -05:00
committed by Bjorn Andersson
parent 839936d967
commit c8a346e408
6 changed files with 60 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/qcom/msm8956.dtsi
View File

@@ -8,8 +8,8 @@
#include "msm8976.dtsi"
&pmu {
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
&pmu_a72 {
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0x30) | IRQ_TYPE_LEVEL_HIGH)>;
};
&tsens {

12
arch/arm64/boot/dts/qcom/msm8976.dtsi
View File

@@ -222,11 +222,17 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu: pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
pmu_a72: pmu-a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_RAW(0xf0) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";

11
arch/arm64/boot/dts/qcom/sm4450.dtsi
View File

@@ -292,9 +292,14 @@
reg = <0x0 0xa0000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-a78 {
compatible = "arm,cortex-a78-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {

14
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@@ -301,8 +301,18 @@
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-a78 {
compatible = "arm,cortex-a78-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-x1 {
compatible = "arm,cortex-x1-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};

19
arch/arm64/boot/dts/qcom/sm8550.dtsi
View File

@@ -352,8 +352,23 @@
reg = <0 0xa0000000 0 0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
pmu-a510 {
compatible = "arm,cortex-a510-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-a710 {
compatible = "arm,cortex-a710-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-a715 {
compatible = "arm,cortex-a715-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-x3 {
compatible = "arm,cortex-x3-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};

14
arch/arm64/boot/dts/qcom/sm8650.dtsi
View File

@@ -390,8 +390,18 @@
reg = <0 0xa0000000 0 0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
pmu-a520 {
compatible = "arm,cortex-a520-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-a720 {
compatible = "arm,cortex-a720-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
pmu-x4 {
compatible = "arm,cortex-x4-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};