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scsi: ufs: exynos: gs101: Enable clock gating with hibern8

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Enable clock gating and hibern8 capabilities for gs101. This leads to a
significantly cooler phone when running the upstream kernel.

The exynos_ufs_post_hibern8() hook is also updated to remove the
UIC_CMD_DME_HIBER_EXIT code path as this causes a hang on gs101.

The code path is removed rather than re-factored as no other SoC in
ufs-exynos driver sets UFSHCD_CAP_HIBERN8_WITH_CLK_GATING
capability. Additionally until the previous commit the hibern8 callbacks
were broken anyway as they expected a bool.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20241031150033.3440894-14-peter.griffin@linaro.org
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
Peter Griffin
2024-10-31 15:00:32 +00:00
committed by Martin K. Petersen
parent ceef938bbf
commit cabc453ca6
1 changed files with 4 additions and 20 deletions
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24
drivers/ufs/host/ufs-exynos.c
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@@ -224,6 +224,9 @@ static int gs101_ufs_drv_init(struct exynos_ufs *ufs)
/* Enable WriteBooster */
hba->caps |= UFSHCD_CAP_WB_EN;
/* Enable clock gating and hibern8 */
hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
/* set ACG to be controlled by UFS_ACG_DISABLE */
reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE);
hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE);
@@ -1563,26 +1566,7 @@ static void exynos_ufs_post_hibern8(struct ufs_hba *hba, enum uic_cmd_dme cmd)
{
struct exynos_ufs *ufs = ufshcd_get_variant(hba);
if (cmd == UIC_CMD_DME_HIBER_EXIT) {
u32 cur_mode = 0;
u32 pwrmode;
if (ufshcd_is_hs_mode(&ufs->dev_req_params))
pwrmode = FAST_MODE;
else
pwrmode = SLOW_MODE;
ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode);
if (cur_mode != (pwrmode << 4 | pwrmode)) {
dev_warn(hba->dev, "%s: power mode change\n", __func__);
hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf;
hba->pwr_info.pwr_tx = cur_mode & 0xf;
ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
}
if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB))
exynos_ufs_establish_connt(ufs);
} else if (cmd == UIC_CMD_DME_HIBER_ENTER) {
if (cmd == UIC_CMD_DME_HIBER_ENTER) {
ufs->entry_hibern8_t = ktime_get();
exynos_ufs_gate_clks(ufs);
if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)