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clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs

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Join the two to register them in one shot.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230120092053.182923-18-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
AngeloGioacchino Del Regno
2023-01-20 10:20:47 +01:00
committed by Stephen Boyd
parent 66c8773b43
commit d7595ddeec
1 changed files with 15 additions and 22 deletions
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37
drivers/clk/mediatek/clk-mt8183.c
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@@ -613,21 +613,6 @@ static const char * const apll_i2s5_parents[] = {
"aud_2_sel"
};
static struct mtk_composite top_aud_muxes[] = {
MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
0x320, 8, 1),
MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
0x320, 9, 1),
MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
0x320, 10, 1),
MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
0x320, 11, 1),
MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
0x320, 12, 1),
MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
0x328, 20, 1),
};
static const char * const mcu_mp0_parents[] = {
"clk26m",
"armpll_ll",
@@ -658,7 +643,19 @@ static struct mtk_composite mcu_muxes[] = {
MUX(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0, 9, 2),
};
static struct mtk_composite top_aud_divs[] = {
static struct mtk_composite top_aud_comp[] = {
MUX(CLK_TOP_MUX_APLL_I2S0, "apll_i2s0_sel", apll_i2s0_parents,
0x320, 8, 1),
MUX(CLK_TOP_MUX_APLL_I2S1, "apll_i2s1_sel", apll_i2s1_parents,
0x320, 9, 1),
MUX(CLK_TOP_MUX_APLL_I2S2, "apll_i2s2_sel", apll_i2s2_parents,
0x320, 10, 1),
MUX(CLK_TOP_MUX_APLL_I2S3, "apll_i2s3_sel", apll_i2s3_parents,
0x320, 11, 1),
MUX(CLK_TOP_MUX_APLL_I2S4, "apll_i2s4_sel", apll_i2s4_parents,
0x320, 12, 1),
MUX(CLK_TOP_MUX_APLL_I2S5, "apll_i2s5_sel", apll_i2s5_parents,
0x328, 20, 1),
DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_sel",
0x320, 2, 0x324, 8, 0),
DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_sel",
@@ -1170,12 +1167,8 @@ static int clk_mt8183_top_probe(struct platform_device *pdev)
ARRAY_SIZE(top_muxes), node,
&mt8183_clk_lock, top_clk_data);
mtk_clk_register_composites(&pdev->dev, top_aud_muxes,
ARRAY_SIZE(top_aud_muxes), base,
&mt8183_clk_lock, top_clk_data);
mtk_clk_register_composites(&pdev->dev, top_aud_divs,
ARRAY_SIZE(top_aud_divs), base,
mtk_clk_register_composites(&pdev->dev, top_aud_comp,
ARRAY_SIZE(top_aud_comp), base,
&mt8183_clk_lock, top_clk_data);
mtk_clk_register_gates(&pdev->dev, node, top_clks,