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ARM: dts: aspeed: ast2600-evb: Enable Quad SPI RX tranfers

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Now that the pinctrl definitions of the ast2600 SoC have been fixed,
see commit 925fbe1f7e ("dt-bindings: pinctrl: aspeed-g6: add FWQSPI
function/group"), it is safe to activate QSPI on the ast2600 evb.

Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220603073705.1624351-1-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
This commit is contained in:
Cédric Le Goater
2022-06-03 09:37:05 +02:00
committed by Joel Stanley
parent e360b84c33
commit da41645f11
1 changed files with 2 additions and 0 deletions
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2
arch/arm/boot/dts/aspeed-ast2600-evb.dts
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@@ -182,6 +182,7 @@
status = "okay";
m25p,fast-read;
label = "bmc";
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
@@ -196,6 +197,7 @@
status = "okay";
m25p,fast-read;
label = "pnor";
spi-rx-bus-width = <4>;
spi-max-frequency = <100000000>;
};
};