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clk: qcom: dispcc-sm8250: Add RETAIN_FF_ENABLE flag for mdss_gdsc

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All SoC supported by this driver supports the RETAIN_FF_ENABLE flag,
so it should be enabled here.

This feature enables registers to maintain their state after
dis/re-enabling the GDSC.

Signed-off-by: Robert Foss <robert.foss@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221102090140.965450-3-robert.foss@linaro.org
This commit is contained in:
Robert Foss
2022-11-02 10:01:37 +01:00
committed by Bjorn Andersson
parent b5f84650fb
commit e1a297a681
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/qcom/dispcc-sm8250.c
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@@ -1137,7 +1137,7 @@ static struct gdsc mdss_gdsc = {
.name = "mdss_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL,
.flags = HW_CTRL | RETAIN_FF_ENABLE,
};
static struct clk_regmap *disp_cc_sm8250_clocks[] = {