arm64: dts: qcom: sa8775p: add missing i2c nodes
Add the missing nodes for the i2c buses present on sa8775p Soc. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-3-quic_shazhuss@quicinc.com
This commit is contained in:
Shazad Hussain
committed by
Bjorn Andersson
Bjorn Andersson
parent
07e3e17205
commit
ee2f5f906d
@@ -490,6 +490,69 @@
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#size-cells = <2>;
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status = "disabled";
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i2c14: i2c@880000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x880000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c15: i2c@884000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x884000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c16: i2c@888000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x888000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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spi16: spi@888000 {
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compatible = "qcom,geni-spi";
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reg = <0x0 0x00888000 0x0 0x4000>;
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@@ -511,6 +574,27 @@
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status = "disabled";
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};
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i2c17: i2c@88c000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x88c000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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uart17: serial@88c000 {
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compatible = "qcom,geni-uart";
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reg = <0x0 0x0088c000 0x0 0x4000>;
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@@ -546,6 +630,48 @@
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#size-cells = <0>;
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status = "disabled";
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};
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i2c19: i2c@894000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x894000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c20: i2c@898000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x898000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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};
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qupv3_id_0: geniqup@9c0000 {
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@@ -559,6 +685,132 @@
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<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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iommus = <&apps_smmu 0x403 0x0>;
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status = "disabled";
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i2c0: i2c@980000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x980000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c1: i2c@984000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x984000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c2: i2c@988000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x988000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c3: i2c@98c000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x98c000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c4: i2c@990000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x990000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c5: i2c@994000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0x994000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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};
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qupv3_id_1: geniqup@ac0000 {
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@@ -573,6 +825,90 @@
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iommus = <&apps_smmu 0x443 0x0>;
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status = "disabled";
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i2c7: i2c@a80000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0xa80000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c8: i2c@a84000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0xa84000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c9: i2c@a88000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0xa88000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
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&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
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<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "qup-core",
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"qup-config",
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"qup-memory";
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power-domains = <&rpmhpd SA8775P_CX>;
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status = "disabled";
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};
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i2c10: i2c@a8c000 {
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compatible = "qcom,geni-i2c";
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reg = <0x0 0xa8c000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
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clock-names = "se";
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interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
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&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core",
|
||||
"qup-config",
|
||||
"qup-memory";
|
||||
power-domains = <&rpmhpd SA8775P_CX>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart10: serial@a8c000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x0 0x00a8c000 0x0 0x4000>;
|
||||
@@ -589,6 +925,48 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c11: i2c@a90000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x0 0xa90000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
||||
clock-names = "se";
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core",
|
||||
"qup-config",
|
||||
"qup-memory";
|
||||
power-domains = <&rpmhpd SA8775P_CX>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c12: i2c@a94000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x0 0xa94000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
||||
clock-names = "se";
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core",
|
||||
"qup-config",
|
||||
"qup-memory";
|
||||
power-domains = <&rpmhpd SA8775P_CX>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart12: serial@a94000 {
|
||||
compatible = "qcom,geni-uart";
|
||||
reg = <0x0 0x00a94000 0x0 0x4000>;
|
||||
@@ -603,6 +981,27 @@
|
||||
power-domains = <&rpmhpd SA8775P_CX>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c13: i2c@a98000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x0 0xa98000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
||||
clock-names = "se";
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core",
|
||||
"qup-config",
|
||||
"qup-memory";
|
||||
power-domains = <&rpmhpd SA8775P_CX>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_id_3: geniqup@bc0000 {
|
||||
@@ -616,6 +1015,27 @@
|
||||
<&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
|
||||
iommus = <&apps_smmu 0x43 0x0>;
|
||||
status = "disabled";
|
||||
|
||||
i2c21: i2c@b80000 {
|
||||
compatible = "qcom,geni-i2c";
|
||||
reg = <0x0 0xb80000 0x0 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
|
||||
clock-names = "se";
|
||||
interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS
|
||||
&clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
|
||||
&config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>,
|
||||
<&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS
|
||||
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
|
||||
interconnect-names = "qup-core",
|
||||
"qup-config",
|
||||
"qup-memory";
|
||||
power-domains = <&rpmhpd SA8775P_CX>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ufs_mem_hc: ufs@1d84000 {
|
||||
|
||||
Reference in New Issue
Block a user