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Merge tag 'imx-dt64-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

Browse Source 
i.MX arm64 device tree for 6.10:

- New board support: Emcraft Systems NavQ+ Kit, Toradex Colibri iMX8DX,
  and S32G-VNP-RDB3 board.
- A series from Alexander Stein that adds empty DSI output endpoint to
  simplify DSI connection description at board level.
- Add pinmux and I2C GPIOs to support bus recovery for LX2160A.
- Add cm40 subsystem description for i.MX8 SoCs.
- A series from Frank Li that adds ADC, LPSPI and FlexSPI devices for
  imx8qm-mek board.
- Add audio devices ASRC, ESAI, SPDIF and SAI for i.MX8QXP and correct
  audio LPCG index.
- A couple of changes from Ghennadi Procopciuc that add SCMI firmware
  and uSDHC nodes for S32G SoC.
- A couple of imx8mp-msc-sm2s updates from Ian Ray improving I2C pad
  drive strength and adding SDA/SCL GPIOs for I2C devices.
- Add PCA9451A PMIC and PCF2131 RTC support for imx93-11x11-evk board.
- A series from Lucas Stach to enable HDMI display support for i.MX8MP.
- A series from Peng Fan to improve i.MX93 support for LPI2C, LPSPI, FEC
  and eQoS.
- A couple of LS1028A changes from Rob Herring to improve PCI device
  description.
- A series from Shengjiu Wang adding HDMI and PDM mic sound support for
  imx8mp-evk board.
- A number of i.MX8M Venice device improvements from Stefan Eichenberger,
  Tim Harvey and Vitor Soares.
- A series from Xu Yang that enables USB support for imx8ulp-evk and
  imx93-11x11-evk board.
- Other small and random updates on various boards.

* tag 'imx-dt64-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (78 commits)
  arm64: dts: imx93-11x11-evk: add RTC PCF2131 support
  arm64: dts: imx93-11x11-evk: add reset gpios for ethernet PHYs
  arm64: dts: imx93-11x11-evk: add sleep pinctrl for sdhc2
  arm64: dts: imx93-11x11-evk: add different usdhc pinctrl for different timing usage
  arm64: dts: imx93-11x11-evk: add sleep pinctrl for eqos and fec
  arm64: dts: imx93-11x11-evk: update resource table address
  arm64: dts: imx93: add nvmem property for eqos
  arm64: dts: imx93: add nvmem property for fec1
  arm64: dts: imx93: assign usdhc[1..3] root clock to 400MHz
  arm64: dts: imx93: add dma support for lpspi[1..8]
  arm64: dts: imx93: add dma support for lpi2c[1..8]
  arm64: dts: imx93: use FSL_EDMA_RX for rx channel
  arm64: dts: freescale: ls1028a: Add standard PCI device compatible strings to ENETC
  arm64: dts: freescale: ls1028a: Fix embedded PCI interrupt mapping
  arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960 and sai[0,1,4,5]
  arm64: dts: imx8mp: Align both CSI2 pixel clock
  arm64: dts: freescale: imx8m[mp]-verdin: Update audio card name
  arm64: dts: imx8mp: Enable HDMI on TQMa8MPxL/MBa8MPxL
  arm64: dts: imx8ulp: add caam jr
  arm64: dts: imx8mp-msc-sm2s: Add i2c{1,6} sda-/scl-gpios
  ...

Link: https://lore.kernel.org/r/20240428121247.10370-4-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-04-29 17:59:43 +02:00
parent 7194048ccf 8005c3e17d
commit f71b3cf82e
68 changed files with 3022 additions and 131 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm64/boot/dts/freescale/Makefile
View File

@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-kbox-a-230-ls.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var1.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
@@ -98,6 +99,10 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-11-x.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-aster.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris-v2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dx-colibri-iris.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
@@ -166,6 +171,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb
@@ -259,4 +265,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
dtb-$(CONFIG_ARCH_S32) += s32g399a-rdb3.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb

2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts
View File

@@ -10,7 +10,7 @@
/dts-v1/;
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include "fsl-ls1028a-kontron-sl28.dts"
#include "fsl-ls1028a-kontron-sl28-var3.dts"
/ {
model = "Kontron SMARC-sAL28 (Single PHY) on SMARC Eval 2.0 carrier";

18
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
* This is for the network variant 3 which has one ethernet ports.
*
* Copyright (C) 2024 Michael Walle <michael@walle.cc>
*
*/
/dts-v1/;
#include "fsl-ls1028a-kontron-sl28.dts"
/ {
model = "Kontron SMARC-sAL28 (Single PHY)";
compatible = "kontron,sl28-var3", "kontron,sl28", "fsl,ls1028a";
};

20
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@@ -1099,21 +1099,25 @@
0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
/* BAR4 (PF5) - non-prefetchable memory */
0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
enetc_port0: ethernet@0,0 {
compatible = "fsl,enetc";
compatible = "pci1957,e100", "fsl,enetc";
reg = <0x000000 0 0 0 0>;
status = "disabled";
};
enetc_port1: ethernet@0,1 {
compatible = "fsl,enetc";
compatible = "pci1957,e100", "fsl,enetc";
reg = <0x000100 0 0 0 0>;
status = "disabled";
};
enetc_port2: ethernet@0,2 {
compatible = "fsl,enetc";
compatible = "pci1957,e100", "fsl,enetc";
reg = <0x000200 0 0 0 0>;
phy-mode = "internal";
status = "disabled";
@@ -1126,14 +1130,14 @@
};
enetc_mdio_pf3: mdio@0,3 {
compatible = "fsl,enetc-mdio";
compatible = "pci1957,ee01", "fsl,enetc-mdio";
reg = <0x000300 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
};
ethernet@0,4 {
compatible = "fsl,enetc-ptp";
compatible = "pci1957,ee02", "fsl,enetc-ptp";
reg = <0x000400 0 0 0 0>;
clocks = <&clockgen QORIQ_CLK_HWACCEL 3>;
little-endian;
@@ -1143,7 +1147,7 @@
mscc_felix: ethernet-switch@0,5 {
reg = <0x000500 0 0 0 0>;
/* IEP INT_B */
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <2>;
status = "disabled";
mscc_felix_ports: ports {
@@ -1201,7 +1205,7 @@
};
enetc_port3: ethernet@0,6 {
compatible = "fsl,enetc";
compatible = "pci1957,e100", "fsl,enetc";
reg = <0x000600 0 0 0 0>;
phy-mode = "internal";
status = "disabled";
@@ -1216,7 +1220,7 @@
rcec@1f,0 {
reg = <0x00f800 0 0 0 0>;
/* IEP INT_A */
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <1>;
};
};

108
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@@ -748,7 +748,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c0_scl>;
pinctrl-1 = <&i2c0_scl_gpio>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -761,6 +764,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c1_scl>;
pinctrl-1 = <&i2c1_scl_gpio>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -773,6 +780,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c2_scl>;
pinctrl-1 = <&i2c2_scl_gpio>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -785,6 +796,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c3_scl>;
pinctrl-1 = <&i2c3_scl_gpio>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -797,7 +812,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c4_scl>;
pinctrl-1 = <&i2c4_scl_gpio>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -810,6 +828,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c5_scl>;
pinctrl-1 = <&i2c5_scl_gpio>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -822,6 +844,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c6_scl>;
pinctrl-1 = <&i2c6_scl_gpio>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -834,6 +860,10 @@
clock-names = "i2c";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&i2c7_scl>;
pinctrl-1 = <&i2c7_scl_gpio>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -1669,6 +1699,80 @@
};
};
pinmux_i2crv: pinmux@70010012c {
compatible = "pinctrl-single";
reg = <0x00000007 0x0010012c 0x0 0xc>;
#address-cells = <2>;
#size-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
i2c1_scl: i2c1-scl-pins {
pinctrl-single,bits = <0x0 0 0x7>;
};
i2c1_scl_gpio: i2c1-scl-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
i2c2_scl: i2c2-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
i2c2_scl_gpio: i2c2-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
i2c3_scl: i2c3-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
};
i2c3_scl_gpio: i2c3-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
i2c4_scl: i2c4-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
};
i2c4_scl_gpio: i2c4-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
i2c5_scl: i2c5-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
};
i2c5_scl_gpio: i2c5-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
i2c6_scl: i2c6-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
i2c6_scl_gpio: i2c6-scl-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
i2c7_scl: i2c7-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
i2c7_scl_gpio: i2c7-scl-gpio-pins {
pinctrl-single,bits = <0x4 0x1 0x7>;
};
i2c0_scl: i2c0-scl-pins {
pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
};
i2c0_scl_gpio: i2c0-scl-gpio-pins {
pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
};
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,

1
arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
View File

@@ -25,6 +25,7 @@
i2c7 = &mpcie1_i2c;
i2c8 = &mpcie0_i2c;
i2c9 = &pcieclk_i2c;
i2c10 = &i2c5;
mmc0 = &esdhc0;
mmc1 = &esdhc1;
serial0 = &uart0;

9
arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
View File

@@ -71,3 +71,12 @@
reg = <0x54>;
};
};
&i2c5 {
status = "okay";
rtc@6f {
compatible = "microchip,mcp7940x";
reg = <0x6f>;
};
};

285
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
View File

@@ -6,6 +6,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/firmware/imx/rsrc.h>
audio_ipg_clk: clock-audio-ipg {
@@ -119,13 +120,96 @@ audio_subsys: bus@59000000 {
#size-cells = <1>;
ranges = <0x59000000 0x0 0x59000000 0x1000000>;
asrc0: asrc@59000000 {
compatible = "fsl,imx8qm-asrc";
reg = <0x59000000 0x10000>;
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>,
<&asrc0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_4>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_4>,
<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "mem", "ipg",
"asrck_0", "asrck_1", "asrck_2", "asrck_3",
"asrck_4", "asrck_5", "asrck_6", "asrck_7",
"asrck_8", "asrck_9", "asrck_a", "asrck_b",
"asrck_c", "asrck_d", "asrck_e", "asrck_f",
"spba";
dmas = <&edma0 0 0 0>,
<&edma0 1 0 0>,
<&edma0 2 0 0>,
<&edma0 3 0 FSL_EDMA_RX>,
<&edma0 4 0 FSL_EDMA_RX>,
<&edma0 5 0 FSL_EDMA_RX>;
/* tx* is output channel of asrc, it is rx channel for eDMA */
dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
fsl,asrc-rate = <8000>;
fsl,asrc-width = <16>;
fsl,asrc-clk-map = <0>;
power-domains = <&pd IMX_SC_R_ASRC_0>;
status = "disabled";
};
esai0: esai@59010000 {
compatible = "fsl,imx8qm-esai";
reg = <0x59010000 0x10000>;
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&esai0_lpcg IMX_LPCG_CLK_4>,
<&esai0_lpcg IMX_LPCG_CLK_0>,
<&esai0_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>;
clock-names = "core", "extal", "fsys", "spba";
dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
dma-names = "rx", "tx";
power-domains = <&pd IMX_SC_R_ESAI_0>;
status = "disabled";
};
spdif0: spdif@59020000 {
compatible = "fsl,imx8qm-spdif";
reg = <0x59020000 0x10000>;
interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */
<&clk_dummy>, /* rxtx0 */
<&spdif0_lpcg IMX_LPCG_CLK_0>, /* rxtx1 */
<&clk_dummy>, /* rxtx2 */
<&clk_dummy>, /* rxtx3 */
<&clk_dummy>, /* rxtx4 */
<&audio_ipg_clk>, /* rxtx5 */
<&clk_dummy>, /* rxtx6 */
<&clk_dummy>, /* rxtx7 */
<&clk_dummy>; /* spba */
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
"rxtx5", "rxtx6", "rxtx7", "spba";
dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
<&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
dma-names = "rx", "tx";
power-domains = <&pd IMX_SC_R_SPDIF_0>;
status = "disabled";
};
sai0: sai@59040000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59040000 0x10000>;
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai0_lpcg 1>,
clocks = <&sai0_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
<&sai0_lpcg 0>,
<&sai0_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
@@ -139,9 +223,9 @@ audio_subsys: bus@59000000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59050000 0x10000>;
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai1_lpcg 1>,
clocks = <&sai1_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
<&sai1_lpcg 0>,
<&sai1_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
@@ -155,9 +239,9 @@ audio_subsys: bus@59000000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59060000 0x10000>;
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai2_lpcg 1>,
clocks = <&sai2_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
<&sai2_lpcg 0>,
<&sai2_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
@@ -171,9 +255,9 @@ audio_subsys: bus@59000000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59070000 0x10000>;
interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai3_lpcg 1>,
clocks = <&sai3_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
<&sai3_lpcg 0>,
<&sai3_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
@@ -239,6 +323,40 @@ audio_subsys: bus@59000000 {
<&pd IMX_SC_R_DMA_0_CH23>;
};
asrc0_lpcg: clock-controller@59400000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59400000 0x10000>;
#clock-cells = <1>;
clocks = <&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "asrc0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ASRC_0>;
};
esai0_lpcg: clock-controller@59410000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59410000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "esai0_lpcg_extal_clk",
"esai0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ESAI_0>;
};
spdif0_lpcg: clock-controller@59420000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59420000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "spdif0_lpcg_tx_clk",
"spdif0_lpcg_gclkw";
power-domains = <&pd IMX_SC_R_SPDIF_0>;
};
sai0_lpcg: clock-controller@59440000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59440000 0x10000>;
@@ -333,6 +451,101 @@ audio_subsys: bus@59000000 {
status = "disabled";
};
asrc1: asrc@59800000 {
compatible = "fsl,imx8qm-asrc";
reg = <0x59800000 0x10000>;
interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&asrc1_lpcg IMX_LPCG_CLK_4>,
<&asrc1_lpcg IMX_LPCG_CLK_4>,
<&aud_pll_div0_lpcg IMX_LPCG_CLK_0>,
<&aud_pll_div1_lpcg IMX_LPCG_CLK_0>,
<&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
<&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "mem", "ipg",
"asrck_0", "asrck_1", "asrck_2", "asrck_3",
"asrck_4", "asrck_5", "asrck_6", "asrck_7",
"asrck_8", "asrck_9", "asrck_a", "asrck_b",
"asrck_c", "asrck_d", "asrck_e", "asrck_f",
"spba";
dmas = <&edma1 0 0 0>,
<&edma1 1 0 0>,
<&edma1 2 0 0>,
<&edma1 3 0 FSL_EDMA_RX>,
<&edma1 4 0 FSL_EDMA_RX>,
<&edma1 5 0 FSL_EDMA_RX>;
/* tx* is output channel of asrc, it is rx channel for eDMA */
dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
fsl,asrc-rate = <8000>;
fsl,asrc-width = <16>;
fsl,asrc-clk-map = <1>;
power-domains = <&pd IMX_SC_R_ASRC_1>;
status = "disabled";
};
sai4: sai@59820000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59820000 0x10000>;
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai4_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
<&sai4_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
dma-names = "rx", "tx";
power-domains = <&pd IMX_SC_R_SAI_4>;
status = "disabled";
};
sai5: sai@59830000 {
compatible = "fsl,imx8qm-sai";
reg = <0x59830000 0x10000>;
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sai5_lpcg IMX_LPCG_CLK_4>,
<&clk_dummy>,
<&sai5_lpcg IMX_LPCG_CLK_0>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma1 10 0 0>;
dma-names = "tx";
power-domains = <&pd IMX_SC_R_SAI_5>;
status = "disabled";
};
amix: amix@59840000 {
compatible = "fsl,imx8qm-audmix";
reg = <0x59840000 0x10000>;
clocks = <&amix_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_AMIX>;
dais = <&sai4>, <&sai5>;
status = "disabled";
};
mqs: mqs@59850000 {
compatible = "fsl,imx8qm-mqs";
reg = <0x59850000 0x10000>;
clocks = <&mqs0_lpcg IMX_LPCG_CLK_4>, <&mqs0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk", "core";
power-domains = <&pd IMX_SC_R_MQS_0>;
status = "disabled";
};
edma1: dma-controller@599f0000 {
compatible = "fsl,imx8qm-edma";
reg = <0x599f0000 0xc0000>;
@@ -481,4 +694,60 @@ audio_subsys: bus@59000000 {
"sai3_rx_bclk",
"sai4_rx_bclk";
};
asrc1_lpcg: clock-controller@59c00000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59c00000 0x10000>;
#clock-cells = <1>;
clocks = <&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "asrc1_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_ASRC_1>;
};
sai4_lpcg: clock-controller@59c20000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59c20000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "sai4_lpcg_mclk",
"sai4_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_4>;
};
sai5_lpcg: clock-controller@59c30000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59c30000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "sai5_lpcg_mclk",
"sai5_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_SAI_5>;
};
amix_lpcg: clock-controller@59c40000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59c40000 0x10000>;
#clock-cells = <1>;
clocks = <&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>;
clock-output-names = "amix_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_AMIX>;
};
mqs0_lpcg: clock-controller@59c50000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x59c50000 0x10000>;
#clock-cells = <1>;
clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
<&audio_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "mqs0_lpcg_mclk",
"mqs0_lpcg_ipg_clk";
power-domains = <&pd IMX_SC_R_MQS_0>;
};
};

91
arch/arm64/boot/dts/freescale/imx8-ss-cm40.dtsi Normal file
View File

@@ -0,0 +1,91 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
* Dong Aisheng <aisheng.dong@nxp.com>
*/
#include <dt-bindings/firmware/imx/rsrc.h>
cm40_ipg_clk: clock-cm40-ipg {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <132000000>;
clock-output-names = "cm40_ipg_clk";
};
cm40_subsys: bus@34000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x34000000 0x0 0x34000000 0x4000000>;
interrupt-parent = <&cm40_intmux>;
cm40_lpuart: serial@37220000 {
compatible = "fsl,imx8qxp-lpuart";
reg = <0x37220000 0x1000>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cm40_uart_lpcg IMX_LPCG_CLK_1>, <&cm40_uart_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "baud";
assigned-clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_M4_0_UART>;
status = "disabled";
};
cm40_i2c: i2c@37230000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x37230000 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cm40_i2c_lpcg IMX_LPCG_CLK_0>,
<&cm40_i2c_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>;
assigned-clock-rates = <24000000>;
power-domains = <&pd IMX_SC_R_M4_0_I2C>;
status = "disabled";
};
cm40_intmux: intmux@37400000 {
compatible = "fsl,imx-intmux";
reg = <0x37400000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&cm40_ipg_clk>;
clock-names = "ipg";
power-domains = <&pd IMX_SC_R_M4_0_INTMUX>;
status = "disabled";
};
cm40_uart_lpcg: clock-controller@37620000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37620000 0x1000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_M4_0_UART IMX_SC_PM_CLK_PER>,
<&cm40_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>;
clock-output-names = "cm40_lpcg_uart_clk",
"cm40_lpcg_uart_ipg_clk";
power-domains = <&pd IMX_SC_R_M4_0_UART>;
};
cm40_i2c_lpcg: clock-controller@37630000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x37630000 0x1000>;
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_M4_0_I2C IMX_SC_PM_CLK_PER>,
<&cm40_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
clock-output-names = "cm40_lpcg_i2c_clk",
"cm40_lpcg_i2c_ipg_clk";
power-domains = <&pd IMX_SC_R_M4_0_I2C>;
};
};

2
arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
View File

@@ -21,7 +21,6 @@ img_subsys: bus@58000000 {
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;
@@ -35,7 +34,6 @@ img_subsys: bus@58000000 {
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
clock-names = "per", "ipg";
assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
assigned-clock-rates = <200000000>, <200000000>;

16
arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8dx-colibri.dtsi"
#include "imx8x-colibri-aster.dtsi"
/ {
model = "Toradex Colibri iMX8DX on Aster Board";
compatible = "toradex,colibri-imx8x-aster",
"toradex,colibri-imx8x",
"fsl,imx8dx";
};

16
arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8dx-colibri.dtsi"
#include "imx8x-colibri-eval-v3.dtsi"
/ {
model = "Toradex Colibri iMX8DX on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx8x-eval-v3",
"toradex,colibri-imx8x",
"fsl,imx8dx";
};

16
arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8dx-colibri.dtsi"
#include "imx8x-colibri-iris-v2.dtsi"
/ {
model = "Toradex Colibri iMX8DX on Colibri Iris V2 Board";
compatible = "toradex,colibri-imx8x-iris-v2",
"toradex,colibri-imx8x",
"fsl,imx8dx";
};

16
arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts Normal file
View File

@@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
/dts-v1/;
#include "imx8dx-colibri.dtsi"
#include "imx8x-colibri-iris.dtsi"
/ {
model = "Toradex Colibri iMX8DX on Colibri Iris Board";
compatible = "toradex,colibri-imx8x-iris",
"toradex,colibri-imx8x",
"fsl,imx8dx";
};

11
arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi Normal file
View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2018-2021 Toradex
*/
#include "imx8dx.dtsi"
#include "imx8x-colibri.dtsi"
/ {
model = "Toradex Colibri iMX8DX Module";
};

13
arch/arm64/boot/dts/freescale/imx8dx.dtsi Normal file
View File

@@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017-2020 NXP
*/
/dts-v1/;
#include "imx8dxp.dtsi"
&gpu_3d0 {
assigned-clock-rates = <372000000>, <372000000>;
};

37
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@@ -16,6 +16,8 @@
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial6 = &cm40_lpuart;
};
chosen {
@@ -51,6 +53,16 @@
};
};
m2_uart1_sel: regulator-m2uart1sel {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "m2_uart1_sel";
gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
mux3_en: regulator-0 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
@@ -340,6 +352,12 @@
status = "okay";
};
&lpuart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
@@ -354,6 +372,16 @@
status = "okay";
};
&cm40_intmux {
status = "disabled";
};
&cm40_lpuart {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cm40_lpuart>;
status = "disabled";
};
&lsio_gpio4 {
status = "okay";
};
@@ -595,6 +623,15 @@
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041

13
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View File

@@ -5,6 +5,7 @@
#include <dt-bindings/clock/imx8-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -231,6 +232,7 @@
};
/* sorted in register address */
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
@@ -241,3 +243,14 @@
#include "imx8dxl-ss-conn.dtsi"
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-ddr.dtsi"
&cm40_intmux {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};

19
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
View File

@@ -72,6 +72,20 @@
enable-active-high;
};
reg_1v5: regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vddext_3v3: regulator-vddext-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDEXT_3V3";
@@ -381,7 +395,7 @@
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
@@ -441,6 +455,9 @@
assigned-clock-rates = <24000000>;
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
DOVDD-supply = <&buck5_reg>;
AVDD-supply = <&reg_1v8>;
DVDD-supply = <&reg_1v5>;
port {
ov5640_to_mipi_csi2: endpoint {

1
arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts
View File

@@ -117,7 +117,6 @@
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
status = "okay";
};
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View File

@@ -57,7 +57,7 @@
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View File

@@ -297,7 +297,7 @@
};
tpm@1 {
compatible = "tcg,tpm_tis-spi";
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};

40
arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi
View File

@@ -10,7 +10,7 @@
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mm-wm8904";
simple-audio-card,name = "verdin-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
@@ -32,6 +32,25 @@
sound-dai = <&sai2>;
};
};
reg_usb_hub: regulator-usb-hub {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-name = "HUB_PWR_EN";
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-name = "PCIE_1_PWR_EN";
startup-delay-us = <100000>;
};
};
/* Verdin SPI_1 */
@@ -58,6 +77,11 @@
status = "okay";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
@@ -93,6 +117,7 @@
/* Verdin PCIE_1 */
&pcie0 {
vpcie-supply = <&reg_pcie>;
status = "okay";
};
@@ -115,6 +140,11 @@
status = "okay";
};
/* We support turning off sleep moci on Dahlia */
&reg_force_sleep_moci {
status = "disabled";
};
/* Verdin I2S_1 */
&sai2 {
status = "okay";
@@ -143,8 +173,16 @@
/* Verdin USB_2 */
&usbotg2 {
#address-cells = <1>;
#size-cells = <0>;
disable-over-current;
status = "okay";
usb-hub@1 {
compatible = "usb424,2744";
reg = <1>;
vdd-supply = <&reg_usb_hub>;
};
};
/* Verdin SD_1 */

7
arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi
View File

@@ -10,7 +10,7 @@
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mm-nau8822";
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
@@ -78,6 +78,11 @@
status = "okay";
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&gpio_expander_21 {
status = "okay";
};

5
arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi
View File

@@ -81,6 +81,11 @@
pinctrl-0 = <&pinctrl_gpios_ext_yavia>;
};
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&hwmon_temp {
status = "okay";
};

26
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@@ -110,6 +110,22 @@
startup-delay-us = <200000>;
};
/*
* By default we enable CTRL_SLEEP_MOCI#, this is required to have
* peripherals on the carrier board powered.
* If more granularity or power saving is required this can be disabled
* in the carrier board device tree files.
*/
reg_force_sleep_moci: regulator-force-sleep-moci {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio5 1 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
regulator-name = "CTRL_SLEEP_MOCI#";
};
reg_usb_otg1_vbus: regulator-usb-otg1 {
compatible = "regulator-fixed";
enable-active-high;
@@ -333,16 +349,6 @@
"SODIMM_212",
"SODIMM_151",
"SODIMM_153";
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <1 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
/* On-module I2C */

9
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@@ -1168,6 +1168,13 @@
remote-endpoint = <&lcdif_to_dsim>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
};
};
};
};
@@ -1253,7 +1260,6 @@
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
@@ -1274,7 +1280,6 @@
reg = <0x32e50000 0x200>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop2>;

16
arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts
View File

@@ -112,3 +112,19 @@
};
};
};
&i2c2 {
hdmi@3d {
avdd-supply = <&buck5>;
dvdd-supply = <&buck5>;
pvdd-supply = <&buck5>;
a2vdd-supply = <&buck5>;
v1p2-supply = <&buck5>;
};
};
&i2c3 {
camera@3c {
DOVDD-supply = <&buck5>;
};
};

16
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
View File

@@ -158,3 +158,19 @@
};
};
};
&i2c2 {
hdmi@3d {
avdd-supply = <&buck5_reg>;
dvdd-supply = <&buck5_reg>;
pvdd-supply = <&buck5_reg>;
a2vdd-supply = <&buck5_reg>;
v1p2-supply = <&buck5_reg>;
};
};
&i2c3 {
camera@3c {
DOVDD-supply = <&buck5_reg>;
};
};

16
arch/arm64/boot/dts/freescale/imx8mn-evk.dts
View File

@@ -125,3 +125,19 @@
};
};
};
&i2c2 {
hdmi@3d {
avdd-supply = <&buck5>;
dvdd-supply = <&buck5>;
pvdd-supply = <&buck5>;
a2vdd-supply = <&buck5>;
v1p2-supply = <&buck5>;
};
};
&i2c3 {
camera@3c {
DOVDD-supply = <&buck5>;
};
};

45
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
View File

@@ -30,7 +30,7 @@
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&adv7533_out>;
remote-endpoint = <&adv7535_out>;
};
};
};
@@ -52,6 +52,27 @@
enable-active-high;
};
reg_1v5: regulator-1v5 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V5";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
};
reg_1v8: regulator-1v8 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vddext_3v3: regulator-vddext-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDEXT_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@@ -193,15 +214,11 @@
hdmi@3d {
compatible = "adi,adv7535";
reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
reg-names = "main", "cec", "edid", "packet";
reg = <0x3d>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
adi,dsi-lanes = <4>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
v3p3-supply = <&reg_vddext_3v3>;
ports {
#address-cells = <1>;
@@ -210,7 +227,7 @@
port@0 {
reg = <0>;
adv7533_in: endpoint {
adv7535_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
@@ -218,7 +235,7 @@
port@1 {
reg = <1>;
adv7533_out: endpoint {
adv7535_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
@@ -227,7 +244,7 @@
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
reg = <0x50>;
@@ -284,6 +301,8 @@
assigned-clock-rates = <24000000>;
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
AVDD-supply = <&reg_1v8>;
DVDD-supply = <&reg_1v5>;
port {
ov5640_to_mipi_csi2: endpoint {
@@ -335,7 +354,7 @@
reg = <1>;
dsi_out: endpoint {
remote-endpoint = <&adv7533_in>;
remote-endpoint = <&adv7535_in>;
data-lanes = <1 2 3 4>;
};
};

1
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts
View File

@@ -126,7 +126,6 @@
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ptn5150>;
status = "okay";
port {
typec1_dr_sw: endpoint {

8
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@@ -1104,6 +1104,13 @@
remote-endpoint = <&lcdif_to_dsim>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
};
};
};
};
@@ -1213,7 +1220,6 @@
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
phys = <&usbphynop1>;

2
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
View File

@@ -340,7 +340,7 @@
&i2c3 {
/* Connected to USB Hub */
usb-typec@52 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;

2
arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
View File

@@ -197,10 +197,8 @@
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {

1
arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts
View File

@@ -144,7 +144,6 @@
pinctrl-0 = <&pinctrl_eqos>;
nvmem-cells = <&ethmac1>;
nvmem-cell-names = "mac-address";
phy-supply = <&reg_baseboard_vdd3v3>;
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
status = "okay";

10
arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts
View File

@@ -167,6 +167,16 @@
VDDIO-supply = <&reg_vdd_3p3v_awo>;
};
csi2exp: gpio@24 {
compatible = "nxp,pca9570";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"CSI2_#RESET", "CSI2_#PWDN",
"CSI_#PWDN", "CSI_#RESET";
};
typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;

45
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@@ -145,6 +145,27 @@
};
sound-hdmi {
compatible = "fsl,imx-audio-hdmi";
model = "audio-hdmi";
audio-cpu = <&aud2htx>;
hdmi-out;
};
sound-micfil {
compatible = "fsl,imx-audio-card";
model = "micfil-audio";
pri-dai-link {
link-name = "micfil hifi";
format = "i2s";
cpu {
sound-dai = <&micfil>;
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -198,6 +219,10 @@
cpu-supply = <&reg_arm>;
};
&aud2htx {
status = "okay";
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
@@ -524,6 +549,16 @@
status = "okay";
};
&micfil {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX8MP_CLK_PDM>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <196608000>;
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <10000000>;
status = "okay";
@@ -790,6 +825,16 @@
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6
MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6
MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0xd6
MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0xd6
MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0

46
arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi
View File

@@ -200,8 +200,11 @@
};
&i2c1 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <400000>;
status = "okay";
@@ -241,8 +244,11 @@
};
&i2c6 {
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c6>;
pinctrl-1 = <&pinctrl_i2c6_gpio>;
scl-gpios = <&gpio3 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
clock-frequency = <400000>;
status = "okay";
@@ -602,38 +608,50 @@
pinctrl_i2c1: i2c1grp {
fsl,pins =
<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3>;
<MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001e0>,
<MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001e0>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins =
<MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e0>,
<MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e0>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins =
<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3>;
<MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e0>,
<MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e0>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins =
<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3>;
<MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001e0>,
<MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001e0>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins =
<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3>,
<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3>;
<MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001e0>,
<MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001e0>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins =
<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3>,
<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3>;
<MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e0>,
<MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e0>;
};
pinctrl_i2c6: i2c6grp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3>,
<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3>;
<MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001e0>,
<MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001e0>;
};
pinctrl_i2c6_gpio: i2c6gpiogrp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x1e0>,
<MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x1e0>;
};
pinctrl_lcd0_backlight: lcd0-backlightgrp {

424
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts Normal file
View File

@@ -0,0 +1,424 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2021 Emcraft Systems
* Copyright 2024 Gilles Talis <gilles.talis@gmail.com>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include "imx8mp.dtsi"
/ {
model = "Emcraft Systems i.MX8MPlus NavQ+ Kit";
compatible = "emcraft,imx8mp-navqp", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_STATUS;
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <12000>;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&eqos {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <1000>;
reset-deassert-us = <10000>;
qca,disable-smarteee;
qca,disable-hibernation-mode;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
regulators {
BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
};
};
&uart2 {
/* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* SD Card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
/* eMMC */
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x110
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};

38
arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts
View File

@@ -135,6 +135,18 @@
};
};
hdmi-connector {
compatible = "hdmi-connector";
label = "X44";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
display: display {
/*
* Display is not fixed, so compatible has to be added from
@@ -470,6 +482,28 @@
"", "", "", "";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c2 {
clock-frequency = <384000>;
pinctrl-names = "default", "gpio";
@@ -531,6 +565,10 @@
status = "okay";
};
&lcdif3 {
status = "okay";
};
&pcf85063 {
/* RTC_EVENT# is connected on MBa8MPxL */
pinctrl-names = "default";

2
arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi
View File

@@ -68,7 +68,7 @@
status = "okay";
tpm@1 {
compatible = "tcg,tpm_tis-spi";
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x1>;
spi-max-frequency = <36000000>;
};

36
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
View File

@@ -8,6 +8,10 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
aliases {
ethernet1 = &eth1;
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
pinctrl-names = "default";
@@ -151,6 +155,38 @@
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@3,0 {
reg = <0x1800 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
local-mac-address = [00 00 00 00 00 00];
};
};
};
};
};
/* GPS */

36
arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
View File

@@ -8,6 +8,10 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
aliases {
ethernet1 = &eth1;
};
connector {
compatible = "gpio-usb-b-connector", "usb-b-connector";
pinctrl-names = "default";
@@ -163,6 +167,38 @@
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@4,0 {
reg = <0x2000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
local-mac-address = [00 00 00 00 00 00];
};
};
};
};
};
/* GPS */

13
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso
View File

@@ -62,12 +62,25 @@
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipi_csi_0_in: endpoint {
remote-endpoint = <&imx219_to_mipi_csi2>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
mipi_csi_0_out: endpoint {
remote-endpoint = <&isi_in_0>;
};
};
};
};

6
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@@ -404,6 +404,12 @@
label = "vdd_dram";
};
channel@9e {
gw,mode = <2>;
reg = <0x9e>;
label = "vdd_1p0";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;

56
arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi
View File

@@ -10,7 +10,7 @@
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mp-wm8904";
simple-audio-card,name = "verdin-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
@@ -32,6 +32,25 @@
sound-dai = <&sai1>;
};
};
reg_usb_hub: regulator-usb-hub {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-name = "HUB_PWR_EN";
};
reg_pcie: regulator-pcie {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
regulator-name = "PCIE_1_PWR_EN";
startup-delay-us = <100000>;
};
};
&backlight {
@@ -70,6 +89,11 @@
status = "okay";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
/* Current measurement into module VCC */
&hwmon {
status = "okay";
@@ -110,8 +134,14 @@
};
};
/* Verdin I2C_3_HDMI */
&i2c5 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
vpcie-supply = <&reg_pcie>;
status = "okay";
};
@@ -138,6 +168,11 @@
vin-supply = <&reg_3p3v>;
};
/* We support turning off sleep moci on Dahlia */
&reg_force_sleep_moci {
status = "disabled";
};
/* Verdin I2S_1 */
&sai1 {
assigned-clocks = <&clk IMX8MP_CLK_SAI1>;
@@ -181,6 +216,25 @@
status = "okay";
};
&usb_dwc3_1 {
#address-cells = <1>;
#size-cells = <0>;
usb_hub_3_0: usb-hub@1 {
compatible = "usb424,5744";
reg = <1>;
peer-hub = <&usb_hub_2_0>;
vdd-supply = <&reg_usb_hub>;
};
usb_hub_2_0: usb-hub@2 {
compatible = "usb424,2744";
reg = <2>;
peer-hub = <&usb_hub_3_0>;
vdd-supply = <&reg_usb_hub>;
};
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";

12
arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi
View File

@@ -22,7 +22,7 @@
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mp-nau8822";
simple-audio-card,name = "verdin-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
@@ -93,6 +93,11 @@
status = "okay";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&gpio_expander_21 {
status = "okay";
vcc-supply = <&reg_1p8v>;
@@ -131,6 +136,11 @@
};
};
/* Verdin I2C_3_HDMI */
&i2c5 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";

5
arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi
View File

@@ -112,6 +112,11 @@
status = "okay";
};
/* Verdin I2C_3_HDMI */
&i2c5 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";

10
arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi
View File

@@ -100,6 +100,11 @@
status = "okay";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
&hwmon_temp {
status = "okay";
};
@@ -117,6 +122,11 @@
status = "okay";
};
/* Verdin I2C_3_HDMI */
&i2c5 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";

53
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View File

@@ -116,6 +116,22 @@
vin-supply = <&reg_vdd_3v3>;
};
/*
* By default we enable CTRL_SLEEP_MOCI#, this is required to have
* peripherals on the carrier board powered.
* If more granularity or power saving is required this can be disabled
* in the carrier board device tree files.
*/
reg_force_sleep_moci: regulator-force-sleep-moci {
compatible = "regulator-fixed";
enable-active-high;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
regulator-always-on;
regulator-boot-on;
regulator-name = "CTRL_SLEEP_MOCI#";
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
enable-active-high;
@@ -439,16 +455,6 @@
"SODIMM_256",
"SODIMM_48",
"SODIMM_44";
ctrl-sleep-moci-hog {
gpio-hog;
/* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "CTRL_SLEEP_MOCI#";
output-high;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
};
};
/* On-module I2C */
@@ -664,8 +670,6 @@
};
};
/* TODO: Verdin I2C_3_HDMI */
/* Verdin I2C_4_CSI */
&i2c3 {
clock-frequency = <400000>;
@@ -764,6 +768,16 @@
};
};
/* Verdin I2C_3_HDMI */
&i2c5 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c5>;
pinctrl-1 = <&pinctrl_i2c5_gpio>;
scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
/* Verdin PCIE_1 */
&pcie {
pinctrl-names = "default";
@@ -1106,8 +1120,6 @@
pinctrl_hdmi_hog: hdmihoggrp {
fsl,pins =
<MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
<MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
<MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
<MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
};
@@ -1163,6 +1175,19 @@
<MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
};
/* Verdin I2C_3_HDMI */
pinctrl_i2c5: i2c5grp {
fsl,pins =
<MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400001c6>, /* SODIMM 59 */
<MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400001c6>; /* SODIMM 57 */
};
pinctrl_i2c5_gpio: i2c5gpiogrp {
fsl,pins =
<MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x400001c6>, /* SODIMM 59 */
<MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x400001c6>; /* SODIMM 57 */
};
/* Verdin I2S_2_BCLK (TOUCH_RESET#) */
pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
fsl,pins =

168
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@@ -836,6 +836,23 @@
<&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
};
pgc_hdmimix: power-domain@14 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
<&clk IMX8MP_CLK_HDMI_APB>;
assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
<&clk IMX8MP_CLK_HDMI_APB>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL1_133M>;
assigned-clock-rates = <500000000>, <133000000>;
};
pgc_hdmi_phy: power-domain@15 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
};
pgc_mipi_phy2: power-domain@16 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
@@ -1513,6 +1530,16 @@
status = "disabled";
};
aud2htx: aud2htx@30cb0000 {
compatible = "fsl,imx8mp-aud2htx";
reg = <0x30cb0000 0x10000>;
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>;
clock-names = "bus";
dmas = <&sdma2 26 2 0>;
dma-names = "tx";
status = "disabled";
};
};
sdma3: dma-controller@30e00000 {
@@ -1630,7 +1657,7 @@
compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
reg = <0x32e40000 0x10000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <500000000>;
clock-frequency = <266000000>;
clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
<&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
@@ -1640,7 +1667,7 @@
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_CLK_24M>;
assigned-clock-rates = <500000000>;
assigned-clock-rates = <266000000>;
power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
status = "disabled";
@@ -1725,6 +1752,13 @@
remote-endpoint = <&lcdif1_to_dsim>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
};
};
};
};
@@ -1889,6 +1923,136 @@
#power-domain-cells = <1>;
#clock-cells = <0>;
};
hdmi_blk_ctrl: blk-ctrl@32fc0000 {
compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
reg = <0x32fc0000 0x1000>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_ROOT>,
<&clk IMX8MP_CLK_HDMI_REF_266M>,
<&clk IMX8MP_CLK_HDMI_24M>,
<&clk IMX8MP_CLK_HDMI_FDCC_TST>;
clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmimix>,
<&pgc_hdmimix>, <&pgc_hdmi_phy>,
<&pgc_hdmimix>, <&pgc_hdmimix>;
power-domain-names = "bus", "irqsteer", "lcdif",
"pai", "pvi", "trng",
"hdmi-tx", "hdmi-tx-phy",
"hdcp", "hrv";
#power-domain-cells = <1>;
};
irqsteer_hdmi: interrupt-controller@32fc2000 {
compatible = "fsl,imx-irqsteer";
reg = <0x32fc2000 0x1000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
fsl,channel = <1>;
fsl,num-irqs = <64>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>;
clock-names = "ipg";
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
};
hdmi_pvi: display-bridge@32fc4000 {
compatible = "fsl,imx8mp-hdmi-pvi";
reg = <0x32fc4000 0x1000>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <12>;
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
pvi_from_lcdif3: endpoint {
remote-endpoint = <&lcdif3_to_pvi>;
};
};
port@1 {
reg = <1>;
pvi_to_hdmi_tx: endpoint {
remote-endpoint = <&hdmi_tx_from_pvi>;
};
};
};
};
lcdif3: display-controller@32fc6000 {
compatible = "fsl,imx8mp-lcdif";
reg = <0x32fc6000 0x1000>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <8>;
clocks = <&hdmi_tx_phy>,
<&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_ROOT>;
clock-names = "pix", "axi", "disp_axi";
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
status = "disabled";
port {
lcdif3_to_pvi: endpoint {
remote-endpoint = <&pvi_from_lcdif3>;
};
};
};
hdmi_tx: hdmi@32fd8000 {
compatible = "fsl,imx8mp-hdmi-tx";
reg = <0x32fd8000 0x7eff>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <0>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_REF_266M>,
<&clk IMX8MP_CLK_32K>,
<&hdmi_tx_phy>;
clock-names = "iahb", "isfr", "cec", "pix";
assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
reg-io-width = <1>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_tx_from_pvi: endpoint {
remote-endpoint = <&pvi_to_hdmi_tx>;
};
};
port@1 {
reg = <1>;
/* Point endpoint to the HDMI connector */
};
};
};
hdmi_tx_phy: phy@32fdff00 {
compatible = "fsl,imx8mp-hdmi-phy";
reg = <0x32fdff00 0x100>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>,
<&clk IMX8MP_CLK_HDMI_24M>;
clock-names = "apb", "ref";
assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
};
pcie: pcie@33800000 {

2
arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
View File

@@ -42,7 +42,7 @@
status = "okay";
typec_ptn5100: usb-typec@50 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;

2
arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
View File

@@ -429,7 +429,7 @@
};
typec_ptn5100: usb-typec@52 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;

7
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@@ -1290,6 +1290,13 @@
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
};
};
};
};

86
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@@ -39,6 +39,20 @@
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0>;
vref-supply = <&reg_vref_1v8>;
status = "okay";
};
&i2c1 {
@@ -71,6 +85,37 @@
status = "okay";
};
&lpspi2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi2 &pinctrl_lpspi2_cs>;
cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
reg = <0>;
compatible = "rohm,dh2228fv";
spi-max-frequency = <30000000>;
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <133000000>;
spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@@ -130,6 +175,12 @@
>;
};
pinctrl_adc0: adc0grp {
fsl,pins = <
IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020
@@ -149,6 +200,41 @@
>;
};
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x06000040
IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x06000040
IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x06000040
>;
};
pinctrl_lpspi2_cs: lpspi2csgrp {
fsl,pins = <
IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x21
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
IMX8QM_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
IMX8QM_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
IMX8QM_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
IMX8QM_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
IMX8QM_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
IMX8QM_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
IMX8QM_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021
IMX8QM_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
IMX8QM_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
IMX8QM_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
IMX8QM_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
IMX8QM_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
IMX8QM_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
IMX8QM_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
IMX8QM_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
IMX8QM_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020

140
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@@ -44,6 +44,22 @@
};
};
};
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
audio-cpu = <&sai1>;
audio-codec = <&wm8960>;
hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
audio-routing = "Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Mic Jack",
"Mic Jack", "MICB";
};
};
&dsp {
@@ -149,7 +165,7 @@
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110";
compatible = "nxp,ptn5110", "tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x50>;
@@ -188,6 +204,47 @@
};
&cm40_i2c {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_cm40_i2c>;
pinctrl-1 = <&pinctrl_cm40_i2c_gpio>;
scl-gpios = <&lsio_gpio1 10 GPIO_ACTIVE_HIGH>;
sda-gpios = <&lsio_gpio1 9 GPIO_ACTIVE_HIGH>;
status = "okay";
wm8960: audio-codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>,
<49152000>,
<12288000>,
<12288000>;
wlf,shared-lrclk;
wlf,hp-cfg = <2 2 3>;
wlf,gpio-cfg = <1 3>;
};
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
};
&cm40_intmux {
status = "okay";
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
@@ -218,6 +275,53 @@
status = "okay";
};
&sai0 {
#sound-dai-cells = <0>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai0>;
status = "okay";
};
&sai1 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&sai4 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai4_lpcg IMX_LPCG_CLK_0>;
assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
status = "okay";
};
&sai5 {
assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>,
<&sai5_lpcg IMX_LPCG_CLK_0>;
assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
status = "okay";
};
&thermal_zones {
pmic-thermal {
polling-delay-passive = <250>;
@@ -314,6 +418,21 @@
};
&iomuxc {
pinctrl_cm40_i2c: cm40i2cgrp {
fsl,pins = <
IMX8QXP_ADC_IN1_M40_I2C0_SDA 0x0600004c
IMX8QXP_ADC_IN0_M40_I2C0_SCL 0x0600004c
>;
};
pinctrl_cm40_i2c_gpio: cm40i2cgpio-grp {
fsl,pins = <
IMX8QXP_ADC_IN1_LSIO_GPIO1_IO09 0xc600004c
IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
@@ -385,6 +504,25 @@
>;
};
pinctrl_sai0: sai0grp {
fsl,pins = <
IMX8QXP_SAI0_TXD_ADMA_SAI0_TXD 0x06000060
IMX8QXP_SAI0_RXD_ADMA_SAI0_RXD 0x06000040
IMX8QXP_SAI0_TXC_ADMA_SAI0_TXC 0x06000040
IMX8QXP_SAI0_TXFS_ADMA_SAI0_TXFS 0x06000040
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040
IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040
IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040
IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000060
IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041

1
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@@ -317,6 +317,7 @@
/* sorted in register address */
#include "imx8-ss-img.dtsi"
#include "imx8-ss-vpu.dtsi"
#include "imx8-ss-cm40.dtsi"
#include "imx8-ss-gpu0.dtsi"
#include "imx8-ss-adma.dtsi"
#include "imx8-ss-conn.dtsi"

84
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
View File

@@ -127,12 +127,70 @@
pinctrl-1 = <&pinctrl_lpi2c7>;
status = "okay";
ptn5150_1: typec@1d {
compatible = "nxp,ptn5150";
reg = <0x1d>;
int-gpios = <&gpiof 3 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec1>;
status = "disabled";
};
pcal6408: gpio@21 {
compatible = "nxp,pcal9554b";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
ptn5150_2: typec@3d {
compatible = "nxp,ptn5150";
reg = <0x3d>;
int-gpios = <&gpiof 5 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec2>;
status = "disabled";
};
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
over-current-active-low;
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <110>;
status = "okay";
};
&usbmisc1 {
status = "okay";
};
&usbotg2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
over-current-active-low;
status = "okay";
};
&usbphy2 {
fsl,tx-d-cal = <110>;
status = "okay";
};
&usbmisc2 {
status = "okay";
};
&usdhc0 {
@@ -224,6 +282,32 @@
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8ULP_PAD_PTF3__PTF3 0x3
>;
};
pinctrl_typec2: typec2grp {
fsl,pins = <
MX8ULP_PAD_PTF5__PTF5 0x3
>;
};
pinctrl_usb1: usb1grp {
fsl,pins = <
MX8ULP_PAD_PTF2__USB0_ID 0x10003
MX8ULP_PAD_PTF4__USB0_OC 0x10003
>;
};
pinctrl_usb2: usb2grp {
fsl,pins = <
MX8ULP_PAD_PTD23__USB1_ID 0x10003
MX8ULP_PAD_PTF6__USB1_OC 0x10003
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
MX8ULP_PAD_PTD1__SDHC0_CMD 0x3

94
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@@ -252,6 +252,38 @@
#reset-cells = <1>;
};
crypto: crypto@292e0000 {
compatible = "fsl,sec-v4.0";
reg = <0x292e0000 0x10000>;
ranges = <0 0x292e0000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
};
};
tpm5: tpm@29340000 {
compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
reg = <0x29340000 0x1000>;
@@ -472,6 +504,68 @@
status = "disabled";
};
usbotg1: usb@29900000 {
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
reg = <0x29900000 0x200>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB0>;
power-domains = <&scmi_devpd IMX8ULP_PD_USB0>;
phys = <&usbphy1>;
fsl,usbmisc = <&usbmisc1 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
rx-burst-size-dword = <0x8>;
status = "disabled";
};
usbmisc1: usbmisc@29900200 {
compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x29900200 0x200>;
#index-cells = <1>;
status = "disabled";
};
usbphy1: usb-phy@29910000 {
compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
reg = <0x29910000 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
#phy-cells = <0>;
status = "disabled";
};
usbotg2: usb@29920000 {
compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
reg = <0x29920000 0x200>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB1>;
power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
phys = <&usbphy2>;
fsl,usbmisc = <&usbmisc2 0>;
ahb-burst-config = <0x0>;
tx-burst-size-dword = <0x8>;
rx-burst-size-dword = <0x8>;
status = "disabled";
};
usbmisc2: usbmisc@29920200 {
compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x29920200 0x200>;
#index-cells = <1>;
status = "disabled";
};
usbphy2: usb-phy@29930000 {
compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
reg = <0x29930000 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
#phy-cells = <0>;
status = "disabled";
};
fec: ethernet@29950000 {
compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
reg = <0x29950000 0x10000>;

397
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View File

@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/usb/pd.h>
#include "imx93.dtsi"
/ {
@@ -38,7 +39,7 @@
no-map;
};
vdev1vring0: vdev1vring0@a4000000 {
vdev1vring0: vdev1vring0@a4010000 {
reg = <0 0xa4010000 0 0x8000>;
no-map;
};
@@ -48,8 +49,8 @@
no-map;
};
rsc_table: rsc-table@2021f000 {
reg = <0 0x2021f000 0 0x1000>;
rsc_table: rsc-table@2021e000 {
reg = <0 0x2021e000 0 0x1000>;
no-map;
};
@@ -104,9 +105,85 @@
status = "okay";
};
&eqos {
&lpi2c3 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
typec1_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
ptn5110_2: tcpc@51 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x51>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
typec2_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec2_dr_sw: endpoint {
remote-endpoint = <&usb2_drd_sw>;
};
};
};
};
};
};
&eqos {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay";
@@ -120,13 +197,17 @@
ethphy1: ethernet-phy@1 {
reg = <1>;
eee-broken-1000t;
reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy2>;
fsl,magic-packet;
@@ -140,6 +221,9 @@
ethphy2: ethernet-phy@2 {
reg = <2>;
eee-broken-1000t;
reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <80000>;
};
};
};
@@ -156,21 +240,58 @@
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb1_drd_sw: endpoint {
remote-endpoint = <&typec1_dr_sw>;
};
};
};
&usbotg2 {
dr_mode = "otg";
hnp-disable;
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
port {
usb2_drd_sw: endpoint {
remote-endpoint = <&typec2_dr_sw>;
};
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1>;
pinctrl-2 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
@@ -183,6 +304,118 @@
status = "okay";
};
&lpi2c2 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-1 = <&pinctrl_lpi2c2>;
status = "okay";
pcal6524: gpio@22 {
compatible = "nxp,pcal6524";
reg = <0x22>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6524>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio3>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
};
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
interrupt-parent = <&pcal6524>;
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <610000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <670000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
regulator-name = "BUCK4";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5{
regulator-name = "BUCK5";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <1060000>;
regulator-max-microvolt = <1140000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <840000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
pcf2131: rtc@53 {
compatible = "nxp,pcf2131";
reg = <0x53>;
interrupt-parent = <&pcal6524>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
};
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
@@ -203,6 +436,25 @@
>;
};
pinctrl_eqos_sleep: eqossleepgrp {
fsl,pins = <
MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
@@ -222,6 +474,32 @@
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_fec_sleep: fecsleepgrp {
fsl,pins = <
MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
@@ -238,8 +516,62 @@
>;
};
pinctrl_lpi2c2: lpi2c2grp {
fsl,pins = <
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_pcal6524: pcal6524grp {
fsl,pins = <
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
@@ -267,8 +599,40 @@
>;
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
/* need to config the SION for data and cmd pad, refer to ERR052021 */
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
@@ -279,4 +643,17 @@
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
>;
};
pinctrl_usdhc2_sleep: usdhc2sleepgrp {
fsl,pins = <
MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
>;
};
};

140
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx93-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -183,6 +184,20 @@
status = "disabled";
};
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
clock-names = "main_clk";
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>;
clock-names = "main_clk";
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -316,6 +331,8 @@
clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
<&clk IMX93_CLK_BUS_AON>;
clock-names = "per", "ipg";
dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -328,6 +345,8 @@
clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
<&clk IMX93_CLK_BUS_AON>;
clock-names = "per", "ipg";
dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -340,6 +359,8 @@
clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
<&clk IMX93_CLK_BUS_AON>;
clock-names = "per", "ipg";
dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -352,6 +373,8 @@
clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
<&clk IMX93_CLK_BUS_AON>;
clock-names = "per", "ipg";
dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -361,7 +384,7 @@
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART1_GATE>;
clock-names = "ipg";
dmas = <&edma1 17 0 1>, <&edma1 16 0 0>;
dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -372,7 +395,7 @@
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART2_GATE>;
clock-names = "ipg";
dmas = <&edma1 19 0 1>, <&edma1 18 0 0>;
dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -400,7 +423,7 @@
<&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma1 22 0 1>, <&edma1 21 0 0>;
dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -509,8 +532,7 @@
reg = <0x44530000 0x10000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_ADC1_GATE>;
clock-names = "ipg";
#io-channel-cells = <1>;
@@ -693,6 +715,8 @@
clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -705,6 +729,8 @@
clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -717,6 +743,8 @@
clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -729,6 +757,8 @@
clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -738,7 +768,7 @@
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART3_GATE>;
clock-names = "ipg";
dmas = <&edma2 18 0 1>, <&edma2 17 0 0>;
dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -749,7 +779,7 @@
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART4_GATE>;
clock-names = "ipg";
dmas = <&edma2 20 0 1>, <&edma2 19 0 0>;
dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -760,7 +790,7 @@
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART5_GATE>;
clock-names = "ipg";
dmas = <&edma2 22 0 1>, <&edma2 21 0 0>;
dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -771,7 +801,7 @@
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART6_GATE>;
clock-names = "ipg";
dmas = <&edma2 24 0 1>, <&edma2 23 0 0>;
dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -814,7 +844,7 @@
<&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma2 59 0 1>, <&edma2 58 0 0>;
dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -827,7 +857,7 @@
<&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma2 61 0 1>, <&edma2 60 0 0>;
dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -846,7 +876,7 @@
<&clk IMX93_CLK_DUMMY>,
<&clk IMX93_CLK_AUD_XCVR_GATE>;
clock-names = "ipg", "phy", "spba", "pll_ipg";
dmas = <&edma2 65 0 1>, <&edma2 66 0 0>;
dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -857,7 +887,7 @@
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART7_GATE>;
clock-names = "ipg";
dmas = <&edma2 88 0 1>, <&edma2 87 0 0>;
dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -868,7 +898,7 @@
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_LPUART8_GATE>;
clock-names = "ipg";
dmas = <&edma2 90 0 1>, <&edma2 89 0 0>;
dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -882,6 +912,8 @@
clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -894,6 +926,8 @@
clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -906,6 +940,8 @@
clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -918,6 +954,8 @@
clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -930,6 +968,8 @@
clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -942,6 +982,8 @@
clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -954,6 +996,8 @@
clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -966,6 +1010,8 @@
clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
<&clk IMX93_CLK_BUS_WAKEUP>;
clock-names = "per", "ipg";
dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -986,6 +1032,9 @@
<&clk IMX93_CLK_WAKEUP_AXI>,
<&clk IMX93_CLK_USDHC1_GATE>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX93_CLK_USDHC1>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
@@ -1000,6 +1049,9 @@
<&clk IMX93_CLK_WAKEUP_AXI>,
<&clk IMX93_CLK_USDHC2_GATE>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX93_CLK_USDHC2>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
assigned-clock-rates = <400000000>;
bus-width = <4>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
@@ -1030,6 +1082,8 @@
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
nvmem-cells = <&eth_mac1>;
nvmem-cell-names = "mac-address";
status = "disabled";
};
@@ -1052,6 +1106,8 @@
assigned-clock-rates = <100000000>, <250000000>;
intf_mode = <&wakeupmix_gpr 0x28>;
snps,clk-csr = <0>;
nvmem-cells = <&eth_mac2>;
nvmem-cell-names = "mac-address";
status = "disabled";
};
@@ -1063,6 +1119,9 @@
<&clk IMX93_CLK_WAKEUP_AXI>,
<&clk IMX93_CLK_USDHC3_GATE>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX93_CLK_USDHC3>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
assigned-clock-rates = <400000000>;
bus-width = <4>;
fsl,tuning-start-tap = <1>;
fsl,tuning-step = <2>;
@@ -1136,6 +1195,15 @@
reg = <0x47510000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
eth_mac1: mac-address@4ec {
reg = <0x4ec 0x6>;
};
eth_mac2: mac-address@4f2 {
reg = <0x4f2 0x6>;
};
};
s4muap: mailbox@47520000 {
@@ -1167,6 +1235,50 @@
status = "disabled";
};
usbotg1: usb@4c100000 {
compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x4c100000 0x200>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
<&clk IMX93_CLK_HSIO_32K_GATE>;
clock-names = "usb_ctrl_root", "usb_wakeup";
assigned-clocks = <&clk IMX93_CLK_HSIO>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <133000000>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
};
usbmisc1: usbmisc@4c100200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x4c100200 0x200>;
#index-cells = <1>;
};
usbotg2: usb@4c200000 {
compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x4c200000 0x200>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>,
<&clk IMX93_CLK_HSIO_32K_GATE>;
clock-names = "usb_ctrl_root", "usb_wakeup";
assigned-clocks = <&clk IMX93_CLK_HSIO>;
assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
assigned-clock-rates = <133000000>;
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
status = "disabled";
};
usbmisc2: usbmisc@4c200200 {
compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
"fsl,imx6q-usbmisc";
reg = <0x4c200200 0x200>;
#index-cells = <1>;
};
ddr-pmu@4e300dc0 {
compatible = "fsl,imx93-ddr-pmu";
reg = <0x4e300dc0 0x200>;

14
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View File

@@ -316,17 +316,11 @@
&mipi_dsi {
samsung,burst-clock-frequency = <891000000>;
samsung,esc-clock-frequency = <20000000>;
};
ports {
port@1 {
reg = <1>;
mipi_dsi_out: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&lvds_bridge_in>;
};
};
};
&mipi_dsi_out {
data-lanes = <1 2 3 4>;
remote-endpoint = <&lvds_bridge_in>;
};
&pwm3 {

37
arch/arm64/boot/dts/freescale/s32g2.dtsi
View File

@@ -3,7 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2017-2021 NXP
* Copyright 2017-2021, 2024 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -14,6 +14,18 @@
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scmi_buf: shm@d0000000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0xd0000000 0x0 0x80>;
no-map;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -77,6 +89,19 @@
};
firmware {
scmi {
compatible = "arm,scmi-smc";
arm,smc-id = <0xc20000fe>;
#address-cells = <1>;
#size-cells = <0>;
shmem = <&scmi_buf>;
clks: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -113,6 +138,16 @@
status = "disabled";
};
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 32>, <&clks 31>, <&clks 33>;
clock-names = "ipg", "ahb", "per";
bus-width = <8>;
status = "disabled";
};
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
reg = <0x50800000 0x10000>,

6
arch/arm64/boot/dts/freescale/s32g274a-evb.dts
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2019-2021 NXP
* Copyright 2019-2021, 2024 NXP
*/
/dts-v1/;
@@ -32,3 +32,7 @@
&uart0 {
status = "okay";
};
&usdhc0 {
status = "okay";
};

6
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2019-2021 NXP
* Copyright 2019-2021, 2024 NXP
*/
/dts-v1/;
@@ -38,3 +38,7 @@
&uart1 {
status = "okay";
};
&usdhc0 {
status = "okay";
};

233
arch/arm64/boot/dts/freescale/s32g3.dtsi Normal file
View File

@@ -0,0 +1,233 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2021-2023 NXP
*
* Authors: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
* Ciprian Costea <ciprianmarian.costea@nxp.com>
* Andra-Teodora Ilie <andra.ilie@nxp.com>
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "nxp,s32g3";
interrupt-parent = <&gic>;
#address-cells = <0x02>;
#size-cells = <0x02>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
cluster1 {
core0 {
cpu = <&cpu4>;
};
core1 {
cpu = <&cpu5>;
};
core2 {
cpu = <&cpu6>;
};
core3 {
cpu = <&cpu7>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x101>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x102>;
enable-method = "psci";
clocks = <&dfs 0>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x103>;
enable-method = "psci";
clocks = <&dfs 0>;
};
};
firmware {
scmi: scmi {
compatible = "arm,scmi-smc";
shmem = <&scmi_shmem>;
arm,smc-id = <0xc20000fe>;
#address-cells = <1>;
#size-cells = <0>;
dfs: protocol@13 {
reg = <0x13>;
#clock-cells = <1>;
};
clks: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
psci: psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
scmi_shmem: shm@d0000000 {
compatible = "arm,scmi-shmem";
reg = <0x0 0xd0000000 0x0 0x80>;
no-map;
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
uart0: serial@401c8000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x401c8000 0x3000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart1: serial@401cc000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x401cc000 0x3000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart2: serial@402bc000 {
compatible = "nxp,s32g3-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x402bc000 0x3000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
usdhc0: mmc@402f0000 {
compatible = "nxp,s32g3-usdhc",
"nxp,s32g2-usdhc";
reg = <0x402f0000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 32>,
<&clks 31>,
<&clks 33>;
clock-names = "ipg", "ahb", "per";
status = "disabled";
};
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x50800000 0x10000>,
<0x50900000 0x200000>,
<0x50400000 0x2000>,
<0x50410000 0x2000>,
<0x50420000 0x2000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* sec-phys */
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* phys */
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* virt */
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, /* hyp-phys */
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; /* hyp-virt */
arm,no-tick-in-suspend;
};
};

45
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts Normal file
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@@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* Copyright 2021-2023 NXP
*
* NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)
*/
/dts-v1/;
#include "s32g3.dtsi"
/ {
model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)";
compatible = "nxp,s32g399a-rdb3", "nxp,s32g3";
aliases {
mmc0 = &usdhc0;
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
/* 4GiB RAM */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>,
<0x8 0x80000000 0 0x80000000>;
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usdhc0 {
bus-width = <8>;
status = "okay";
};