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arm64: dts: qcom: sm6115: Add GPUCC and Adreno SMMU

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Add GPUCC and Adreno SMMU nodes in preparation for adding the GPU
itself.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230315-topic-kamorta_adrsmmu-v1-2-d1c0dea90bd9@linaro.org
This commit is contained in:
Konrad Dybcio
2023-03-15 11:52:09 +01:00
committed by Bjorn Andersson
parent 7c3a3554ba
commit fc7c39d61c
1 changed files with 38 additions and 0 deletions
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38
arch/arm64/boot/dts/qcom/sm6115.dtsi
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@@ -5,6 +5,7 @@
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
@@ -1111,6 +1112,43 @@
};
};
gpucc: clock-controller@5990000 {
compatible = "qcom,sm6115-gpucc";
reg = <0x0 0x05990000 0x0 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
adreno_smmu: iommu@59a0000 {
compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x059a0000 0x0 0x10000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
clock-names = "mem",
"hlos",
"iface";
power-domains = <&gpucc GPU_CX_GDSC>;
#global-interrupts = <1>;
#iommu-cells = <2>;
};
mdss: display-subsystem@5e00000 {
compatible = "qcom,sm6115-mdss";
reg = <0x0 0x05e00000 0x0 0x1000>;