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Author SHA1 Message Date
Phil Edworthy
63804400f2 clk: renesas: rzg2l: Make use of CLK_MON registers optional 
The RZ/V2M SoC doesn't use CLK_MON registers, so make them optional.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-9-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:12:33 +02:00
Phil Edworthy
75b0ad42cc clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers 
All of the muxes and dividers that can be modified require the HIWORD
flags, so make the macros set them. It won't affect read only muxes and
dividers.
This will make the clock tables a little easier to read, particularly for
new SoCs coming.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-8-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:12:32 +02:00
Phil Edworthy
8282fe0029 clk: renesas: rzg2l: Add read only versions of the clk macros 
This just makes the clk tables easier to read.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-7-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:12:32 +02:00
Phil Edworthy
ceb3bfab2d clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro 
We only ever use ARRAY_SIZE() to populate the number of parents, so
move this into the macro to always detect it automatically. This
also makes the tables of clocks a little simpler.
Similarly for the DEF_SD_MUX macro.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-6-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:12:32 +02:00
Phil Edworthy
4a526957e6 dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC 
Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20220503115557.53370-4-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:53 +02:00
Geert Uytterhoeven
049bddcb89 Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19 
Renesas RZ/V2M DT Binding Definitions

Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by
driver and DT source files.
 2022-05-05 12:10:49 +02:00
Geert Uytterhoeven
53c58c08b4 clk: renesas: r9a07g044: Fix OSTM1 module clock name 
Fix a typo in the name of the "ostm1_pclk" clock.
This change has no run-time impact.

Fixes: 161450134a ("clk: renesas: r9a07g044: Add OSTM clock and reset entries")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
 2022-05-05 12:10:21 +02:00
Biju Das
84c9829d16 clk: renesas: r9a07g043: Add clock and reset entries for ADC 
Add clock and reset entries for ADC block in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
b676853004 clk: renesas: r9a07g043: Add TSU clock and reset entry 
Add TSU clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
14d8857d82 clk: renesas: r9a07g043: Add RSPI clock and reset entries 
Add RSPI{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
4e683604cf clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller 
Add clock and reset entries for SPI Multi I/O Bus Controller.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
67f80edf83 clk: renesas: r9a07g044: Add DSI clock and reset entries 
Add DSI clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
6f6178f1e1 clk: renesas: r9a07g044: Add LCDC clock and reset entries 
Add LCDC clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-9-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
31d5ef2f56 clk: renesas: r9a07g044: Add M4 Clock support 
Add support for M4 clock which is sourced from pll2_533_div2.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
359f10c1b0 clk: renesas: r9a07g044: Add M3 Clock support 
Add support for M3 clock which is sourced from DSI divider connected
to PLL5_4 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
300d95c5bb clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support 
Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
60191843db clk: renesas: r9a07g044: Add M1 clock support 
Add support for M1 clock which is sourced from FOUTPOSTDIV.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
46bb3e15e8 clk: renesas: rzg2l: Add DSI divider clk support 
M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)

This patch add support for DSI divider clk by combining
DSIDIVA and DSIDIVB.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
6cc859cae9 clk: renesas: rzg2l: Add PLL5_4 clk mux support 
Add PLL5_4 clk mux support to select clock from clock
sources FOUTPOSTDIV and FOUT1PH0.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:21 +02:00
Biju Das
1561380ee7 clk: renesas: rzg2l: Add FOUTPOSTDIV clk support 
PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
from DSI divider which is connected to PLL5_4 MUX.

This patch adds support for generating FOUTPOSTDIV clk.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:10:20 +02:00
Phil Edworthy
96055bf71a dt-bindings: clock: Add r9a09g011 CPG Clock Definitions 
Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs
(CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's
Manual (Rev. 1.10, Sep. 2021).

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-05-05 12:04:58 +02:00
Yoshihiro Shimoda
0ab55cf183 clk: renesas: cpg-mssr: Add support for R-Car V4H 
Initial CPG support for R-Car V4H (r8a779g0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-29 12:23:39 +02:00
Geert Uytterhoeven
d1fcd661ba Merge tag 'renesas-r8a779g0-dt-binding-defs-tag' into renesas-clk-for-v5.19 
Renesas R-Car V4H DT Binding Definitions

Clock and Power Domain definitions for the Renesas R-Car V4H (R8A779G0)
SoC, shared by driver and DT source files.
 2022-04-29 12:23:34 +02:00
Yoshihiro Shimoda
7f906eaa95 clk: renesas: rcar-gen4: Add CLK_TYPE_GEN4_PLL4 
R-Car V4H (r8a779g0) has PLL4 so that add CLK_TYPE_GEN4_PLL4.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220425064201.459633-5-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-29 12:08:36 +02:00
Biju Das
5d33481f54 clk: renesas: r9a07g043: Add WDT clock and reset entries 
Add WDT{0,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-28 16:37:45 +02:00
Biju Das
6c05648b57 clk: renesas: r9a07g043: Add OSTM clock and reset entries 
Add OSTM{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-28 16:37:45 +02:00
Biju Das
1cbda37757 clk: renesas: r9a07g043: Add clock and reset entries for CANFD 
Add clock and reset entries for CANFD in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-28 16:37:44 +02:00
Biju Das
666b5a010e clk: renesas: r9a07g043: Add USB clocks/resets 
Add clock/reset entries for USB PHY control, USB2.0 host and device.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-28 16:37:44 +02:00
Biju Das
be5b5fcbc7 clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries 
Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-28 16:37:44 +02:00
Biju Das
a9391e0190 clk: renesas: r9a07g043: Add I2C clocks/resets 
Add I2C{0,1,2,3} clock and reset entries.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220425095244.156720-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-28 16:37:44 +02:00
Miquel Raynal
2a6da4a11f clk: renesas: r9a06g032: Fix the RTC hclock description 
It needs to be un-gated, but also a reset must be released and an idle
flag should also be disabled.

The driver already supports all these operations, so update the
description of the RTC hclock to fit these requirements.

Fixes: 4c3d88526e ("clk: renesas: Renesas R9A06G032 clock driver")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20220421090016.79517-3-miquel.raynal@bootlin.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-28 16:33:16 +02:00
Yoshihiro Shimoda
13b4d179c6 dt-bindings: clock: renesas,cpg-mssr: Document r8a779g0 
Add binding documentation for the R-Car V4H (R8A779G0) Clock Pulse
Generator.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220420084255.375700-7-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-25 10:45:15 +02:00
Yoshihiro Shimoda
b243a358b3 clk: renesas: r8a779f0: Add UFS clock 
Add the module clock used by the UFS host controller on the Renesas
R-Car S4-8 (R8A779F0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220411124932.3765571-1-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-25 10:43:41 +02:00
Yoshihiro Shimoda
f2afa78d5a dt-bindings: clock: Add r8a779g0 CPG Core Clock Definitions 
Add all Clock Pulse Generator Core Clock Outputs for the Renesas
R-Car V4H (R8A779G0) SoC.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/20220425064201.459633-3-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-25 10:34:19 +02:00
Yoshihiro Shimoda
90715507cb dt-bindings: power: Add r8a779g0 SYSC power domain definitions 
Add power domain indices for R-Car V4H (r8a779g0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220425064201.459633-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-25 10:34:19 +02:00
Biju Das
59086e4193 clk: renesas: r9a07g043: Add SDHI clock and reset entries 
Add SDHI{0,1} mux, clock and reset entries to CPG driver

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-13 12:30:19 +02:00
Biju Das
e11f804afc clk: renesas: r9a07g043: Add GbEthernet clock/reset 
Add ETH{0,1} clock/reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-13 12:30:19 +02:00
Biju Das
f201eb8445 clk: renesas: r9a07g043: Add ethernet clock sources 
Ethernet reference clock can be sourced from PLL5_500 or PLL6. Add
support for ethernet source clock selection using SEL_PLL_6_2 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-13 12:30:18 +02:00
Biju Das
6c185664b3 clk: renesas: r9a07g043: Add GPIO clock and reset entries 
Add GPIO clock and reset entries in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-13 12:30:18 +02:00
Biju Das
c8b088224c clk: renesas: Add support for RZ/G2UL SoC 
The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present on RZ/G2UL.

This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-13 12:29:08 +02:00
Geert Uytterhoeven
948f592433 Merge tag 'renesas-r9a07g043-dt-binding-defs-tag' into renesas-clk-for-v5.19 
Renesas RZ/G2UL DT Binding Definitions

Clock and reset definitions for the Renesas RZ/G2UL (R9A07G043) SoC,
shared by driver and DT source files.
 2022-04-13 12:28:47 +02:00
Geert Uytterhoeven
880c3fa319 clk: renesas: Move RPC core clocks 
The RPC and RPCD2 core clocks were added to the sections for internal
core clocks, while they are core clock outputs, visible from DT.

Move them to the correct sections.
Rename the ".rpc" clock on R-Car S4 to "rpc".
Fixup nearby whitespace to increase uniformity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/a938b938f00939b9206d7fbaba78e2ef09915f5f.1649681891.git.geert+renesas@glider.be
 2022-04-13 12:27:45 +02:00
Geert Uytterhoeven
29db30c45f clk: renesas: rzg2l: Simplify multiplication/shift logic 
"a * (1 << b)" == "a << b".

No change in generated code.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/71e1cf2e30fb2d7966fc8ec6bab23eb7e24aa1c4.1645460687.git.geert+renesas@glider.be
 2022-04-13 12:27:45 +02:00
Biju Das
eb27897854 dt-bindings: clock: Add R9A07G043 CPG Clock and Reset Definitions 
Define RZ/G2UL (R9A07G043U) Clock Pulse Generator Core Clock and module
clock outputs, as listed in Table 7.1.4.2 ("Clock List r0.51") and also
add Reset definitions referring to registers CPG_RST_* in Section 7.2.3
("Register configuration") of the RZ/G2UL Hardware User's Manual (Rev.
0.51, Nov. 2021).

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220402073037.23947-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-13 12:21:04 +02:00
Geert Uytterhoeven
9d18f81b35 clk: renesas: r8a77995: Add RPC clocks 
Describe the various clocks used by the SPI Multi I/O Bus Controller
(RPC-IF) on the R-Car D3 SoC: RPCSRC internal clock, RPC{,D2} clocks
derived from it, and RPC-IF module clock.

The RPCSRC clock divider on R-Car D3 is very similar to the one on R-Car
E3, but uses a different pre-divider for the PLL0 parent.  Add a new
macro to describe it, reusing the existing clock type for R-Car E3.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/3fd1e886b7737cd0e199603bae81d01be9dcf3aa.1648546700.git.geert+renesas@glider.be
 2022-04-11 12:13:13 +02:00
Geert Uytterhoeven
2a214607e4 clk: renesas: r8a77990: Add RPC clocks 
Describe the various clocks used by the SPI Multi I/O Bus Controller
(RPC-IF) on the R-Car E3 SoC: RPCSRC internal clock, RPC{,D2} clocks
derived from it, and RPC-IF module clock.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/3295013f27f1e4b8fbf3f79b950d65157ea95ef2.1648546700.git.geert+renesas@glider.be
 2022-04-11 12:05:09 +02:00
Biju Das
3733db1f77 dt-bindings: clock: renesas: Document RZ/G2UL SoC 
Document the device tree binding for the Renesas RZ/G2UL Type-1
and Type-2 SoC. RZ/G2UL Type-2 has fewer clocks than RZ/G2UL Type-1
SoC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220315142915.17764-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-04 10:58:46 +02:00
Phil Edworthy
53367bd28f clk: renesas: rzg2l: Remove unused notifiers 
notifiers is not used.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220304143241.8523-1-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-04-04 10:58:46 +02:00
Linus Torvalds
3123109284 Linux 5.18-rc1 v5.18-rc1 2022-04-03 14:08:21 -07:00
Linus Torvalds
09bb8856d4 Merge tag 'trace-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace 
Pull more tracing updates from Steven Rostedt:

 - Rename the staging files to give them some meaning. Just
   stage1,stag2,etc, does not show what they are for

 - Check for NULL from allocation in bootconfig

 - Hold event mutex for dyn_event call in user events

 - Mark user events to broken (to work on the API)

 - Remove eBPF updates from user events

 - Remove user events from uapi header to keep it from being installed.

 - Move ftrace_graph_is_dead() into inline as it is called from hot
   paths and also convert it into a static branch.

* tag 'trace-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace:
  tracing: Move user_events.h temporarily out of include/uapi
  ftrace: Make ftrace_graph_is_dead() a static branch
  tracing: Set user_events to BROKEN
  tracing/user_events: Remove eBPF interfaces
  tracing/user_events: Hold event_mutex during dyn_event_add
  proc: bootconfig: Add null pointer check
  tracing: Rename the staging files for trace_events
 2022-04-03 12:26:01 -07:00