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Bryan O'Donoghue
7cfa2e758b arm64: dts: qcom: sc8280xp: camss: Add CCI definitions 
sc8280xp has four Camera Control Interface (CCI) blocks which pinout to
two I2C master controllers for each CCI.

The CCI I2C pins are not muxed so we define them in the dtsi.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20240111-linux-next-24-01-02-sc8280xp-camss-core-dtsi-v4-3-cdd5c57ff1dc@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-30 15:32:10 -06:00
Bjorn Andersson
59c84ee83f arm64: dts: qcom: sa8295p-adp: Enable GPU 
With the necessary support in place for supplying VDD_GFX from the
MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU
and the GPU on the SA8295P ADP.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-7-7011c2a63037@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-30 14:47:21 -06:00
Bjorn Andersson
904c711ef4 arm64: dts: qcom: sa8295p-adp: add max20411 
The SA8295P ADP has a MAX20411 LDO regulator on I2C 12, supplying the
VDD_GFX pads. Enable the bus and add the maxim,max20411 device on the
bus.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-6-7011c2a63037@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-30 14:46:41 -06:00
Bjorn Andersson
fd5821a1a8 arm64: dts: qcom: sa8540p: Drop gfx.lvl as power-domain for gpucc 
The SA8295P and SA8540P uses an external regulator (max20411), and
gfx.lvl is not provided by rpmh. Drop the power-domains property of the
gpucc node to reflect this.

Fixes: eec51ab2fd ("arm64: dts: qcom: sc8280xp: Add GPU related nodes")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-5-7011c2a63037@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-30 14:46:28 -06:00
Luca Weiss
410dd97e3f arm64: dts: qcom: sm7225-fairphone-fp4: Switch firmware ext to .mbn 
Specify the file name for the squashed/non-split firmware with the .mbn
extension instead of the split .mdt. The kernel can load both but the
squashed version is preferred in dts nowadays.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240110-fp4-mbn-v1-1-45e7e33b1834@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-28 12:04:00 -06:00
Dmitry Baryshkov
39e62f41c3 arm64: dts: qcom: rename PM2250 to PM4125 
It seems, the only actual mentions of PM2250 can be found are related to
the Qualcomm RB1 platform. However even RB1 schematics use PM4125 as a
PMIC name. Rename PM2250 to PM4125 to follow the documentation.

Note, this doesn't change the compatible strings. There was a previous
argument regarding renaming of compat strings.

Fixes: c309b9a540 ("arm64: dts: qcom: Add initial PM2250 device tree")
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240128-pm2250-pm4125-rename-v2-2-d51987e9f83a@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-28 12:04:00 -06:00
Luca Weiss
d51b2d5c4a arm64: dts: qcom: qcm6490-fairphone-fp5: Add PMIC GLINK 
Via the PMIC GLINK driver we can get info about fuel gauge, charger and
USB connector events. Add the node to the dts and configure USB so that
role switching works.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Link: https://lore.kernel.org/r/20231220-fp5-pmic-glink-v1-3-2a1f8e3c661c@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-28 12:04:00 -06:00
David Heidelberg
afe9867a0c arm64: dts: qcom: sdm845-oneplus-common: improve DAI node naming 
Make it easier to understand what the reg in those nodes is by using the
constants provided by qcom,q6dsp-lpass-ports.h.

Name nodes according to dt-binding expectations.

Fix for
```
arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dtb: service@4: dais: Unevaluated properties are not allowed ('qi2s@22', 'qi2s@23' were unexpected)
```

Fixes: b7b7342868 ("arm64: dts: qcom: sdm845-oneplus-*: add audio devices")
Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20231229200245.259689-1-david@ixit.cz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-28 12:04:00 -06:00
Luca Weiss
5dbbe7e0a2 arm64: dts: qcom: qcm6490-fairphone-fp5: Add missing reserved-memory 
It seems we also need to reserve a region of 81 MiB called "removed_mem"
otherwise we can easily hit the following error with higher RAM usage:

  [ 1467.809274] Internal error: synchronous external abort: 0000000096000010 [#2] SMP

Fixes: eee9602ad6 ("arm64: dts: qcom: qcm6490: Add device-tree for Fairphone 5")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231229-fp5-reserved-mem-v1-1-87bb818f1397@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-28 12:04:00 -06:00
Luca Weiss
40ec6a2817 arm64: dts: qcom: sc7280: Add static properties to cryptobam 
When the properties num-channels & qcom,num-ees are not specified, the
driver tries to read the values from registers, but this read fails and
resets the device if the interconnect from the qcom,qce node is not
already active when that happens.

Add the static properties to not touch any registers during probe, the
rest of the time when the BAM is used by QCE then the interconnect will
be active already.

Fixes: d488f903a8 ("arm64: dts: qcom: sc7280: add QCrypto nodes")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20231229-sc7280-cryptobam-fixup-v1-1-bd8f68589b80@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-28 12:04:00 -06:00
Suraj Jaiswal
e51b74f2da arm64: dts: qcom: sa8775p: enable safety IRQ 
Add changes to support safety IRQ handling
support for ethernet.

Signed-off-by: Suraj Jaiswal <quic_jsuraj@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240110111649.2256450-3-quic_jsuraj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-28 12:04:00 -06:00
Stephan Gerhold
0f893a2cb1 arm64: dts: qcom: apq8016-sbc-d3-camera: Use more generic node names 
Add "regulator" to the node names of the fixed regulators, and drop the
"_rear" part of the camera node name since it is not part of the class
of the device (which is simply "camera").

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230922-apq8016-sbc-camera-dtso-v1-1-ce9451895ca1@gerhold.net
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:42:59 -06:00
Krzysztof Kozlowski
7f65047231 arm64: dts: qcom: split PCIe interrupt-names entries per lines 
Other PCIe nodes in SM8250 and SM8350 have one interrupt name per
line, so adjust PCIe0 to match the style.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-7-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:37:26 -06:00
Krzysztof Kozlowski
7ee7c0f326 arm64: dts: qcom: sm8650: describe all PCI MSI interrupts 
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  Not
tested on hardware.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-6-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:37:26 -06:00
Krzysztof Kozlowski
79d99c74c6 arm64: dts: qcom: sm8550: describe all PCI MSI interrupts 
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  Only
boot tested on hardware.

Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-5-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:37:26 -06:00
Krzysztof Kozlowski
aa87ad5575 arm64: dts: qcom: sm8450: describe all PCI MSI interrupts 
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  Only
boot tested on hardware.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-4-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:37:26 -06:00
Krzysztof Kozlowski
f9a7f70093 arm64: dts: qcom: sm8350: describe all PCI MSI interrupts 
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  Not
tested on hardware.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-3-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:37:26 -06:00
Krzysztof Kozlowski
534ecb509d arm64: dts: qcom: sm8250: describe all PCI MSI interrupts 
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  Not
tested on hardware.

PCIe0 was done already in commit f2819650aa ("arm64: dts: qcom:
sm8250: provide additional MSI interrupts").

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-2-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:37:26 -06:00
Krzysztof Kozlowski
b6b75a4c03 arm64: dts: qcom: sm8150: describe all PCI MSI interrupts 
Each group of MSI interrupts is mapped to the separate host interrupt.
Describe each of interrupts in the device tree for PCIe hosts.  Not
tested on hardware.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240126-b4-dt-bindings-pci-qcom-split-dts-v2-1-0bb067f73adb@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 20:37:26 -06:00
Konrad Dybcio
6e115b75b4 arm64: dts: qcom: sm8450: Add missing interconnects to serial 
The serial ports did not have their interconnect paths specified when
they were first introduced. Fix that.

Fixes: 5188049c9b ("arm64: dts: qcom: Add base SM8450 DTSI")
Fixes: f583741847 ("arm64: dts: qcom: sm8450: add uart20 node")
Reported-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Suggested-by: Georgi Djakov <djakov@kernel.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240116-topic-8450serial-v1-1-b685e6a5ad78@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 18:47:46 -06:00
Raymond Hackley
80daa2fa2f dt-bindings: qcom: Document new msm8916-samsung devices 
Document the new following device tree bindings used in their
device trees:

- samsung,fortuna3g
- samsung,gprimeltecan
- samsung,grandprimelte
- samsung,rossa

Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240120095715.13689-2-raymondhackley@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:15:15 -06:00
Krzysztof Kozlowski
915253bdd6 arm64: dts: qcom: sm8450-hdk: correct AMIC4 and AMIC5 microphones 
Due to lack of documentation the AMIC4 and AMIC5 analogue microphones
were never actually working, so the audio routing for them was added
hoping it is correct.  It turned out not correct - their routing should
point to SWR_INPUT0 (so audio mixer TX SMIC MUX0 = SWR_MIC0) and
SWR_INPUT1 (so audio mixer TX SMIC MUX0 = SWR_MIC1), respectively.  With
proper mixer settings and fixed LPASS TX macr codec TX SMIC MUXn
widgets, this makes all microphones working on HDK8450.

Cc: stable@vger.kernel.org
Fixes: f20cf2bc3f ("arm64: dts: qcom: sm8450-hdk: add other analogue microphones")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240124121855.162730-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:11:36 -06:00
Krzysztof Kozlowski
6de995bc46 arm64: dts: qcom: sm8150: add necessary ref clock to PCIe 
The PCIe nodes should get the ref clock, according to information from
Qualcomm.

Link: https://lore.kernel.org/all/20231121065440.GB3315@thinkpad/
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231208105155.36097-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
ac68c7d391 arm64: dts: qcom: sdm630: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-12-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
6a46408928 arm64: dts: qcom: sm8550: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, unify the naming scheme of the
thermal zones across the tree while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-11-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
36fd56ab4d arm64: dts: qcom: sm8450: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-10-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
43c925e456 arm64: dts: qcom: sm8350: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-9-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
fb18c89381 arm64: dts: qcom: sm8250: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-8-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
f18c63a821 arm64: dts: qcom: sm8150: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones. Also, update the trip point label
to be more telling, while at it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-7-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
834932689f arm64: dts: qcom: sm6115: Mark GPU @ 125C critical 
If the GPU ever reaches this temperature, the "critical" signal shuold
definitely be propagated. Fix the wrong type.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-6-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
de5e4e88ac arm64: dts: qcom: sm6115: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-5-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
08b1b831e1 arm64: dts: qcom: sdm845: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-4-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
f48cea4a6f arm64: dts: qcom: sc8180x: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-3-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:38 -06:00
Konrad Dybcio
93c4e1fb9d arm64: dts: qcom: msm8939: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-2-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:37 -06:00
Konrad Dybcio
04ee83047e arm64: dts: qcom: msm8916: Hook up GPU cooling device 
In order to allow for throttling the GPU, hook up the cooling device
to the respective thermal zones.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-gpu_cooling-v1-1-fda30c57e353@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:37 -06:00
Konrad Dybcio
7d62dbd1b3 arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes 
The RPMh driver will cache sleep and wake votes until the cluster
power-domain is about to enter idle, to avoid unnecessary writes. So
associate the apps_rsc with the cluster pd, so that it can be notified
about this event.

Without this, only AMC votes are being committed.

Fixes: af16b00578 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-x1e_fixes-v1-4-70723e08d5f6@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:37 -06:00
Konrad Dybcio
f33767e3cf arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain 
Previous Qualcomm SoCs over the past couple years have used the Arm DSU
architecture, which basically unified the meaning of the "cluster" and
"system". This is however clearly not the case on X1E, as can be seen
by three separate cluster power domains.

Add the lacking system-level power domain. For now it's going to be
always-on, as no system-wide idle states are defined at the moment.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240102-topic-x1e_fixes-v1-3-70723e08d5f6@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 17:06:37 -06:00
Krishna Kurapati
927173bf8a arm64: dts: qcom: Add missing interrupts for qcs404/ipq5332 
For qcs404 and ipq5332, certain interrupts are missing in DT.
Add them to ensure they are in accordance to bindings.

The interrupts added enable remote wakeup functionality for these SoCs.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-5-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 16:42:02 -06:00
Krishna Kurapati
7c9afa1fd8 arm64: dts: qcom: Fix hs_phy_irq for SDM670/SDM845/SM6350 
For sm6350/sdm670/sdm845, although they are qusb2 phy targets, dp/dm
interrupts are used for wakeup instead of qusb2_phy irq. These targets
were part of a generation that were the last ones to implement QUSB2 PHY
and the design incorporated dedicated DP/DM interrupts which eventually
carried forward to the newer femto based targets.

Add the missing pwr_event irq for these targets. Also modify order of
interrupts in accordance to bindings update. Modifying the order of these
interrupts is harmless as the driver tries to get these interrupts from DT
by name and not by index.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-4-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 16:42:02 -06:00
Krishna Kurapati
6bf150aef2 arm64: dts: qcom: Fix hs_phy_irq for non-QUSB2 targets 
On non-QUSB2 targets (like the ones that use femto phys, M31 phy, eusb2
phy), many of the QCOM DTs are missing the IRQ for either hs_phy_irq or
pwr_event. In one case, the hs_phy_irq was incorrectly defined with the
latter's IRQ number. Since the DT must describe the hw whether or not
the driver uses these interrupts, fix and add the missing entries in order
to describe the HW completely and accurately.

Also modify order of interrupts in accordance to bindings update.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-3-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 16:42:02 -06:00
Krishna Kurapati
2c6597c72e arm64: dts: qcom: Fix hs_phy_irq for QUSB2 targets 
On several QUSB2 Targets, the hs_phy_irq mentioned is actually
qusb2_phy interrupt specific to QUSB2 PHY's. Rename hs_phy_irq
to qusb2_phy for such targets.

In actuality, the hs_phy_irq is also present in these targets, but
kept in for debug purposes in hw test environments. This is not
triggered by default and its functionality is mutually exclusive
to that of qusb2_phy interrupt.

Add missing hs_phy_irq's, pwr_event irq's for QUSB2 PHY targets.
Add missing ss_phy_irq on some targets which allows for remote
wakeup to work on a Super Speed link.

Also modify order of interrupts in accordance to bindings update.
Since driver looks up for interrupts by name and not by index, it
is safe to modify order of these interrupts in the DT.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Link: https://lore.kernel.org/r/20240125185921.5062-2-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 16:42:02 -06:00
Neil Armstrong
b5e25ded27 arm64: dts: qcom: sm8550: add support for the SM8550-HDK board 
The SM8550-HDK is an embedded development platforms for the
Snapdragon 8 Gen 2 SoC aka SM8550, with the following features:
- Qualcomm SM8550 SoC
- 16GiB On-board LPDDR5
- On-board WiFi 7 + Bluetooth 5.3/BLE
- On-board UFS4.0
- M.2 Key B+M Gen3x2 PCIe Slot
- HDMI Output
- USB-C Connector with DP Almode & Audio Accessory mode
- Micro-SDCard Slot
- Audio Jack with Playback and Microphone
- 2 On-board Analog microphones
- 2 On-board Speakers
- 96Boards Compatible Low-Speed and High-Speed connectors [1]
  - For Camera, Sensors and external Display cards
  - Compatible with the Linaro Debug board [2]
- SIM Slot for Modem
- Debug connectors
- 6x On-Board LEDs

Product Page: [3]

[1] https://www.96boards.org/specifications/
[2] https://git.codelinaro.org/linaro/qcomlt/debugboard
[3] https://www.lantronix.com/products/snapdragon-8-gen-2-mobile-hardware-development-kit/

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240125-topic-sm8550-upstream-hdk8550-v3-2-73bb5ef11cf8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 16:38:12 -06:00
Neil Armstrong
507cad6e0f dt-bindings: arm: qcom: Document the HDK8550 board 
Document the Qualcomm SM8550 based HDK (Hardware Development Kit)
embedded development platform designed by Qualcomm and sold by Lantronix.

[1] https://www.lantronix.com/products/snapdragon-8-gen-2-mobile-hardware-development-kit/

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240125-topic-sm8550-upstream-hdk8550-v3-1-73bb5ef11cf8@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-27 16:38:12 -06:00
Konrad Dybcio
3168e86af8 arm64: dts: qcom: sc8180x: Add RPMh sleep stats 
Add the sleep stats node to enable peeking at the power collapse reports
coming from the AOSS.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-10-93b5c107ed43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-22 18:12:43 -06:00
Konrad Dybcio
dcad0590d1 arm64: dts: qcom: sc8180x: Shrink aoss_qmp register space size 
The AOSS_QMP region is overallocated, bleeding into space that's supposed
to be used by other peripherals. Fix it.

Fixes: 8575f197b0 ("arm64: dts: qcom: Introduce the SC8180x platform")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-9-93b5c107ed43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-22 18:12:43 -06:00
Konrad Dybcio
f0cd5a0ebd arm64: dts: qcom: sc8180x: Add missing CPU<->MDP_CFG path 
To guarantee the required resources are enabled, describe the
interconnect path between the MDSS and the CPU.

Fixes: 494dec9b6f ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-8-93b5c107ed43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-22 18:12:42 -06:00
Konrad Dybcio
6d9fb9e4c4 arm64: dts: qcom: sc8180x: Require LOW_SVS vote for MMCX if DISPCC is on 
To ensure the PLLs are getting enough power, cast a vote with DISPCC so
that MMCX is at least at LOW_SVS.

Fixes: 494dec9b6f ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-7-93b5c107ed43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-22 18:12:42 -06:00
Konrad Dybcio
309b5774f4 arm64: dts: qcom: sc8180x: Don't hold MDP core clock at FMAX 
There's an OPP table to handle this, drop the permanent vote.

Fixes: 494dec9b6f ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-6-93b5c107ed43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-22 18:12:42 -06:00
Konrad Dybcio
24e98cb3d5 arm64: dts: qcom: sc8180x: Fix eDP PHY power-domains 
The (e)DP PHYs are powered by the MX line, not through the MDSS GDSC.
Fix that up.

Fixes: 494dec9b6f ("arm64: dts: qcom: sc8180x: Add display and gpu nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-5-93b5c107ed43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-22 18:12:42 -06:00
Konrad Dybcio
07b600dfdf arm64: dts: qcom: sc8180x: Add missing CPU off state 
The CPUs can be powered off without pulling the plug from the rest of
the system. Describe the idle state responsible for this.

Fixes: 8575f197b0 ("arm64: dts: qcom: Introduce the SC8180x platform")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231230-topic-8180_more_fixes-v1-4-93b5c107ed43@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-01-22 18:12:42 -06:00