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Matthias Kaehlcke
eb59cd3e39 arm64: dts: qcom: pm6150: Add thermal zone for PMIC on-die temperature 
Add a thermal zone for the pm6150 on-die temperature. The system should
try to shut down orderly when the temperature reaches the critical trip
point at 115°C, otherwise the PMIC will perform a HW power off at 145°C.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210603081215.v2.1.Id4510e9e4baaa3f6c9fdd5cdf4d8606e63c262e3@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-06-05 22:36:15 -05:00
Judy Hsiao
ad7395c748 arm64: dts: qcom: sc7180: add label for secondary mi2s 
Adds label for MI2S secondary block to allow follower projects to override
for the four speaker support which uses I2S SD1 line on gpio52 pin.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Judy Hsiao <judyhsiao@chromium.org>
Link: https://lore.kernel.org/r/20210601022117.4071117-1-judyhsiao@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-06-01 11:01:34 -05:00
Rajendra Nayak
9d6e639cba arm64: dts: qcom: sc7280: Add "google,senor" to the compatible 
The sc7280 IDP board is also called senor in the Chrome OS builds.
Add the "google,senor" compatible so coreboot/depthcharge knows what
device tree blob to pick

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1619674827-26650-2-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 17:22:14 -05:00
Rajendra Nayak
17bf8dfa2a dt-bindings: arm: qcom: Document google,senor board 
Document the google,senor board based on sc7280 SoC

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Link: https://lore.kernel.org/r/1619674827-26650-1-git-send-email-rnayak@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 17:22:04 -05:00
Sibi Sankar
c3bbe55c94 arm64: dts: qcom: sc7280: Add nodes to boot WPSS 
Add miscellaneous nodes to boot the Wireless Processor Subsystem (WPSS) on
SC7280 SoCs.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1619508824-14413-6-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 17:10:51 -05:00
Sibi Sankar
a1dff44b35 dt-bindings: mailbox: Add WPSS client index to IPCC 
Add WPSS remote processor client index to Inter-Processor Communication
Controller (IPCC) block.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1619508824-14413-2-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 17:10:51 -05:00
Sujit Kautkar
d4282fb4f8 arm64: dts: qcom: sc7180: Move rmtfs memory region 
Move rmtfs memory region so that it does not overlap with system
RAM (kernel data) when KAsan is enabled. This puts rmtfs right
after mba_mem which is not supposed to increase beyond 0x94600000

Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Sujit Kautkar <sujitka@chromium.org>
Link: https://lore.kernel.org/r/20210514113430.1.Ic2d032cd80424af229bb95e2c67dd4de1a70cb0c@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 13:32:36 -05:00
Taniya Das
422a295221 arm64: dts: qcom: sc7280: Add clock controller nodes 
Add support for the video, gpu, display, lpass clock controller
device nodes for SC7280 SoC.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1618020280-5470-3-git-send-email-tdas@codeaurora.org
[bjorn: Dropped includes, as they are not present in v5.13-rc1]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 13:19:30 -05:00
Taniya Das
7dbd121a2c arm64: dts: qcom: sc7280: Add cpufreq hw node 
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lore.kernel.org/r/1618020280-5470-2-git-send-email-tdas@codeaurora.org
[bjorn: Dropped reg-names]
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 13:11:41 -05:00
Matthias Kaehlcke
822c8f2a2f arm64: dts: qcom: sc7180: coachz: Add thermal config for skin temperature 
Add ADC and thermal monitor configuration for skin temperature,
plus a thermal zone that monitors the skin temperature and uses
the big cores as cooling devices.

CoachZ rev1 is stuffed with an incompatible thermistor for the
skin temperature, disable the thermal zone for rev1 to avoid
the use of bogus temperature values.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210414111007.v1.1.I1a438604a79025307f177347d45815987b105cb5@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 13:05:59 -05:00
Douglas Anderson
c1124180eb arm64: dts: qcom: sc7180: Fix sc7180-qmp-usb3-dp-phy reg sizes 
As per Dmitry Baryshkov [1]:
a) The 2nd "reg" should be 0x3c because "Offset 0x38 is
   USB3_DP_COM_REVISION_ID3 (not used by the current driver though)."
b) The 3rd "reg" "is a serdes region and qmp_v3_dp_serdes_tbl contains
   registers 0x148 and 0x154."

I think because the 3rd "reg" is a serdes region we should just use
the same size as the 1st "reg"?

[1] https://lore.kernel.org/r/ee5695bb-a603-0dd5-7a7f-695e919b1af1@linaro.org

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Cc: Stephen Boyd <swboyd@chromium.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Rob Clark <robdclark@chromium.org>
Fixes: 58fd7ae621 ("arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phy")
Reported-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210315103836.1.I9a97120319d43b42353aeac4d348624d60687df7@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 13:05:39 -05:00
Jonathan Marek
dc5d91250a arm64: dts: qcom: sm8250: fix display nodes 
Use sm8250 compatibles instead of sdm845 compatibles

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210329120051.3401567-5-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 13:03:15 -05:00
Stephen Boyd
c0dcfe6a78 arm64: dts: qcom: c630: Add no-hpd to DSI bridge node 
We should indicate that we're not using the HPD pin on this device, per
the binding document. Otherwise if code in the future wants to enable
HPD in the bridge when this property is absent we'll be enabling HPD
when it isn't supposed to be used. Presumably this board isn't using hpd
on the bridge.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Steev Klimaszewski <steev@kali.org>
Fixes: 956e9c85f4 ("arm64: dts: qcom: c630: Define eDP bridge and panel")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210324231424.2890039-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 13:02:16 -05:00
Serge Semin
eb9b7bfd59 arm64: dts: qcom: Harmonize DWC USB3 DT nodes name 
In accordance with the DWC USB3 bindings the corresponding node
name is suppose to comply with the Generic USB HCD DT schema, which
requires the USB nodes to have the name acceptable by the regexp:
"^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly
named.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210324204836.29668-8-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 13:01:35 -05:00
Stephen Boyd
5f551b5ce5 arm64: dts: qcom: trogdor: Add no-hpd to DSI bridge node 
We should indicate that we're not using the HPD pin on this device, per
the binding document. Otherwise if code in the future wants to enable
HPD in the bridge when this property is absent we'll be wasting power
powering hpd when we don't use it on trogdor boards. We didn't notice
this before because the kernel driver blindly disables hpd, but that
won't be true for much longer.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Cc: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Cc: Douglas Anderson <dianders@chromium.org>
Fixes: 7ec3e67307 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210324025534.1837405-1-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:59:59 -05:00
Petr Vorel
f890f89d9a arm64: dts: qcom: msm8994-angler: Fix gpio-reserved-ranges 85-88 
Reserve GPIO pins 85-88 as these aren't meant to be accessible from the
application CPUs (causes reboot). Yet another fix similar to
9134586715, 5f8d3ab136, which is needed to allow angler to boot after
3edfb7bd76 ("gpiolib: Show correct direction from the beginning").

Fixes: feeaf56ac7 ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support")

Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210415193913.1836153-1-petr.vorel@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Konrad Dybcio
0a275a35ce arm64: dts: qcom: msm8996: Make CPUCC actually probe (and work) 
Fix the compatible to make the driver probe and tell the
driver where to look for the "xo" clock to make sure everything
works.

Then we get a happy (eh, happier) 8996:

somainline-sdcard:/home/konrad# cat /sys/kernel/debug/clk/pwrcl_pll/clk_rate
1152000000

Don't backport without "arm64: dts: qcom: msm8996: Add CPU opps", as
the system fails to boot without consumers for these clocks.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210527192958.775434-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Loic Poulain
90173a954a arm64: dts: qcom: msm8996: Add CPU opps 
Add the operating points capabilities of the kryo CPUs, that can be
used for frequency scaling. There are two differents operating point
tables, one for the big cluster and one for the LITTLE cluster.

This frequency scaling support can then be used as a passive cooling
device (cpufreq cooling device).

Only add nominal fmax for now, since there is no dynamic control of
VDD APC (s11..) which is statically set at its nominal value.

Original patch link: https://patchwork.kernel.org/project/linux-arm-msm/patch/1595253740-29466-6-git-send-email-loic.poulain@linaro.org/

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
[konrad: drop the thermals part, rebase and remove spaces within <>]
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210527194455.782108-2-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Matthias Kaehlcke
b502efda64 arm64: dts: qcom: sc7180: Add CoachZ rev3 
CoachZ rev3 uses a 100k NTC thermistor for the charger temperatures,
instead of the 47k NTC that is stuffed in earlier revisions. Add .dts
files for rev3.

The 47k NTC currently isn't supported by the PM6150 ADC driver.
Disable the charger thermal zone for rev1 and rev2 to avoid the use
of bogus temperature values.

This also gets rid of the explicit DT files for rev2 and handles
rev2 in the rev1 .dts instead. There was some back and forth
downstream involving the 'dmic_clk_en' pin, after that was sorted
out the DT for rev1 and rev2 is the same.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210322094628.v4.3.I95b8a63103b77cab6a7cf9c150f0541db57fda98@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Matthias Kaehlcke
ad6fc14313 arm64: dts: qcom: sc7180: Add pompom rev3 
The only kernel visible change with respect to rev2 is that pompom
rev3 changed the charger thermistor from a 47k to a 100k NTC to use
a thermistor which is supported by the PM6150 ADC driver.

Disable the charger thermal zone for pompom rev1 and rev2 to avoid
the use of bogus temperature values from the unsupported thermistor.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210322094628.v4.2.I4138c3edee23d1efa637eef51e841d9d2e266659@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Matthias Kaehlcke
39441f73d9 arm64: dts: qcom: sc7180: lazor: Simplify disabling of charger thermal zone 
Commit f73558cc83d1 ("arm64: dts: qcom: sc7180: Disable charger
thermal zone for lazor") disables the charger thermal zone for
specific lazor revisions due to an unsupported thermistor type.
The initial idea was to disable the thermal zone for older
revisions and leave it enabled for newer ones that use a
supported thermistor. Finally the thermistor won't be changed
on newer revisions, hence the thermal zone should be disabled
for all lazor (and limozeen) revisions. Instead of disabling
it per revision do it once in the shared .dtsi for lazor.

Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20210322094628.v4.1.I6d587e7ae72a5a47253bb95dfdc3158f8cc8a157@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Roja Rani Yarubandi
caaf1f38d9 arm64: dts: qcom: sc7180: Remove QUP-CORE ICC path 
We had introduced the QUP-CORE ICC path to put proxy votes from
QUP wrapper on behalf of earlycon, if other users of QUP-CORE turn
off this clock before the real console is probed, unclocked access
to HW was seen from earlycon.

With ICC sync state support proxy votes are no longer need as ICC
will ensure that the default bootloader votes are not removed until
all it's consumer are probed.

We can safely remove ICC path for QUP-CORE clock from QUP wrapper
device.

Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20210324101836.25272-3-rojay@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Vinod Koul
1dee9e3b09 arm64: dts: qcom: sm8350: fix the node unit addresses 
Some node unit addresses were put wrongly in the dts, resulting in
below warning when run with W=1

arch/arm64/boot/dts/qcom/sm8350.dtsi:693.34-702.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c222000: simple-bus unit address format error, expected "c263000"
arch/arm64/boot/dts/qcom/sm8350.dtsi:704.34-713.5: Warning (simple_bus_reg): /soc@0/thermal-sensor@c223000: simple-bus unit address format error, expected "c265000"
arch/arm64/boot/dts/qcom/sm8350.dtsi:1180.32-1185.5: Warning (simple_bus_reg): /soc@0/interconnect@90e0000: simple-bus unit address format error, expected "90c0000"

Fix by correcting to the correct address as given in reg node

Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210513060733.382420-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Vinod Koul
84c856d07d arm64: dts: qcom: sm8350: use interconnect enums 
Add interconnect enums instead of numbers now that interconnect is in
mainline.

Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210513060705.382184-1-vkoul@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Felipe Balbi
0500629017 arm64: dts: qcom: sm8150: Add DMA nodes 
With this patch, DMA has a chance of probing and doing something
useful.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@microsoft.com>
Link: https://lore.kernel.org/r/20210417061951.2105530-3-balbi@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Vincent Knecht
15c5a08c84 arm64: dts: qcom: msm8916-alcatel-idol347: enable touchscreen 
Enable the MStar msg2638 touchscreen.

Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
Link: https://lore.kernel.org/r/20210528114345.543761-1-vincent.knecht@mailoo.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Loic Poulain
af260f1f7d arm64: dts: qcom: msm8996: Rename speedbin node 
The speedbin value blown in the efuse is used to determine is used to
determine the voltage and frequency value for different IPs, including
GPU, CPUs... So it's really not a gpu specific information.

This patch simply renames 'gpu_speed_bin' node to 'speedbin'.

Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210527194455.782108-1-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:10 -05:00
Robert Marko
58b2785dda arm64: dts: qcom: ipq8074: disable USB phy by default 
One of the QUSB USB PHY-s has been left enabled by
default, this is probably just a mistake as other
USB PHY-s are disabled by default.

It makes no sense to have it enabled by default as
not all board implement USB ports, so disable it.

Reviewed-by: Kathiravan T <kathirav@codeaurora.org>
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20210526150125.1816335-1-robimarko@gmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-31 12:12:02 -05:00
Konrad Dybcio
a4bdd15e79 arm64: dts: qcom: msm8996: Add DMA to QUPs and UARTs 
Add BAM DMA nodes and add required properties to devices
to enable DMA operations.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210525200246.118323-5-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:34 -05:00
Konrad Dybcio
fbe7be5b23 arm64: dts: qcom: msm8996: Strictly limit USB2 host to USB2 speeds 
As the name implies, the USB2 controller should only operate at
USB2 speeds. Make sure it does just that by pinning it to USB
High-Speed (USB2) mode.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210525200246.118323-3-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:34 -05:00
satya priya
fbd5a1d226 arm64: dts: qcom: sc7280: Add ADC channel nodes for PMIC temperatures to sc7280-idp 
Add channel nodes for the on die temperatures of PMICS
pmk8350, pm8350, pmr735a and pmr735b.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-11-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:34 -05:00
satya priya
a1cbfdfdc2 arm64: dts: qcom: sc7280: Include PMIC DT files for sc7280-idp 
The sc7280-idp has four PMICs, include their .dtsi files.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1621937466-1502-10-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
satya priya
d0927c2134 arm64: dts: qcom: pmk8350: Correct the GPIO node 
Add gpio ranges and correct the compatible to add
"qcom,spmi-gpio" as this pmic is on spmi bus.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1621937466-1502-9-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
satya priya
b2de431360 arm64: dts: qcom: pmk8350: Add peripherals for pmk8350 
Add PON, RTC, VADC and ACD_TM support for PMK8350.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-8-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
satya priya
f878e1baa4 arm64: dts: qcom: pmr735a: Correct the GPIO node 
Add gpio ranges and correct the compatible to add
"qcom,spmi-gpio" as this pmic is on spmi bus.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1621937466-1502-7-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
satya priya
7a3544e5d4 arm64: dts: qcom: pmr735a: Add temp-alarm support 
Add temp-alarm support for PMR735A pmic.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-6-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
satya priya
6327abef80 arm64: dts: qcom: pm8350c: Correct the GPIO node 
Add gpio ranges and correct the compatible to add
"qcom,spmi-gpio" as this pmic is on spmi bus.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: satya priya <skakit@codeaurora.org>
Link: https://lore.kernel.org/r/1621937466-1502-5-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
satya priya
3795fe7d49 arm64: dts: qcom: pm8350c: Add temp-alarm support 
Add temp-alarm support for PM8350C pmic.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-4-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
satya priya
0e17fe8cf8 arm64: dts: qcom: pm7325: Add pm7325 base dts file 
Add base DTS file for pm7325 along with GPIOs and temp-alarm nodes.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-3-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
satya priya
4dcaa68ee2 arm64: dts: qcom: sm8350: Add label for thermal-zones node 
Add label "thermal_zones" for thermal-zones node.

Signed-off-by: satya priya <skakit@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1621937466-1502-2-git-send-email-skakit@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Rajeshwari Ravindra Kamble
9ec1c5867c arm64: dts: qcom: SC7280: Add thermal zone support 
Adding thermal zone and cooling maps support in SC7280.

Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Rajeshwari Ravindra Kamble <rkambl@codeaurora.org>
Link: https://lore.kernel.org/r/1620367641-23383-4-git-send-email-rkambl@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Rajeshwari Ravindra Kamble
132f5a8df9 arm64: dts: qcom: SC7280: Add device node support for TSENS 
Adding device node for TSENS controller and critical interrupt support in SC7280.

Signed-off-by: Rajeshwari Ravindra Kamble <rkambl@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/1620367641-23383-3-git-send-email-rkambl@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Yassine Oudjana
4753492de9 arm64: dts: qcom: msm8996: Add usb3 interrupts 
Add hs_phy_irq and ss_phy_irq to usb3.

Tested-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Link: https://lore.kernel.org/r/dvfyYKA9vnJdunbQ1CL-dgjXtv_1wYpRnezdc3PHoCyrgmfi5KP0Dn4MtaumQEpHIQAHL9tTdqcaCK7YJWyrdWXCrPeGd4uMh-nFeu7xQYw=@protonmail.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Konrad Dybcio
3343de9af7 arm64: dts: qcom: msm8996: Clean up the SDHCI2 node 
Fix the indentation, add pinctrl and move status="disabled"
down.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-11-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Konrad Dybcio
37aa540cbd arm64: dts: qcom: pmi8994: Add WLED node 
Add and configure WLED node to enable backlight
control on WLED-enabled devices.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-10-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Konrad Dybcio
12d5403757 arm64: dts: qcom: msm8996: Add DSI0 nodes 
Add required nodes to support DSI displays connected to the
primary interface.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-9-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Konrad Dybcio
f7342c7d29 arm64: dts: qcom: pm8994: Add RESIN node 
Add a RESIN node to support RESIN-connected buttons on some
devices.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-8-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Konrad Dybcio
d774e762b0 arm64: dts: qcom: msm8996: Disable Venus by default 
Disable Venus by default to allow booting without closed firmware and
enable it on the boards that didn't previously disable it. This commit
brings no functional difference.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-7-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Konrad Dybcio
37b05cecfe arm64: dts: qcom: msm8996: Disable MDSS and Adreno by default 
Disable them by default to allow for booting without a display
and proprietary firmware. Then, enable them on boards that didn't
previously disable them. Hence, this commit brings no functional
difference.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-6-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:33 -05:00
Konrad Dybcio
c33d9068a7 arm64: dts: qcom: msm8996: Add BLSP2_I2C5 and BLSP2_I2C6 
Add the fifth and sixth I2C host on the second BLSP, used for
various board-specific peripherals.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210228130831.203765-5-konrad.dybcio@somainline.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
 2021-05-25 22:40:32 -05:00