mirror of
https://github.com/zeldaret/mm.git
synced 2026-07-09 21:51:32 -04:00
yeet HW_REG
This commit is contained in:
@@ -12,9 +12,6 @@
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#define KSEG0 0x80000000 // 0x80000000 - 0x9FFFFFFF Physical memory, cached, unmapped
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#define RDRAM_CACHED KSEG0
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// Volatile access wrapper, enforcing uncached memory
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#define HW_REG(reg, type) *(volatile type*)((reg) | KSEG1)
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#define AI_DRAM_ADDR_REG 0x04500000
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#define AI_LEN_REG 0x04500004
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#define AI_CONTROL_REG 0x04500008
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+2
-2
@@ -51,8 +51,8 @@
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u32 __osSpGetStatus(void);
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void __osSpSetStatus(u32 data);
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s32 __osSpSetPc(void* pc);
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s32 __osSpRawStartDma(s32 direction, void* devAddr, void* dramAddr, size_t size);
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s32 __osSpSetPc(u32 pc);
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s32 __osSpRawStartDma(s32 direction, u32 devAddr, void* dramAddr, size_t size);
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#endif
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@@ -18,15 +18,15 @@ s32 osAiSetNextBuffer(void* buf, u32 size) {
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}
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// Originally a call to __osAiDeviceBusy
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status = HW_REG(AI_STATUS_REG, s32);
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status = IO_READ(AI_STATUS_REG);
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if (status & AI_STATUS_AI_FULL) {
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return -1;
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}
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// OS_K0_TO_PHYSICAL replaces osVirtualToPhysical, this replacement
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// assumes that only KSEG0 addresses are given
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HW_REG(AI_DRAM_ADDR_REG, u32) = OS_K0_TO_PHYSICAL(bufAdjusted);
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HW_REG(AI_LEN_REG, u32) = size;
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IO_WRITE(AI_DRAM_ADDR_REG, OS_K0_TO_PHYSICAL(bufAdjusted));
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IO_WRITE(AI_LEN_REG, size);
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return 0;
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}
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@@ -13,7 +13,7 @@ void CIC6105_Nop80081828(void) {
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}
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void CIC6105_PrintRomInfo(void) {
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FaultDrawer_DrawText(80, 200, "SP_STATUS %08x", HW_REG(SP_STATUS_REG, u32));
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FaultDrawer_DrawText(80, 200, "SP_STATUS %08x", IO_READ(SP_STATUS_REG));
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FaultDrawer_DrawText(40, 184, "ROM_F [Creator:%s]", gBuildTeam);
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FaultDrawer_DrawText(56, 192, "[Date:%s]", gBuildDate);
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}
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+6
-6
@@ -73,14 +73,14 @@ void Sched_HandleAudioCancel(SchedContext* sched) {
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osSyncPrintf("AUDIO SP キャンセルします\n");
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if ((sched->curRSPTask != NULL) && (sched->curRSPTask->list.t.type == M_AUDTASK)) {
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if (!(HW_REG(SP_STATUS_REG, u32) & SP_STATUS_HALT)) {
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if (!(IO_READ(SP_STATUS_REG) & SP_STATUS_HALT)) {
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// Attempts to stop AUDIO SP
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osSyncPrintf("AUDIO SP止めようとします\n");
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HW_REG(SP_STATUS_REG, u32) = SP_SET_HALT;
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IO_WRITE(SP_STATUS_REG, SP_SET_HALT);
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i = 0;
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while (!(HW_REG(SP_STATUS_REG, u32) & SP_STATUS_HALT)) {
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while (!(IO_READ(SP_STATUS_REG) & SP_STATUS_HALT)) {
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if (i++ > 100) {
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// AUDIO SP did not stop (10ms timeout)
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osSyncPrintf("AUDIO SP止まりませんでした(10msタイムアウト)\n");
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@@ -135,14 +135,14 @@ void Sched_HandleGfxCancel(SchedContext* sched) {
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osSyncPrintf("GRAPH SP キャンセルします\n");
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if ((sched->curRSPTask != NULL) && (sched->curRSPTask->list.t.type == M_GFXTASK)) {
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if (!(HW_REG(SP_STATUS_REG, u32) & SP_STATUS_HALT)) {
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if (!(IO_READ(SP_STATUS_REG) & SP_STATUS_HALT)) {
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// GRAPH SP tries to stop
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osSyncPrintf("GRAPH SP止めようとします\n");
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HW_REG(SP_STATUS_REG, u32) = SP_SET_HALT;
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IO_WRITE(SP_STATUS_REG, SP_SET_HALT);
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i = 0;
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while (!(HW_REG(SP_STATUS_REG, u32) & SP_STATUS_HALT)) {
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while (!(IO_READ(SP_STATUS_REG) & SP_STATUS_HALT)) {
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if (i++ > 100) {
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// GRAPH SP did not stop (10ms timeout)
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osSyncPrintf("GRAPH SP止まりませんでした(10msタイムアウト)\n");
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@@ -1,5 +1,5 @@
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#include "global.h"
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u32 osAiGetLength(void) {
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return HW_REG(AI_LEN_REG, u32);
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return IO_READ(AI_LEN_REG);
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}
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@@ -14,7 +14,7 @@ s32 osAiSetFrequency(u32 frequency) {
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bitrate = 16;
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}
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HW_REG(AI_DACRATE_REG, u32) = dacRate - 1;
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HW_REG(AI_BITRATE_REG, u32) = bitrate - 1;
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IO_WRITE(AI_DACRATE_REG, dacRate - 1);
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IO_WRITE(AI_BITRATE_REG, bitrate - 1);
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return osViClock / (s32)dacRate;
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}
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@@ -28,30 +28,30 @@ OSPiHandle* osCartRomInit(void) {
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bzero(&__CartRomHandle.transferInfo, sizeof(__OSTranxInfo));
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/* Uses `status & PI_STATUS_ERROR` in OoT */
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while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
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while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
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;
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}
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lastLatency = HW_REG(PI_BSD_DOM1_LAT_REG, u32);
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lastPageSize = HW_REG(PI_BSD_DOM1_PGS_REG, u32);
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lastRelDuration = HW_REG(PI_BSD_DOM1_RLS_REG, u32);
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lastPulse = HW_REG(PI_BSD_DOM1_PWD_REG, u32);
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lastLatency = IO_READ(PI_BSD_DOM1_LAT_REG);
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lastPageSize = IO_READ(PI_BSD_DOM1_PGS_REG);
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lastRelDuration = IO_READ(PI_BSD_DOM1_RLS_REG);
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lastPulse = IO_READ(PI_BSD_DOM1_PWD_REG);
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HW_REG(PI_BSD_DOM1_LAT_REG, u32) = 0xFF;
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HW_REG(PI_BSD_DOM1_PGS_REG, u32) = 0;
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HW_REG(PI_BSD_DOM1_RLS_REG, u32) = 3;
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HW_REG(PI_BSD_DOM1_PWD_REG, u32) = 0xFF;
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IO_WRITE(PI_BSD_DOM1_LAT_REG, 0xFF);
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IO_WRITE(PI_BSD_DOM1_PGS_REG, 0);
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IO_WRITE(PI_BSD_DOM1_RLS_REG, 3);
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IO_WRITE(PI_BSD_DOM1_PWD_REG, 0xFF);
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initialConfig = HW_REG(__CartRomHandle.baseAddress, u32);
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initialConfig = IO_READ(__CartRomHandle.baseAddress);
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__CartRomHandle.latency = initialConfig & 0xFF;
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__CartRomHandle.pageSize = (initialConfig >> 0x10) & 0xF;
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__CartRomHandle.relDuration = (initialConfig >> 0x14) & 0xF;
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__CartRomHandle.pulse = (initialConfig >> 8) & 0xFF;
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HW_REG(PI_BSD_DOM1_LAT_REG, u32) = lastLatency;
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HW_REG(PI_BSD_DOM1_PGS_REG, u32) = lastPageSize;
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HW_REG(PI_BSD_DOM1_RLS_REG, u32) = lastRelDuration;
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HW_REG(PI_BSD_DOM1_PWD_REG, u32) = lastPulse;
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IO_WRITE(PI_BSD_DOM1_LAT_REG, lastLatency);
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IO_WRITE(PI_BSD_DOM1_PGS_REG, lastPageSize);
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IO_WRITE(PI_BSD_DOM1_RLS_REG, lastRelDuration);
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IO_WRITE(PI_BSD_DOM1_PWD_REG, lastPulse);
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prevInt = __osDisableInt();
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__CartRomHandle.next = __osPiTable;
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@@ -51,7 +51,7 @@ void __osDevMgrMain(void* arg) {
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__osEPiRawWriteIo(ioMesg->piHandle, LEO_BM_CTL, transfer->bmCtlShadow | LEO_BM_CTL_CLR_MECHANIC_INTR);
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}
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block->errStatus = 4;
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HW_REG(PI_STATUS_REG, u32) = PI_STATUS_CLEAR_INTR;
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IO_WRITE(PI_STATUS_REG, PI_STATUS_CLEAR_INTR);
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__osSetGlobalIntMask(OS_IM_PI | SR_IBIT4);
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}
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osSendMesg(ioMesg->hdr.retQueue, (OSMesg)ioMesg, OS_MESG_NOBLOCK);
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@@ -1,5 +1,5 @@
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#include "global.h"
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u32 osDpGetStatus(void) {
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return HW_REG(DPC_STATUS_REG, u32);
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return IO_READ(DPC_STATUS_REG);
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}
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@@ -1,5 +1,5 @@
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#include "global.h"
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void osDpSetStatus(u32 data) {
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HW_REG(DPC_STATUS_REG, u32) = data;
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IO_WRITE(DPC_STATUS_REG, data);
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}
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+13
-13
@@ -4,7 +4,7 @@ s32 __osEPiRawStartDma(OSPiHandle* handle, s32 direction, uintptr_t cartAddr, vo
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s32 status;
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OSPiHandle* curHandle;
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while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
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while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
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;
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}
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@@ -13,35 +13,35 @@ s32 __osEPiRawStartDma(OSPiHandle* handle, s32 direction, uintptr_t cartAddr, vo
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if (handle->domain == 0) {
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if (curHandle->latency != handle->latency) {
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HW_REG(PI_BSD_DOM1_LAT_REG, u32) = handle->latency;
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IO_WRITE(PI_BSD_DOM1_LAT_REG, handle->latency);
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}
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if (curHandle->pageSize != handle->pageSize) {
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HW_REG(PI_BSD_DOM1_PGS_REG, u32) = handle->pageSize;
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IO_WRITE(PI_BSD_DOM1_PGS_REG, handle->pageSize);
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}
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if (curHandle->relDuration != handle->relDuration) {
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HW_REG(PI_BSD_DOM1_RLS_REG, u32) = handle->relDuration;
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IO_WRITE(PI_BSD_DOM1_RLS_REG, handle->relDuration);
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}
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if (curHandle->pulse != handle->pulse) {
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HW_REG(PI_BSD_DOM1_PWD_REG, u32) = handle->pulse;
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IO_WRITE(PI_BSD_DOM1_PWD_REG, handle->pulse);
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}
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} else {
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if (curHandle->latency != handle->latency) {
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HW_REG(PI_BSD_DOM2_LAT_REG, u32) = handle->latency;
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IO_WRITE(PI_BSD_DOM2_LAT_REG, handle->latency);
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}
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if (curHandle->pageSize != handle->pageSize) {
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HW_REG(PI_BSD_DOM2_PGS_REG, u32) = handle->pageSize;
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IO_WRITE(PI_BSD_DOM2_PGS_REG, handle->pageSize);
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}
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if (curHandle->relDuration != handle->relDuration) {
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HW_REG(PI_BSD_DOM2_RLS_REG, u32) = handle->relDuration;
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IO_WRITE(PI_BSD_DOM2_RLS_REG, handle->relDuration);
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}
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if (curHandle->pulse != handle->pulse) {
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HW_REG(PI_BSD_DOM2_PWD_REG, u32) = handle->pulse;
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IO_WRITE(PI_BSD_DOM2_PWD_REG, handle->pulse);
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}
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}
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@@ -52,15 +52,15 @@ s32 __osEPiRawStartDma(OSPiHandle* handle, s32 direction, uintptr_t cartAddr, vo
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curHandle->pulse = handle->pulse;
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}
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HW_REG(PI_DRAM_ADDR_REG, void*) = (void*)osVirtualToPhysical(dramAddr);
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HW_REG(PI_CART_ADDR_REG, void*) = (void*)((handle->baseAddress | cartAddr) & 0x1FFFFFFF);
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IO_WRITE(PI_DRAM_ADDR_REG, osVirtualToPhysical(dramAddr));
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IO_WRITE(PI_CART_ADDR_REG, K1_TO_PHYS(handle->baseAddress | cartAddr));
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switch (direction) {
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case OS_READ:
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HW_REG(PI_WR_LEN_REG, u32) = size - 1;
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IO_WRITE(PI_WR_LEN_REG, size - 1);
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break;
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case OS_WRITE:
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HW_REG(PI_RD_LEN_REG, u32) = size - 1;
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IO_WRITE(PI_RD_LEN_REG, size - 1);
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break;
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default:
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return -1;
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@@ -4,7 +4,7 @@ s32 __osEPiRawReadIo(OSPiHandle* handle, uintptr_t devAddr, u32* data) {
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s32 status;
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OSPiHandle* curHandle;
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while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
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while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {
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;
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}
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@@ -13,35 +13,35 @@ s32 __osEPiRawReadIo(OSPiHandle* handle, uintptr_t devAddr, u32* data) {
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if (handle->domain == 0) {
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if (curHandle->latency != handle->latency) {
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HW_REG(PI_BSD_DOM1_LAT_REG, u32) = handle->latency;
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IO_WRITE(PI_BSD_DOM1_LAT_REG, handle->latency);
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}
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if (curHandle->pageSize != handle->pageSize) {
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HW_REG(PI_BSD_DOM1_PGS_REG, u32) = handle->pageSize;
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IO_WRITE(PI_BSD_DOM1_PGS_REG, handle->pageSize);
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}
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if (curHandle->relDuration != handle->relDuration) {
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HW_REG(PI_BSD_DOM1_RLS_REG, u32) = handle->relDuration;
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IO_WRITE(PI_BSD_DOM1_RLS_REG, handle->relDuration);
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}
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if (curHandle->pulse != handle->pulse) {
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HW_REG(PI_BSD_DOM1_PWD_REG, u32) = handle->pulse;
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IO_WRITE(PI_BSD_DOM1_PWD_REG, handle->pulse);
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}
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} else {
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if (curHandle->latency != handle->latency) {
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HW_REG(PI_BSD_DOM2_LAT_REG, u32) = handle->latency;
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IO_WRITE(PI_BSD_DOM2_LAT_REG, handle->latency);
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}
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if (curHandle->pageSize != handle->pageSize) {
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HW_REG(PI_BSD_DOM2_PGS_REG, u32) = handle->pageSize;
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IO_WRITE(PI_BSD_DOM2_PGS_REG, handle->pageSize);
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}
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if (curHandle->relDuration != handle->relDuration) {
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HW_REG(PI_BSD_DOM2_RLS_REG, u32) = handle->relDuration;
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IO_WRITE(PI_BSD_DOM2_RLS_REG, handle->relDuration);
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}
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if (curHandle->pulse != handle->pulse) {
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HW_REG(PI_BSD_DOM2_PWD_REG, u32) = handle->pulse;
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IO_WRITE(PI_BSD_DOM2_PWD_REG, handle->pulse);
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}
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}
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@@ -52,6 +52,6 @@ s32 __osEPiRawReadIo(OSPiHandle* handle, uintptr_t devAddr, u32* data) {
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curHandle->pulse = handle->pulse;
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}
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*data = HW_REG(handle->baseAddress | devAddr, u32);
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*data = IO_READ(handle->baseAddress | devAddr);
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return 0;
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}
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@@ -4,42 +4,42 @@ s32 __osEPiRawWriteIo(OSPiHandle* handle, uintptr_t devAddr, u32 data) {
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s32 status;
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OSPiHandle* curHandle;
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while (status = HW_REG(PI_STATUS_REG, u32), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {}
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while (status = IO_READ(PI_STATUS_REG), status & (PI_STATUS_BUSY | PI_STATUS_IOBUSY)) {}
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if (__osCurrentHandle[handle->domain]->type != handle->type) {
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curHandle = __osCurrentHandle[handle->domain];
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if (handle->domain == 0) {
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if (curHandle->latency != handle->latency) {
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HW_REG(PI_BSD_DOM1_LAT_REG, u32) = handle->latency;
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IO_WRITE(PI_BSD_DOM1_LAT_REG, handle->latency);
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}
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if (curHandle->pageSize != handle->pageSize) {
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HW_REG(PI_BSD_DOM1_PGS_REG, u32) = handle->pageSize;
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IO_WRITE(PI_BSD_DOM1_PGS_REG, handle->pageSize);
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}
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if (curHandle->relDuration != handle->relDuration) {
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HW_REG(PI_BSD_DOM1_RLS_REG, u32) = handle->relDuration;
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IO_WRITE(PI_BSD_DOM1_RLS_REG, handle->relDuration);
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}
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if (curHandle->pulse != handle->pulse) {
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HW_REG(PI_BSD_DOM1_PWD_REG, u32) = handle->pulse;
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IO_WRITE(PI_BSD_DOM1_PWD_REG, handle->pulse);
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}
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} else {
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if (curHandle->latency != handle->latency) {
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HW_REG(PI_BSD_DOM2_LAT_REG, u32) = handle->latency;
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IO_WRITE(PI_BSD_DOM2_LAT_REG, handle->latency);
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}
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if (curHandle->pageSize != handle->pageSize) {
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HW_REG(PI_BSD_DOM2_PGS_REG, u32) = handle->pageSize;
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IO_WRITE(PI_BSD_DOM2_PGS_REG, handle->pageSize);
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}
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if (curHandle->relDuration != handle->relDuration) {
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HW_REG(PI_BSD_DOM2_RLS_REG, u32) = handle->relDuration;
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IO_WRITE(PI_BSD_DOM2_RLS_REG, handle->relDuration);
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}
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if (curHandle->pulse != handle->pulse) {
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HW_REG(PI_BSD_DOM2_PWD_REG, u32) = handle->pulse;
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IO_WRITE(PI_BSD_DOM2_PWD_REG, handle->pulse);
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}
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}
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@@ -50,6 +50,6 @@ s32 __osEPiRawWriteIo(OSPiHandle* handle, uintptr_t devAddr, u32 data) {
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curHandle->pulse = handle->pulse;
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}
|
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HW_REG(handle->baseAddress | devAddr, u32) = data;
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IO_WRITE(handle->baseAddress | devAddr, data);
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return 0;
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}
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@@ -1,22 +1,22 @@
|
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#include "global.h"
|
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|
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s32 __osPiRawStartDma(s32 direction, uintptr_t devAddr, void* dramAddr, size_t size) {
|
||||
register int status = HW_REG(PI_STATUS_REG, u32);
|
||||
register int status = IO_READ(PI_STATUS_REG);
|
||||
|
||||
while (status & (PI_STATUS_IOBUSY | PI_STATUS_BUSY)) {
|
||||
status = HW_REG(PI_STATUS_REG, u32);
|
||||
status = IO_READ(PI_STATUS_REG);
|
||||
}
|
||||
|
||||
HW_REG(PI_DRAM_ADDR_REG, u32) = osVirtualToPhysical(dramAddr);
|
||||
IO_WRITE(PI_DRAM_ADDR_REG, osVirtualToPhysical(dramAddr));
|
||||
|
||||
HW_REG(PI_CART_ADDR_REG, u32) = K1_TO_PHYS((uintptr_t)osRomBase | devAddr);
|
||||
IO_WRITE(PI_CART_ADDR_REG, K1_TO_PHYS((uintptr_t)osRomBase | devAddr));
|
||||
|
||||
switch (direction) {
|
||||
case OS_READ:
|
||||
HW_REG(PI_WR_LEN_REG, u32) = size - 1;
|
||||
IO_WRITE(PI_WR_LEN_REG, size - 1);
|
||||
break;
|
||||
case OS_WRITE:
|
||||
HW_REG(PI_RD_LEN_REG, u32) = size - 1;
|
||||
IO_WRITE(PI_RD_LEN_REG, size - 1);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#include "global.h"
|
||||
|
||||
s32 __osSiDeviceBusy() {
|
||||
register u32 status = HW_REG(SI_STATUS_REG, u32);
|
||||
register u32 status = IO_READ(SI_STATUS_REG);
|
||||
|
||||
if (status & (SI_STATUS_DMA_BUSY | SI_STATUS_IO_READ_BUSY)) {
|
||||
return true;
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#include "global.h"
|
||||
|
||||
s32 __osSiRawStartDma(s32 direction, void* dramAddr) {
|
||||
if (HW_REG(SI_STATUS_REG, u32) & (SI_STATUS_DMA_BUSY | SI_STATUS_IO_READ_BUSY)) {
|
||||
if (IO_READ(SI_STATUS_REG) & (SI_STATUS_DMA_BUSY | SI_STATUS_IO_READ_BUSY)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
@@ -9,12 +9,12 @@ s32 __osSiRawStartDma(s32 direction, void* dramAddr) {
|
||||
osWritebackDCache(dramAddr, PIF_RAM_SIZE);
|
||||
}
|
||||
|
||||
HW_REG(SI_DRAM_ADDR_REG, u32) = osVirtualToPhysical(dramAddr);
|
||||
IO_WRITE(SI_DRAM_ADDR_REG, osVirtualToPhysical(dramAddr));
|
||||
|
||||
if (direction == OS_READ) {
|
||||
HW_REG(SI_PIF_ADDR_RD64B_REG, void*) = (void*)PIF_RAM_START;
|
||||
IO_WRITE(SI_PIF_ADDR_RD64B_REG, PIF_RAM_START);
|
||||
} else {
|
||||
HW_REG(SI_PIF_ADDR_WR64B_REG, void*) = (void*)PIF_RAM_START;
|
||||
IO_WRITE(SI_PIF_ADDR_WR64B_REG, PIF_RAM_START);
|
||||
}
|
||||
|
||||
if (direction == OS_READ) {
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
#include "global.h"
|
||||
|
||||
s32 __osSpDeviceBusy(void) {
|
||||
register u32 status = HW_REG(SP_STATUS_REG, u32);
|
||||
register u32 status = IO_READ(SP_STATUS_REG);
|
||||
|
||||
if (status & (SP_STATUS_DMA_BUSY | SP_STATUS_DMA_FULL | SP_STATUS_IO_FULL)) {
|
||||
return true;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#include "global.h"
|
||||
|
||||
u32 __osSpGetStatus() {
|
||||
return HW_REG(SP_STATUS_REG, u32);
|
||||
return IO_READ(SP_STATUS_REG);
|
||||
}
|
||||
|
||||
@@ -1,17 +1,17 @@
|
||||
#include "global.h"
|
||||
|
||||
s32 __osSpRawStartDma(s32 direction, void* devAddr, void* dramAddr, size_t size) {
|
||||
s32 __osSpRawStartDma(s32 direction, u32 devAddr, void* dramAddr, size_t size) {
|
||||
if (__osSpDeviceBusy()) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
HW_REG(SP_MEM_ADDR_REG, u32) = devAddr;
|
||||
HW_REG(SP_DRAM_ADDR_REG, u32) = osVirtualToPhysical(dramAddr);
|
||||
IO_WRITE(SP_MEM_ADDR_REG, devAddr);
|
||||
IO_WRITE(SP_DRAM_ADDR_REG, osVirtualToPhysical(dramAddr));
|
||||
|
||||
if (direction == OS_READ) {
|
||||
HW_REG(SP_WR_LEN_REG, u32) = size - 1;
|
||||
IO_WRITE(SP_WR_LEN_REG, size - 1);
|
||||
} else {
|
||||
HW_REG(SP_RD_LEN_REG, u32) = size - 1;
|
||||
IO_WRITE(SP_RD_LEN_REG, size - 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
@@ -1,13 +1,12 @@
|
||||
#include "global.h"
|
||||
|
||||
s32 __osSpSetPc(void* pc) {
|
||||
register u32 spStatus = HW_REG(SP_STATUS_REG, u32);
|
||||
s32 __osSpSetPc(u32 pc) {
|
||||
register u32 spStatus = IO_READ(SP_STATUS_REG);
|
||||
|
||||
if (!(spStatus & SP_STATUS_HALT)) {
|
||||
return -1;
|
||||
} else {
|
||||
HW_REG(SP_PC_REG, void*) = pc;
|
||||
}
|
||||
IO_WRITE(SP_PC_REG, pc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
#include "global.h"
|
||||
|
||||
void __osSpSetStatus(u32 data) {
|
||||
HW_REG(SP_STATUS_REG, u32) = data;
|
||||
IO_WRITE(SP_STATUS_REG, data);
|
||||
}
|
||||
|
||||
@@ -33,19 +33,19 @@ void osSpTaskLoad(OSTask* intp) {
|
||||
intp->t.flags &= ~OS_TASK_YIELDED;
|
||||
|
||||
if (tp->t.flags & OS_TASK_LOADABLE) {
|
||||
tp->t.ucode = HW_REG((uintptr_t)intp->t.yieldDataPtr + OS_YIELD_DATA_SIZE - 4, u32);
|
||||
tp->t.ucode = IO_READ((uintptr_t)intp->t.yieldDataPtr + OS_YIELD_DATA_SIZE - 4);
|
||||
}
|
||||
}
|
||||
osWritebackDCache(tp, sizeof(OSTask));
|
||||
__osSpSetStatus(SP_CLR_SIG0 | SP_CLR_SIG1 | SP_CLR_SIG2 | SP_SET_INTR_BREAK);
|
||||
|
||||
while (__osSpSetPc((void*)SP_IMEM_START) == -1) {}
|
||||
while (__osSpSetPc(SP_IMEM_START) == -1) {}
|
||||
|
||||
while (__osSpRawStartDma(1, (void*)(SP_IMEM_START - sizeof(*tp)), tp, sizeof(OSTask)) == -1) {}
|
||||
while (__osSpRawStartDma(1, (SP_IMEM_START - sizeof(*tp)), tp, sizeof(OSTask)) == -1) {}
|
||||
|
||||
while (__osSpDeviceBusy()) {}
|
||||
|
||||
while (__osSpRawStartDma(1, (void*)SP_IMEM_START, tp->t.ucodeBoot, tp->t.ucodeBootSize) == -1) {}
|
||||
while (__osSpRawStartDma(1, SP_IMEM_START, tp->t.ucodeBoot, tp->t.ucodeBootSize) == -1) {}
|
||||
}
|
||||
|
||||
void osSpTaskStartGo(OSTask* tp) {
|
||||
|
||||
@@ -24,9 +24,9 @@ void __osViInit(void) {
|
||||
__osViNext->state = 0x20;
|
||||
__osViNext->features = __osViNext->modep->comRegs.ctrl;
|
||||
|
||||
while (HW_REG(VI_CURRENT_REG, u32) > 10) {}
|
||||
while (IO_READ(VI_CURRENT_REG) > 10) {}
|
||||
|
||||
HW_REG(VI_STATUS_REG, u32) = 0;
|
||||
IO_WRITE(VI_STATUS_REG, 0);
|
||||
|
||||
__osViSwapContext();
|
||||
}
|
||||
|
||||
@@ -13,7 +13,7 @@ void __osViSwapContext(void) {
|
||||
field = 0;
|
||||
viNext = __osViNext;
|
||||
viMode = viNext->modep;
|
||||
field = HW_REG(VI_V_CURRENT_LINE_REG, u32) & 1;
|
||||
field = IO_READ(VI_V_CURRENT_LINE_REG) & 1;
|
||||
s2 = osVirtualToPhysical(viNext->buffer);
|
||||
origin = (viMode->fldRegs[field].origin) + s2;
|
||||
if (viNext->state & 2) {
|
||||
@@ -46,19 +46,19 @@ void __osViSwapContext(void) {
|
||||
origin = osVirtualToPhysical(viNext->buffer);
|
||||
}
|
||||
|
||||
HW_REG(VI_ORIGIN_REG, u32) = origin;
|
||||
HW_REG(VI_WIDTH_REG, u32) = viMode->comRegs.width;
|
||||
HW_REG(VI_BURST_REG, u32) = viMode->comRegs.burst;
|
||||
HW_REG(VI_V_SYNC_REG, u32) = viMode->comRegs.vSync;
|
||||
HW_REG(VI_H_SYNC_REG, u32) = viMode->comRegs.hSync;
|
||||
HW_REG(VI_LEAP_REG, u32) = viMode->comRegs.leap;
|
||||
HW_REG(VI_H_START_REG, u32) = hStart;
|
||||
HW_REG(VI_V_START_REG, u32) = vstart;
|
||||
HW_REG(VI_V_BURST_REG, u32) = viMode->fldRegs[field].vBurst;
|
||||
HW_REG(VI_INTR_REG, u32) = viMode->fldRegs[field].vIntr;
|
||||
HW_REG(VI_X_SCALE_REG, u32) = viNext->x.scale;
|
||||
HW_REG(VI_Y_SCALE_REG, u32) = viNext->y.scale;
|
||||
HW_REG(VI_CONTROL_REG, u32) = viNext->features;
|
||||
IO_WRITE(VI_ORIGIN_REG, origin);
|
||||
IO_WRITE(VI_WIDTH_REG, viMode->comRegs.width);
|
||||
IO_WRITE(VI_BURST_REG, viMode->comRegs.burst);
|
||||
IO_WRITE(VI_V_SYNC_REG, viMode->comRegs.vSync);
|
||||
IO_WRITE(VI_H_SYNC_REG, viMode->comRegs.hSync);
|
||||
IO_WRITE(VI_LEAP_REG, viMode->comRegs.leap);
|
||||
IO_WRITE(VI_H_START_REG, hStart);
|
||||
IO_WRITE(VI_V_START_REG, vstart);
|
||||
IO_WRITE(VI_V_BURST_REG, viMode->fldRegs[field].vBurst);
|
||||
IO_WRITE(VI_INTR_REG, viMode->fldRegs[field].vIntr);
|
||||
IO_WRITE(VI_X_SCALE_REG, viNext->x.scale);
|
||||
IO_WRITE(VI_Y_SCALE_REG, viNext->y.scale);
|
||||
IO_WRITE(VI_CONTROL_REG, viNext->features);
|
||||
|
||||
__osViNext = __osViCurr;
|
||||
__osViCurr = viNext;
|
||||
|
||||
@@ -20,16 +20,16 @@ UNK_TYPE4 D_8009CF70;
|
||||
|
||||
void __createSpeedParam(void) {
|
||||
__Dom1SpeedParam.type = DEVICE_TYPE_INIT;
|
||||
__Dom1SpeedParam.latency = HW_REG(PI_BSD_DOM1_LAT_REG, u32);
|
||||
__Dom1SpeedParam.pulse = HW_REG(PI_BSD_DOM1_PWD_REG, u32);
|
||||
__Dom1SpeedParam.pageSize = HW_REG(PI_BSD_DOM1_PGS_REG, u32);
|
||||
__Dom1SpeedParam.relDuration = HW_REG(PI_BSD_DOM1_RLS_REG, u32);
|
||||
__Dom1SpeedParam.latency = IO_READ(PI_BSD_DOM1_LAT_REG);
|
||||
__Dom1SpeedParam.pulse = IO_READ(PI_BSD_DOM1_PWD_REG);
|
||||
__Dom1SpeedParam.pageSize = IO_READ(PI_BSD_DOM1_PGS_REG);
|
||||
__Dom1SpeedParam.relDuration = IO_READ(PI_BSD_DOM1_RLS_REG);
|
||||
|
||||
__Dom2SpeedParam.type = DEVICE_TYPE_INIT;
|
||||
__Dom2SpeedParam.latency = HW_REG(PI_BSD_DOM2_LAT_REG, u32);
|
||||
__Dom2SpeedParam.pulse = HW_REG(PI_BSD_DOM2_PWD_REG, u32);
|
||||
__Dom2SpeedParam.pageSize = HW_REG(PI_BSD_DOM2_PGS_REG, u32);
|
||||
__Dom2SpeedParam.relDuration = HW_REG(PI_BSD_DOM2_RLS_REG, u32);
|
||||
__Dom2SpeedParam.latency = IO_READ(PI_BSD_DOM2_LAT_REG);
|
||||
__Dom2SpeedParam.pulse = IO_READ(PI_BSD_DOM2_PWD_REG);
|
||||
__Dom2SpeedParam.pageSize = IO_READ(PI_BSD_DOM2_PGS_REG);
|
||||
__Dom2SpeedParam.relDuration = IO_READ(PI_BSD_DOM2_RLS_REG);
|
||||
}
|
||||
|
||||
void __osInitialize_common(void) {
|
||||
@@ -74,9 +74,9 @@ void __osInitialize_common(void) {
|
||||
while (true) {}
|
||||
}
|
||||
|
||||
HW_REG(AI_CONTROL_REG, u32) = 1;
|
||||
HW_REG(AI_DACRATE_REG, u32) = 0x3FFF;
|
||||
HW_REG(AI_BITRATE_REG, u32) = 0xF;
|
||||
IO_WRITE(AI_CONTROL_REG, 1);
|
||||
IO_WRITE(AI_DACRATE_REG, 0x3FFF);
|
||||
IO_WRITE(AI_BITRATE_REG, 0xF);
|
||||
}
|
||||
|
||||
void __osInitialize_autodetect(void) {
|
||||
|
||||
Reference in New Issue
Block a user