mirror of
https://github.com/RetroPortingToolKit/psxrecomp
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Record GPU list CPU holds, per-source exception cycles and recent C0 readbacks in always-on rings
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
This commit is contained in:
Matthew Stanley
+10
-4
@@ -65,6 +65,9 @@ Columns: **N** = native, **D** = DuckStation oracle.
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| `sio_state` | ✓ | ✓ | — | SIO registers + (native only) pad/memcard protocol + TX/RX history |
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| `irq_state` | ✓ | ✓ | — | `I_STAT`, `I_MASK` (both), plus chain state on native |
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| `dma_state` | ✓ | ✓ | — | DPCR, DICR, all 7 channel states (madr/bcr/chcr) |
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| `irq_exc_stats` | ✓ | | — | Cumulative per-source exception accounting since boot: deliveries and guest cycles from entry to exit, charged to every `I_STAT & I_MASK` bit pending at entry (`sw` = software interrupt only). Diff two snapshots for a window. `irqctx_ring` entries carry the matching `exit_cycle` |
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| `dma_hold_stats` | ✓ | | — | Cumulative CPU holds for kicked GPU linked-list walks (the kicking store returns only when the walk ends): count, guest `held_cycles`, host `host_us`, words, advance steps, and the `exc_*` share for kicks made inside an exception handler (that host time is what `phase_profile` reports as `exc_share`) |
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| `dma_hold_ring` | ✓ | | `count`, `frame_lo`, `frame_hi` | Newest held kicks (ring of 4096): cycle, frame, held cycles, words, steps, host µs, kick PC, MADR, `in_exc`, `still_active` |
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| `event_state` | | ✓ | — | EvCB table summary (stub on DS — events are BIOS-level) |
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| `overlay_state` | | ✓ | — | Current overlay info |
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| `cdrom_sector_dump` | ✓ | | `offset`, `len` | Dump bytes from the last CD-ROM sector observed by the controller, including LBA/mode metadata |
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@@ -431,9 +434,9 @@ The TCP server is the canonical instrumentation surface. Rule 3 in `CLAUDE.md` i
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## Complete command index (generated)
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**345 commands registered** — 332 on the native server (`runtime/src/debug_server.c`), 61 on the Beetle server (`runtime/src/beetle_debug_server.c`).
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**348 commands registered** — 335 on the native server (`runtime/src/debug_server.c`), 61 on the Beetle server (`runtime/src/beetle_debug_server.c`).
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63 of 345 have prose above; **282 are index-only**. An index-only command still works — it just has no description here yet. Send it `{"cmd":"<name>"}` and read the reply, or find its `handle_*` function in the server source.
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68 of 348 have prose above; **280 are index-only**. An index-only command still works — it just has no description here yet. Send it `{"cmd":"<name>"}` and read the reply, or find its `handle_*` function in the server source.
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Regenerate with `python tools/gen_tcp_commands.py`; `--check` fails if this block has drifted from the code.
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@@ -517,6 +520,8 @@ Regenerate with `python tools/gen_tcp_commands.py`; `--check` fails if this bloc
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| `display_ring_get` | ✓ | | |
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| `display_ring_stats` | ✓ | | |
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| `dma_cdrom_history` | ✓ | | |
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| `dma_hold_ring` | ✓ | | ✓ |
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| `dma_hold_stats` | ✓ | | ✓ |
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| `dma_state` | ✓ | | ✓ |
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| `dma_trace_clear` | ✓ | | |
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| `dma_trace_dump` | ✓ | | |
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@@ -592,8 +597,9 @@ Regenerate with `python tools/gen_tcp_commands.py`; `--check` fails if this bloc
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| `insn_freeze_snapshot` | ✓ | | |
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| `insn_freeze_status` | ✓ | | |
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| `insn_freeze_target` | ✓ | | |
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| `irq_exc_stats` | ✓ | | ✓ |
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| `irq_state` | ✓ | | ✓ |
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| `irqctx_ring` | ✓ | | |
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| `irqctx_ring` | ✓ | | ✓ |
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| `kernel_bless` | ✓ | | |
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| `latency` | ✓ | | |
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| `load_transitions` | ✓ | | |
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@@ -649,7 +655,7 @@ Regenerate with `python tools/gen_tcp_commands.py`; `--check` fails if this bloc
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| `pgxp_miss_ring` | ✓ | | |
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| `pgxp_shadow` | ✓ | | |
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| `phase_hot` | ✓ | | |
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| `phase_profile` | ✓ | | |
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| `phase_profile` | ✓ | | ✓ |
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| `ping` | ✓ | ✓ | ✓ |
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| `present_image_ring_get` | ✓ | | |
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| `present_image_ring_stats` | ✓ | | |
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@@ -168,6 +168,30 @@ void dma_debug_get_gpu_ot_stats(DMAGpuOtStats* out);
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uint64_t dma_debug_get_cdrom_history(const DMACDROMHistoryEntry** out_entries);
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void dma_debug_clear_cdrom_history(void);
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/* Always-on record of every CPU hold for a kicked GPU linked-list walk
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* (the kicking store returns only when the walk ends). Ring is the newest
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* DMA_GPU_HOLD_RING_CAP holds; stats are cumulative since boot. */
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#define DMA_GPU_HOLD_RING_CAP 4096u
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typedef struct {
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uint64_t seq;
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uint64_t cycle; /* guest cycle at the kick */
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uint32_t held_cycles; /* guest cycles the CPU was held */
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uint32_t words; /* list words the walk moved during the hold */
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uint32_t steps; /* advance+service iterations the hold ran */
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uint32_t host_us; /* host wall time spent inside the hold */
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uint32_t frame;
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uint32_t kick_pc; /* guest store PC that kicked the walk */
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uint32_t madr;
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uint8_t in_exception; /* kick came from inside an exception handler */
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uint8_t still_active; /* hold ended with the walk still running */
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} DMAGpuHoldEntry;
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typedef struct {
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uint64_t count, held_cycles, host_us, words, steps;
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uint64_t exc_count, exc_held_cycles, exc_host_us;
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} DMAGpuHoldStats;
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void dma_debug_get_gpu_hold(DMAGpuHoldStats *out_stats,
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const DMAGpuHoldEntry **out_ring);
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#ifdef __cplusplus
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}
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#endif
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+105
-8
@@ -6371,6 +6371,8 @@ static void handle_a0_history(int id, const char *json)
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}
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extern int gpu_get_c0_count(void);
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extern uint64_t gpu_get_c0_total(void);
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extern uint32_t gpu_get_c0_frame(int index);
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extern int gpu_get_c0_history(int index, int *x, int *y, int *w, int *h,
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uint32_t *func, uint32_t *sp, uint32_t *s1,
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uint32_t *fw0, uint32_t *fw1, int *rcount);
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@@ -6379,17 +6381,18 @@ static void handle_c0_history(int id, const char *json)
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{
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(void)json;
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int count = gpu_get_c0_count();
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char buf[8192];
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int pos = snprintf(buf, sizeof(buf), "{\"id\":%d,\"ok\":true,\"count\":%d,\"reads\":[", id, count);
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char buf[65536];
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int pos = snprintf(buf, sizeof(buf), "{\"id\":%d,\"ok\":true,\"count\":%d,\"total\":%llu,\"reads\":[",
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id, count, (unsigned long long)gpu_get_c0_total());
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for (int i = 0; i < count && pos < (int)sizeof(buf) - 300; i++) {
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int x, y, w, h, rcount;
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uint32_t func, sp, s1, fw0, fw1;
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gpu_get_c0_history(i, &x, &y, &w, &h, &func, &sp, &s1, &fw0, &fw1, &rcount);
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pos += snprintf(buf + pos, sizeof(buf) - pos,
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"%s{\"i\":%d,\"x\":%d,\"y\":%d,\"w\":%d,\"h\":%d,"
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"%s{\"i\":%d,\"frame\":%u,\"x\":%d,\"y\":%d,\"w\":%d,\"h\":%d,"
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"\"func\":\"0x%08X\",\"sp\":\"0x%08X\",\"s1\":\"0x%08X\","
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"\"fw0\":\"0x%08X\",\"fw1\":\"0x%08X\",\"reads\":%d}",
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i ? "," : "", i, x, y, w, h, func, sp, s1, fw0, fw1, rcount);
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i ? "," : "", i, gpu_get_c0_frame(i), x, y, w, h, func, sp, s1, fw0, fw1, rcount);
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}
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pos += snprintf(buf + pos, sizeof(buf) - pos, "]}");
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send_fmt("%s", buf);
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@@ -11016,13 +11019,103 @@ static void handle_d44_ring(int id, const char *json)
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* callback word [0x80079D44], CD-DMA-active + dma-depth, and COP0/IRQ state. Shows
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* whether VBlank was delivered while 0x80079D44 was the clobbered 0x016F0110 AND a
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* CD DMA was mid-transfer (the VSync-in-DMA-window bug). */
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/* irq_exc_stats: cumulative per-source exception accounting since boot
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* (interrupts.c). Each delivery is charged to every I_STAT&I_MASK bit pending
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* at entry ("sw" = software interrupt only), with the guest cycles from entry
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* to the exit restore decision. Diff two snapshots for a window. */
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static void handle_irq_exc_stats(int id, const char *json)
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{
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(void)json;
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extern uint64_t g_exc_src_deliveries[12], g_exc_src_cycles[12];
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extern uint64_t g_exc_cycles_total, g_exc_exits_total, g_irqctx_seq;
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static const char *names[12] = { "vblank", "gpu", "cdrom", "dma", "tmr0",
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"tmr1", "tmr2", "sio0", "sio1", "spu", "lightpen", "sw" };
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char buf[2048];
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size_t pos = 0;
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pos += snprintf(buf + pos, sizeof(buf) - pos,
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"{\"id\":%d,\"ok\":true,\"cycle\":%llu,\"frame\":%llu,"
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"\"deliveries\":%llu,\"exits\":%llu,\"exc_cycles\":%llu,\"src\":{",
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id, (unsigned long long)psx_get_cycle_count(),
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(unsigned long long)s_frame_count,
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(unsigned long long)g_irqctx_seq,
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(unsigned long long)g_exc_exits_total,
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(unsigned long long)g_exc_cycles_total);
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for (int b = 0; b < 12; b++)
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pos += snprintf(buf + pos, sizeof(buf) - pos,
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"%s\"%s\":{\"n\":%llu,\"cyc\":%llu}", b ? "," : "", names[b],
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(unsigned long long)g_exc_src_deliveries[b],
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(unsigned long long)g_exc_src_cycles[b]);
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snprintf(buf + pos, sizeof(buf) - pos, "}}");
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debug_server_send_line(buf);
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}
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/* dma_hold_stats: cumulative totals for CPU holds on kicked GPU linked-list
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* walks (dma.c), split by kicks made inside an exception handler. */
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static void handle_dma_hold_stats(int id, const char *json)
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{
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(void)json;
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DMAGpuHoldStats st;
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dma_debug_get_gpu_hold(&st, NULL);
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send_fmt("{\"id\":%d,\"ok\":true,\"frame\":%llu,\"count\":%llu,\"held_cycles\":%llu,"
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"\"host_us\":%llu,\"words\":%llu,\"steps\":%llu,\"exc_count\":%llu,"
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"\"exc_held_cycles\":%llu,\"exc_host_us\":%llu}",
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id, (unsigned long long)s_frame_count,
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(unsigned long long)st.count, (unsigned long long)st.held_cycles,
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(unsigned long long)st.host_us, (unsigned long long)st.words,
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(unsigned long long)st.steps, (unsigned long long)st.exc_count,
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(unsigned long long)st.exc_held_cycles, (unsigned long long)st.exc_host_us);
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}
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/* dma_hold_ring: newest `count` held kicks (default 256, max ring cap),
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* optionally windowed by frame_lo/frame_hi. */
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static void handle_dma_hold_ring(int id, const char *json)
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{
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int count = json_get_int(json, "count", 256);
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int flo = json_get_int(json, "frame_lo", -1);
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int fhi = json_get_int(json, "frame_hi", -1);
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if (count < 1) count = 1;
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if (count > (int)DMA_GPU_HOLD_RING_CAP) count = (int)DMA_GPU_HOLD_RING_CAP;
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DMAGpuHoldStats st;
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const DMAGpuHoldEntry *ring = NULL;
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dma_debug_get_gpu_hold(&st, &ring);
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uint64_t total = st.count;
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uint32_t avail = total < DMA_GPU_HOLD_RING_CAP ? (uint32_t)total : DMA_GPU_HOLD_RING_CAP;
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uint32_t n = (uint32_t)count < avail ? (uint32_t)count : avail;
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size_t BUF_SZ = 256u + (size_t)n * 260u;
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char *buf = (char *)malloc(BUF_SZ);
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if (!buf) { send_err(id, "oom"); return; }
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size_t pos = 0;
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int emitted = 0;
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pos += snprintf(buf + pos, BUF_SZ - pos,
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"{\"id\":%d,\"ok\":true,\"total\":%llu,\"entries\":[",
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id, (unsigned long long)total);
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for (uint32_t i = 0; i < n && pos < BUF_SZ - 260; i++) {
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const DMAGpuHoldEntry *e = &ring[(total - n + i) & (DMA_GPU_HOLD_RING_CAP - 1u)];
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if (flo >= 0 && (int)e->frame < flo) continue;
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if (fhi >= 0 && (int)e->frame > fhi) continue;
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pos += snprintf(buf + pos, BUF_SZ - pos,
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"%s{\"seq\":%llu,\"cycle\":%llu,\"frame\":%u,\"held_cycles\":%u,"
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"\"words\":%u,\"steps\":%u,\"host_us\":%u,\"kick_pc\":\"0x%08X\","
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"\"madr\":\"0x%08X\",\"in_exc\":%u,\"still_active\":%u}",
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emitted ? "," : "", (unsigned long long)e->seq,
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(unsigned long long)e->cycle, e->frame, e->held_cycles, e->words,
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e->steps, e->host_us, e->kick_pc, e->madr,
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(unsigned)e->in_exception, (unsigned)e->still_active);
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emitted++;
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}
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pos += snprintf(buf + pos, BUF_SZ - pos, "],\"emitted\":%d}", emitted);
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debug_server_send_line(buf);
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free(buf);
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}
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static void handle_irqctx_ring(int id, const char *json)
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{
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typedef struct { uint64_t seq, cycle; uint32_t frame, istat, imask, sr, d44,
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cdrom_active, is_vblank; int dma_depth;
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uint32_t take_pc, real_epc, exit_pc, exit_reason, same_thread,
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restored, v0_exit, v0_saved, v1_exit, v1_saved, ra_exit,
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ra_saved, redirects, entry_sp, pump_site; } E;
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ra_saved, redirects, entry_sp, pump_site;
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uint64_t exit_cycle; } E; /* must match IrqCtxEntry */
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extern E g_irqctx_ring[]; extern uint64_t g_irqctx_seq;
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/* Ring cap must track IRQCTX_RING_CAP in interrupts.c. */
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uint32_t cap = 4096u;
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@@ -11036,7 +11129,7 @@ static void handle_irqctx_ring(int id, const char *json)
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uint64_t total = g_irqctx_seq;
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uint32_t avail = total < cap ? (uint32_t)total : cap;
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uint32_t n = (uint32_t)count < avail ? (uint32_t)count : avail;
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size_t BUF_SZ = 512u + (size_t)n * 410u;
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size_t BUF_SZ = 512u + (size_t)n * 480u;
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char *buf = (char *)malloc(BUF_SZ); if (!buf) { send_err(id, "oom"); return; }
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size_t pos = 0;
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pos += snprintf(buf + pos, BUF_SZ - pos,
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@@ -11057,13 +11150,14 @@ static void handle_irqctx_ring(int id, const char *json)
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"\"v0_exit\":\"0x%08X\",\"v0_saved\":\"0x%08X\","
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"\"v1_exit\":\"0x%08X\",\"v1_saved\":\"0x%08X\","
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"\"ra_exit\":\"0x%08X\",\"ra_saved\":\"0x%08X\",\"redirects\":%u,"
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"\"entry_sp\":\"0x%08X\",\"pump_site\":%u}",
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"\"entry_sp\":\"0x%08X\",\"pump_site\":%u,\"exit_cycle\":%llu}",
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emitted ? "," : "", (unsigned long long)e->seq, (unsigned long long)e->cycle,
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e->frame, e->is_vblank, e->d44, e->cdrom_active, e->dma_depth,
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e->sr, e->istat, e->imask,
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e->take_pc, e->real_epc, e->exit_pc, e->exit_reason, e->same_thread,
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e->restored, e->v0_exit, e->v0_saved, e->v1_exit, e->v1_saved,
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e->ra_exit, e->ra_saved, e->redirects, e->entry_sp, e->pump_site);
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e->ra_exit, e->ra_saved, e->redirects, e->entry_sp, e->pump_site,
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(unsigned long long)e->exit_cycle);
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emitted++;
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}
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pos += snprintf(buf + pos, BUF_SZ - pos, "],\"emitted\":%d}", emitted);
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@@ -15083,6 +15177,9 @@ static const CmdEntry s_commands[] = {
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{ "freeze_check", handle_freeze_check },
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{ "d44_ring", handle_d44_ring },
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{ "irqctx_ring", handle_irqctx_ring },
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{ "irq_exc_stats", handle_irq_exc_stats },
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{ "dma_hold_stats", handle_dma_hold_stats },
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{ "dma_hold_ring", handle_dma_hold_ring },
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{ "sp_ring", handle_sp_ring },
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{ "disp_ring", handle_disp_ring },
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{ "cyc_watch", handle_cyc_watch },
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@@ -31,6 +31,16 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <time.h>
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#ifdef _WIN32
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#ifndef WIN32_LEAN_AND_MEAN
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#define WIN32_LEAN_AND_MEAN
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#endif
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#ifndef NOMINMAX
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#define NOMINMAX
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#endif
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#include <windows.h>
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#endif
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#include "gpu_timeline.h"
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/* Word-aligned main-RAM offset of a DMA address (MADR / stepped cursor)
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@@ -807,16 +817,78 @@ static void start_async_gpu_linked_list(void) {
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* its text packets from a template, clearing the link) cannot reach it before
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* the walk does. A cyclic list still ends at the walker's node limit. The hold
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* also ends if an advance moves no list word. */
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/* Always-on hold observability (dma_hold_stats / dma_hold_ring). Every held
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* kick is recorded with its guest cost, its host wall time and whether it was
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* made from inside an exception handler: a kick from an IRQ callback runs the
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* whole walk (and the GPU work it feeds) with in_exception set, which is what
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* the phase profiler's exc_share then measures. */
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extern int psx_get_in_exception(void);
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static DMAGpuHoldEntry s_hold_ring[DMA_GPU_HOLD_RING_CAP];
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static DMAGpuHoldStats s_hold_stats;
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static uint64_t hold_host_ticks(void) {
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#ifdef _WIN32
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LARGE_INTEGER c; QueryPerformanceCounter(&c); return (uint64_t)c.QuadPart;
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#else
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struct timespec ts; timespec_get(&ts, TIME_UTC); /* C11; diagnostics only */
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return (uint64_t)ts.tv_sec * 1000000000ull + (uint64_t)ts.tv_nsec;
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#endif
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}
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static uint64_t hold_host_ticks_per_sec(void) {
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#ifdef _WIN32
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LARGE_INTEGER f; QueryPerformanceFrequency(&f); return (uint64_t)f.QuadPart;
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#else
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return 1000000000ull;
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#endif
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}
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static void hold_cpu_for_gpu_linked_list(void) {
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if (psx_in_device_service || g_ls_replay_active || g_psx_render_pass_active)
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return;
|
||||
const uint64_t cyc0 = psx_cycle_count;
|
||||
const uint64_t host0 = hold_host_ticks();
|
||||
const uint32_t words0 = gpu_linked_list.total_words;
|
||||
uint32_t steps = 0;
|
||||
while (gpu_linked_list.active && ((channels[2].chcr >> 24) & 1u) &&
|
||||
channel_enabled(2)) {
|
||||
const uint32_t moved = gpu_linked_list.total_words;
|
||||
psx_advance_cycles(dma_gpu_ll_cycles_to_event(&gpu_linked_list));
|
||||
psx_devices_service_to_now();
|
||||
steps++;
|
||||
if (gpu_linked_list.active && gpu_linked_list.total_words == moved) break;
|
||||
}
|
||||
const uint64_t host_us = (hold_host_ticks() - host0) * 1000000ull /
|
||||
hold_host_ticks_per_sec();
|
||||
const int in_exc = psx_get_in_exception() != 0;
|
||||
DMAGpuHoldEntry *e = &s_hold_ring[s_hold_stats.count & (DMA_GPU_HOLD_RING_CAP - 1u)];
|
||||
e->seq = s_hold_stats.count;
|
||||
e->cycle = cyc0;
|
||||
e->held_cycles = (uint32_t)(psx_cycle_count - cyc0);
|
||||
e->words = gpu_linked_list.total_words - words0;
|
||||
e->steps = steps;
|
||||
e->host_us = (uint32_t)(host_us > 0xFFFFFFFFull ? 0xFFFFFFFFull : host_us);
|
||||
e->frame = (uint32_t)s_frame_count;
|
||||
e->kick_pc = g_debug_last_store_pc;
|
||||
e->madr = channels[2].madr;
|
||||
e->in_exception = (uint8_t)in_exc;
|
||||
e->still_active = (uint8_t)(gpu_linked_list.active != 0);
|
||||
s_hold_stats.count++;
|
||||
s_hold_stats.held_cycles += e->held_cycles;
|
||||
s_hold_stats.host_us += host_us;
|
||||
s_hold_stats.words += e->words;
|
||||
s_hold_stats.steps += steps;
|
||||
if (in_exc) {
|
||||
s_hold_stats.exc_count++;
|
||||
s_hold_stats.exc_held_cycles += e->held_cycles;
|
||||
s_hold_stats.exc_host_us += host_us;
|
||||
}
|
||||
}
|
||||
|
||||
void dma_debug_get_gpu_hold(DMAGpuHoldStats *out_stats,
|
||||
const DMAGpuHoldEntry **out_ring) {
|
||||
if (out_stats) *out_stats = s_hold_stats;
|
||||
if (out_ring) *out_ring = s_hold_ring;
|
||||
}
|
||||
|
||||
static uint32_t execute_ch2_gpu(void) {
|
||||
|
||||
+24
-7
@@ -3484,15 +3484,18 @@ static uint32_t v_display_y2;
|
||||
/* GPUREAD latch (GP1(10h) get-info result, or VRAM read data) */
|
||||
static uint32_t gpuread_latch;
|
||||
|
||||
/* C0 (VRAM→CPU) capture slot — forward declaration for gpu_read_gpuread */
|
||||
#define C0_HISTORY_CAP_FWD 32
|
||||
/* C0 (VRAM→CPU) history: an always-on ring of the most recent reads
|
||||
* (it used to keep only the first 32 since boot, so gameplay readbacks were
|
||||
* invisible). Forward declaration for gpu_read_gpuread. */
|
||||
#define C0_HISTORY_CAP_FWD 256
|
||||
static struct C0HistEntry {
|
||||
uint16_t x, y, w, h;
|
||||
uint32_t func_addr, sp_val, s1_val;
|
||||
uint32_t first_words[4];
|
||||
int read_count;
|
||||
uint32_t frame;
|
||||
} c0_history_fwd[C0_HISTORY_CAP_FWD];
|
||||
static int c0_history_count_fwd = 0;
|
||||
static uint64_t c0_history_count_fwd = 0; /* total reads since boot */
|
||||
static int c0_capture_slot_fwd = -1;
|
||||
|
||||
/* Vblank presentation callback */
|
||||
@@ -5747,11 +5750,18 @@ static void gp0_exec_cpu_to_vram(void) {
|
||||
#define c0_history_count c0_history_count_fwd
|
||||
#define c0_capture_slot c0_capture_slot_fwd
|
||||
|
||||
int gpu_get_c0_count(void) { return c0_history_count; }
|
||||
/* Total GP0 C0 reads since boot; the ring holds the newest C0_HISTORY_CAP. */
|
||||
uint64_t gpu_get_c0_total(void) { return c0_history_count; }
|
||||
int gpu_get_c0_count(void) {
|
||||
return c0_history_count < C0_HISTORY_CAP ? (int)c0_history_count : C0_HISTORY_CAP;
|
||||
}
|
||||
/* index 0 = oldest entry still in the ring. */
|
||||
int gpu_get_c0_history(int index, int *x, int *y, int *w, int *h,
|
||||
uint32_t *func, uint32_t *sp, uint32_t *s1,
|
||||
uint32_t *fw0, uint32_t *fw1, int *rcount) {
|
||||
if (index < 0 || index >= c0_history_count) return 0;
|
||||
if (index < 0 || index >= gpu_get_c0_count()) return 0;
|
||||
if (c0_history_count > C0_HISTORY_CAP)
|
||||
index = (int)((c0_history_count + (uint64_t)index) % C0_HISTORY_CAP);
|
||||
*x = c0_history[index].x; *y = c0_history[index].y;
|
||||
*w = c0_history[index].w; *h = c0_history[index].h;
|
||||
*func = c0_history[index].func_addr;
|
||||
@@ -5762,6 +5772,12 @@ int gpu_get_c0_history(int index, int *x, int *y, int *w, int *h,
|
||||
*rcount = c0_history[index].read_count;
|
||||
return 1;
|
||||
}
|
||||
uint32_t gpu_get_c0_frame(int index) {
|
||||
if (index < 0 || index >= gpu_get_c0_count()) return 0;
|
||||
if (c0_history_count > C0_HISTORY_CAP)
|
||||
index = (int)((c0_history_count + (uint64_t)index) % C0_HISTORY_CAP);
|
||||
return c0_history[index].frame;
|
||||
}
|
||||
|
||||
static void gp0_exec_vram_to_cpu(void) {
|
||||
/* 0xC0 — VRAM→CPU Copy (3 words)
|
||||
@@ -5777,8 +5793,9 @@ static void gp0_exec_vram_to_cpu(void) {
|
||||
vram_read_h = (h == 0) ? 0x200 : (uint16_t)h;
|
||||
|
||||
/* Record for debug */
|
||||
if (c0_history_count < C0_HISTORY_CAP) {
|
||||
int slot = c0_history_count++;
|
||||
{
|
||||
int slot = (int)(c0_history_count++ % C0_HISTORY_CAP);
|
||||
c0_history[slot].frame = (uint32_t)s_frame_count;
|
||||
c0_history[slot].x = vram_read_x;
|
||||
c0_history[slot].y = vram_read_y;
|
||||
c0_history[slot].w = vram_read_w;
|
||||
|
||||
@@ -82,9 +82,18 @@ typedef struct {
|
||||
* corrupt snapshot (0x801384AC paired with 0x801EFE80). */
|
||||
uint32_t entry_sp; /* cpu->gpr[29] at exception entry */
|
||||
uint32_t pump_site; /* g_cosim_dirty_pump_site at entry (which delivery path) */
|
||||
uint64_t exit_cycle; /* guest cycle at the exit restore decision (0 = not exited) */
|
||||
} IrqCtxEntry;
|
||||
IrqCtxEntry g_irqctx_ring[IRQCTX_RING_CAP];
|
||||
uint64_t g_irqctx_seq = 0;
|
||||
/* Always-on per-source exception accounting (irq_exc_stats). A delivery is
|
||||
* charged to every I_STAT&I_MASK bit pending at entry (index 11 = software
|
||||
* interrupt only); cycles are guest cycles from entry to the exit restore
|
||||
* decision, so a handler that stalls (e.g. a held DMA kick) shows up here. */
|
||||
uint64_t g_exc_src_deliveries[12];
|
||||
uint64_t g_exc_src_cycles[12];
|
||||
uint64_t g_exc_cycles_total;
|
||||
uint64_t g_exc_exits_total;
|
||||
extern uint64_t psx_get_cycle_count(void);
|
||||
|
||||
/* Record an interrupt-delivery decision into the event ring. GATE outcomes are
|
||||
@@ -2000,6 +2009,20 @@ irq_deliver_eval:
|
||||
e->v1_saved = saved_gpr[3];
|
||||
e->ra_exit = cpu->gpr[31];
|
||||
e->ra_saved = saved_gpr[31];
|
||||
e->exit_cycle = psx_get_cycle_count();
|
||||
{
|
||||
const uint64_t spent = e->exit_cycle - e->cycle;
|
||||
const uint32_t pend = (e->istat & e->imask) & 0x7FFu;
|
||||
g_exc_cycles_total += spent;
|
||||
g_exc_exits_total++;
|
||||
if (!pend) { g_exc_src_deliveries[11]++; g_exc_src_cycles[11] += spent; }
|
||||
for (int b = 0; b < 11; b++) {
|
||||
if (pend & (1u << b)) {
|
||||
g_exc_src_deliveries[b]++;
|
||||
g_exc_src_cycles[b] += spent;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (do_restore) {
|
||||
for (int i = 0; i < 32; i++) cpu->gpr[i] = saved_gpr[i];
|
||||
|
||||
@@ -21,6 +21,8 @@
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "dma.h"
|
||||
|
||||
void dma_init(void);
|
||||
void dma_write(uint32_t addr, uint32_t val);
|
||||
void dma_advance(uint32_t cycles);
|
||||
@@ -87,6 +89,8 @@ void event_ring_record_aux(uint16_t kind, uint8_t detail, uint32_t aux) {
|
||||
(void)kind; (void)detail; (void)aux;
|
||||
}
|
||||
void psx_irq_raise(uint32_t bit, uint32_t detail) { (void)bit; (void)detail; }
|
||||
static int s_in_exception;
|
||||
int psx_get_in_exception(void) { return s_in_exception; }
|
||||
|
||||
/* ---- scenario ------------------------------------------------------------ */
|
||||
#define NODE_A 0x00001000u
|
||||
@@ -153,6 +157,30 @@ int main(void) {
|
||||
"GPU received %u words (%08X %08X %08X), expected A's and B's payload",
|
||||
s_gp0_n, s_gp0[0], s_gp0[1], s_gp0[2]);
|
||||
|
||||
/* The hold is recorded in the always-on hold ring (dma_hold_stats /
|
||||
* dma_hold_ring): A's header + 2 words, B's header + 1 word, C's header. */
|
||||
{
|
||||
DMAGpuHoldStats st; const DMAGpuHoldEntry *ring = NULL;
|
||||
dma_debug_get_gpu_hold(&st, &ring);
|
||||
CHECK(st.count == 1u && st.exc_count == 0u, "hold count %llu exc %llu",
|
||||
(unsigned long long)st.count, (unsigned long long)st.exc_count);
|
||||
CHECK(ring && ring[0].words == 6u && ring[0].held_cycles == psx_cycle_count - before
|
||||
&& ring[0].cycle == before && ring[0].in_exception == 0u
|
||||
&& ring[0].still_active == 0u,
|
||||
"hold entry words %u held %u cycle %llu", ring ? ring[0].words : 0u,
|
||||
ring ? ring[0].held_cycles : 0u,
|
||||
ring ? (unsigned long long)ring[0].cycle : 0ull);
|
||||
/* A kick from inside an exception handler is attributed to it. */
|
||||
s_in_exception = 1;
|
||||
kick(0);
|
||||
s_in_exception = 0;
|
||||
dma_debug_get_gpu_hold(&st, &ring);
|
||||
CHECK(st.count == 2u && st.exc_count == 1u && ring[1].in_exception == 1u &&
|
||||
st.exc_held_cycles == ring[1].held_cycles,
|
||||
"exception-kick attribution: count %llu exc %llu",
|
||||
(unsigned long long)st.count, (unsigned long long)st.exc_count);
|
||||
}
|
||||
|
||||
/* Control: a kick from inside the device service is not held. */
|
||||
CHECK(kick(1), "a kick from inside the device service was held");
|
||||
finish_walk();
|
||||
|
||||
Reference in New Issue
Block a user