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https://github.com/RetroPortingToolKit/psxrecomp
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Matthew Stanley
98 lines
5.3 KiB
Markdown
98 lines
5.3 KiB
Markdown
# RFC: FMV callback overhead without guest-state changes
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Status: design review only. No IRQ batching implementation or runtime flag is
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added. Tracking: `beads-eio.3.150`. The contributor's actual prototype patch,
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instrumentation patch, PE capture bytes and raw measurements are not available.
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## What is established
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WO-10 correctly identifies repeated generated block callbacks. With precise
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slicing disabled, the runtime slice body returns early, but the DLL still calls
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through its callback shim. That observation does not quantify the host cost.
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WO-11's own trials did not demonstrate a repeatable batching speedup.
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The reported missing live CFG predecessors were independently reproduced.
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The live address-order loop heuristic also labels acyclic backward jumps as
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loops. These are separately addressed in [PR #354](https://github.com/RetroPortingToolKit/psxrecomp/pull/354).
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Even corrected static metadata does not enumerate every indirect, alias or CPS
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resume edge; it cannot prove that a block is runtime-private.
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## A concrete merge blocker
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The supplied design suppresses `psx_icache_fetch` along with IRQ checks.
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That is not simply reducing host calls. The added native test executes the real
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cache model with a header, a cold body on another line, and the header again:
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| State | Preserve body fetch | Omit body fetch |
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| --- | ---: | ---: |
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| Charged fetch cycles | 14 | 7 |
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| Pending selected load give-back | 0 | 99 |
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| Body cache tag | `0x80010020` | invalid (`1`) |
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The header executes in both cases. The effect matches the in-tree Beetle
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`PS_CPU::ReadInstruction` miss charging and `ReadAbsorb` clearing. This is a
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counterexample to the described operation, not an execution of the missing
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prototype and not certification of every detail of the current cache model.
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## Required invariants for any future patch
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1. Every executed instruction retains its guest cycle charge, including delay
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slots and cache/memory/multiply/GTE effects. Cache tags and load give-back
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evolve identically; removing a host callback must not remove its semantics.
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2. Devices and interrupts remain visible at required guest boundaries. One loop
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iteration or four blocks is not a cycle/deadline bound. Account for pending
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IRQs, COP0, nested/irreducible loops, memory effects and long blocks.
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3. Every supported CPS/alias/indirect entry remains valid, including entries
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not represented by static predecessor edges. A single predecessor is not a
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privacy proof and static unreachability is not permission to delete code.
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4. Unsupported analysis fails closed to the existing faithful path. No per-game
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exclusions, generated-C edits or default-on speculative behavior.
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5. Behavior-changing flags participate in emitted-artifact/cache identity.
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Prove cold/warm and off/on/off transitions cannot reuse the wrong DLL.
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Natural-loop classification requires graph structure, not address order; see
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[LLVM's loop definition](https://llvm.org/docs/LoopTerminology.html#loop-definition).
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## Supplemental evidence requested
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- Exact base revision, complete prototype patch, diagnostic schema patch and
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the exact enabled flags/build commands. Do not reconstruct the patch from
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prose and call it the contributor's tested implementation.
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- For PE-specific attribution: capture JSON with bytes, `game.toml`, seeds,
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matching DLL/manifest identities and bounded raw timing records. Those assets
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are unavailable locally and must not be invented.
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- Inclusive versus exclusive callback timing; treatment of host preemption,
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reentrancy and CPS continuations. Unserialized RDTSC/global counters need
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explicit validation before reporting cycles per guest iteration.
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- Repeatable content-aligned trials with every target invocation represented,
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not only frames where it was the maximum dispatch. Include per-frame tail
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latency, audio underruns and guest-state/event-order comparison.
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## Acceptance before implementation is considered mergeable
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- Synthetic cold/conflicting/uncached fetch, load give-back, pending IRQ,
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deadline crossing, COP0, delay-slot, alias/CPS, nested-loop and irreducible-CFG
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tests; explicit first-divergence comparison where state/timing can change.
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- Unmodified default-path output comparison and cache-key transition tests.
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- Regenerated Tomba/MMX6/Ape LLE boot, FMV, menus and gameplay regression with
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screenshots and progress/state evidence; BIOS/device timing calibrated against
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the independent Beetle oracle. A visual smoke run alone is insufficient.
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- A demonstrated benefit, measured separately from PGO/LTO/debug configuration.
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## Other unresolved brief items
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WO-8's PE decoder is a profiling lead, not proof that the guest algorithm alone
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causes the stalls. Any predecode cache or worker-thread proposal first needs
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verified input identity, memory ownership, dependencies and ordering.
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WO-9's mismatched DLL/manifest rejection is correct. If a longer rejection
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history is wanted, propose a bounded ring exposed over TCP, preserving pair
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validation and atomic publication. Do not add runtime stderr/file logging.
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Current `pgo-train` already finishes the successful profile-use/debug-OFF build.
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Its failure report and exact source revision are needed to investigate the
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claimed early stop. Runtime PGO/LTO do not automatically cover independently
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compiled overlay DLLs. Those build experiments are separate from this RFC.
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Nothing in this draft should be merged as an IRQ performance fix.
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