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This commit is contained in:
KrimtonZ
2021-05-18 16:28:11 -05:00
parent b006dc9e86
commit edeb7fdec0
13 changed files with 1384 additions and 427 deletions
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a.out
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asm/non_matchings/virtual_console/cpu/cpuExecuteOpcode.s
+2 -2
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@@ -1457,7 +1457,7 @@ lbl_80036D5C:
/* 80036DFC 000323BC 56 C4 AE FE */ rlwinm r4, r22, 0x15, 0x1b, 0x1f
/* 80036E00 000323C0 80 C5 00 4C */ lwz r6, 0x4c(r5)
/* 80036E04 000323C4 38 A0 00 00 */ li r5, 0
/* 80036E08 000323C8 4B FD 72 E1 */ bl func_8000E0E8
/* 80036E08 000323C8 4B FD 72 E1 */ bl cpuSetRegisterCP0
/* 80036E0C 000323CC 48 00 2D BC */ b lbl_80039BC8
/* 80036E10 000323D0 56 C0 9E 38 */ rlwinm r0, r22, 0x13, 0x18, 0x1c
/* 80036E14 000323D4 7F 43 D3 78 */ mr r3, r26
@@ -1465,7 +1465,7 @@ lbl_80036D5C:
/* 80036E1C 000323DC 56 C4 AE FE */ rlwinm r4, r22, 0x15, 0x1b, 0x1f
/* 80036E20 000323E0 80 A6 00 48 */ lwz r5, 0x48(r6)
/* 80036E24 000323E4 80 C6 00 4C */ lwz r6, 0x4c(r6)
/* 80036E28 000323E8 4B FD 72 C1 */ bl func_8000E0E8
/* 80036E28 000323E8 4B FD 72 C1 */ bl cpuSetRegisterCP0
/* 80036E2C 000323EC 48 00 2D 9C */ b lbl_80039BC8
/* 80036E30 000323F0 56 C0 05 7F */ clrlwi. r0, r22, 0x15
/* 80036E34 000323F4 40 82 01 64 */ bne lbl_80036F98
asm/non_matchings/virtual_console/cpu/func_8003D47C.s → asm/non_matchings/virtual_console/cpu/cpuGetOffsetAddress.s
+1 -1
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@@ -1,4 +1,4 @@
glabel func_8003D47C
glabel cpuGetOffsetAddress
/* 8003D47C 00038A3C 94 21 FF D0 */ stwu r1, -0x30(r1)
/* 8003D480 00038A40 7C 08 02 A6 */ mflr r0
/* 8003D484 00038A44 90 01 00 34 */ stw r0, 0x34(r1)
asm/non_matchings/virtual_console/cpu/cpuReset.s
+1 -1
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@@ -233,7 +233,7 @@ lbl_8003CB30:
/* 8003CBDC 0003819C 90 03 0A 94 */ stw r0, 0xa94(r3)
/* 8003CBE0 000381A0 93 C3 0A 90 */ stw r30, 0xa90(r3)
/* 8003CBE4 000381A4 7F E3 FB 78 */ mr r3, r31
/* 8003CBE8 000381A8 4B FD 14 6D */ bl func_8000E054
/* 8003CBE8 000381A8 4B FD 14 6D */ bl cpuSetCP0Status
/* 8003CBEC 000381AC 3C 60 00 07 */ lis r3, 0x0006E463@ha
/* 8003CBF0 000381B0 93 DF 0A C8 */ stw r30, 0xac8(r31)
/* 8003CBF4 000381B4 38 03 E4 63 */ addi r0, r3, 0x0006E463@l
asm/non_matchings/virtual_console/cpu/func_8000E0E8.s → asm/non_matchings/virtual_console/cpu/cpuSetRegisterCP0.s
+2 -2
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@@ -3,7 +3,7 @@ glabel lbl_80170A68
.incbin "00000001.app", 0x16CB68, 0x80
.text
glabel func_8000E0E8
glabel cpuSetRegisterCP0
/* 8000E0E8 000096A8 94 21 FF E0 */ stwu r1, -0x20(r1)
/* 8000E0EC 000096AC 7C 08 02 A6 */ mflr r0
/* 8000E0F0 000096B0 90 01 00 24 */ stw r0, 0x24(r1)
@@ -69,7 +69,7 @@ lbl_8000E1BC:
/* 8000E1D8 00009798 80 84 00 64 */ lwz r4, 0x64(r4)
/* 8000E1DC 0000979C 7C A5 00 38 */ and r5, r5, r0
/* 8000E1E0 000097A0 7C C6 20 38 */ and r6, r6, r4
/* 8000E1E4 000097A4 4B FF FE 71 */ bl func_8000E054
/* 8000E1E4 000097A4 4B FF FE 71 */ bl cpuSetCP0Status
/* 8000E1E8 000097A8 48 00 00 78 */ b lbl_8000E260
/* 8000E1EC 000097AC 54 C0 05 EF */ rlwinm. r0, r6, 0, 0x17, 0x17
/* 8000E1F0 000097B0 80 6D 89 20 */ lwz r3, gSystem-_SDA_BASE_(r13)
asm/non_matchings/virtual_console/cpu/func_8000DF58.s
+1 -1
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@@ -1,4 +1,4 @@
glabel func_8000DF58
glabel cpuGetSize
/* 8000DF58 00009518 94 21 FF E0 */ stwu r1, -0x20(r1)
/* 8000DF5C 0000951C 7C 08 02 A6 */ mflr r0
/* 8000DF60 00009520 2C 06 00 00 */ cmpwi r6, 0
asm/non_matchings/virtual_console/cpu/func_8000E054.s
+3 -3
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@@ -1,4 +1,4 @@
glabel func_8000E054
glabel cpuSetCP0Status
/* 8000E054 00009614 94 21 FF D0 */ stwu r1, -0x30(r1)
/* 8000E058 00009618 7C 08 02 A6 */ mflr r0
/* 8000E05C 0000961C 90 01 00 34 */ stw r0, 0x34(r1)
@@ -12,7 +12,7 @@ glabel func_8000E054
/* 8000E07C 0000963C 93 A1 00 24 */ stw r29, 0x24(r1)
/* 8000E080 00009640 7C 7D 1B 78 */ mr r29, r3
/* 8000E084 00009644 7F E3 FB 78 */ mr r3, r31
/* 8000E088 00009648 4B FF FE D1 */ bl func_8000DF58
/* 8000E088 00009648 4B FF FE D1 */ bl cpuGetSize
/* 8000E08C 0000964C 2C 03 00 00 */ cmpwi r3, 0
/* 8000E090 00009650 40 82 00 0C */ bne lbl_8000E09C
/* 8000E094 00009654 38 60 00 00 */ li r3, 0
@@ -22,7 +22,7 @@ lbl_8000E09C:
/* 8000E0A0 00009660 38 A1 00 08 */ addi r5, r1, 8
/* 8000E0A4 00009664 80 9D 0A AC */ lwz r4, 0xaac(r29)
/* 8000E0A8 00009668 38 C1 00 10 */ addi r6, r1, 0x10
/* 8000E0AC 0000966C 4B FF FE AD */ bl func_8000DF58
/* 8000E0AC 0000966C 4B FF FE AD */ bl cpuGetSize
/* 8000E0B0 00009670 2C 03 00 00 */ cmpwi r3, 0
/* 8000E0B4 00009674 40 82 00 0C */ bne lbl_8000E0C0
/* 8000E0B8 00009678 38 60 00 00 */ li r3, 0
asm/virtual_console/code_80007020.s
+1 -1
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@@ -3754,7 +3754,7 @@ lbl_8000A594:
/* 8000A5A0 00005B60 38 A1 00 08 */ addi r5, r1, 8
/* 8000A5A4 00005B64 80 63 00 10 */ lwz r3, 0x10(r3)
/* 8000A5A8 00005B68 80 FF 00 04 */ lwz r7, 4(r31)
/* 8000A5AC 00005B6C 48 03 2E D1 */ bl func_8003D47C
/* 8000A5AC 00005B6C 48 03 2E D1 */ bl cpuGetOffsetAddress
/* 8000A5B0 00005B70 2C 03 00 00 */ cmpwi r3, 0
/* 8000A5B4 00005B74 40 82 00 0C */ bne lbl_8000A5C0
/* 8000A5B8 00005B78 38 60 00 00 */ li r3, 0
asm/virtual_console/code_800440A8.s
+8 -8
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@@ -19898,7 +19898,7 @@ lbl_80055DC4:
/* 80055DD8 00051398 7D E3 7B 78 */ mr r3, r15
/* 80055DDC 0005139C 7C A5 00 38 */ and r5, r5, r0
/* 80055DE0 000513A0 38 80 00 0C */ li r4, 0xc
/* 80055DE4 000513A4 4B FB 83 05 */ bl func_8000E0E8
/* 80055DE4 000513A4 4B FB 83 05 */ bl cpuSetRegisterCP0
/* 80055DE8 000513A8 2C 03 00 00 */ cmpwi r3, 0
/* 80055DEC 000513AC 40 82 00 0C */ bne lbl_80055DF8
/* 80055DF0 000513B0 38 60 00 00 */ li r3, 0
@@ -20265,7 +20265,7 @@ lbl_80056320:
/* 80056350 00051910 7C C6 C8 38 */ and r6, r6, r25
/* 80056354 00051914 90 A1 00 18 */ stw r5, 0x18(r1)
/* 80056358 00051918 90 C1 00 1C */ stw r6, 0x1c(r1)
/* 8005635C 0005191C 4B FB 7D 8D */ bl func_8000E0E8
/* 8005635C 0005191C 4B FB 7D 8D */ bl cpuSetRegisterCP0
/* 80056360 00051920 2C 03 00 00 */ cmpwi r3, 0
/* 80056364 00051924 40 82 00 0C */ bne lbl_80056370
/* 80056368 00051928 38 60 00 00 */ li r3, 0
@@ -20284,7 +20284,7 @@ lbl_80056370:
/* 80056398 00051958 7C C6 D0 38 */ and r6, r6, r26
/* 8005639C 0005195C 90 A1 00 18 */ stw r5, 0x18(r1)
/* 800563A0 00051960 90 C1 00 1C */ stw r6, 0x1c(r1)
/* 800563A4 00051964 4B FB 7D 45 */ bl func_8000E0E8
/* 800563A4 00051964 4B FB 7D 45 */ bl cpuSetRegisterCP0
/* 800563A8 00051968 2C 03 00 00 */ cmpwi r3, 0
/* 800563AC 0005196C 40 82 00 0C */ bne lbl_800563B8
/* 800563B0 00051970 38 60 00 00 */ li r3, 0
@@ -20475,7 +20475,7 @@ lbl_8005664C:
/* 80056650 00051C10 7D E3 7B 78 */ mr r3, r15
/* 80056654 00051C14 80 C1 00 24 */ lwz r6, 0x24(r1)
/* 80056658 00051C18 38 80 00 0B */ li r4, 0xb
/* 8005665C 00051C1C 4B FB 7A 8D */ bl func_8000E0E8
/* 8005665C 00051C1C 4B FB 7A 8D */ bl cpuSetRegisterCP0
/* 80056660 00051C20 2C 03 00 00 */ cmpwi r3, 0
/* 80056664 00051C24 40 82 00 0C */ bne lbl_80056670
/* 80056668 00051C28 38 60 00 00 */ li r3, 0
@@ -20516,7 +20516,7 @@ lbl_800566D4:
/* 800566E4 00051CA4 64 06 20 00 */ oris r6, r0, 0x2000
/* 800566E8 00051CA8 90 C1 00 24 */ stw r6, 0x24(r1)
/* 800566EC 00051CAC 90 A1 00 20 */ stw r5, 0x20(r1)
/* 800566F0 00051CB0 4B FB 79 F9 */ bl func_8000E0E8
/* 800566F0 00051CB0 4B FB 79 F9 */ bl cpuSetRegisterCP0
/* 800566F4 00051CB4 2C 03 00 00 */ cmpwi r3, 0
/* 800566F8 00051CB8 40 82 01 44 */ bne lbl_8005683C
/* 800566FC 00051CBC 38 60 00 00 */ li r3, 0
@@ -21322,7 +21322,7 @@ lbl_800572E8:
/* 80057310 000528D0 54 E0 06 1E */ rlwinm r0, r7, 0, 0x18, 0xf
/* 80057314 000528D4 90 C1 00 08 */ stw r6, 8(r1)
/* 80057318 000528D8 7C 06 33 78 */ or r6, r0, r6
/* 8005731C 000528DC 4B FB 6D CD */ bl func_8000E0E8
/* 8005731C 000528DC 4B FB 6D CD */ bl cpuSetRegisterCP0
/* 80057320 000528E0 2C 03 00 00 */ cmpwi r3, 0
/* 80057324 000528E4 40 82 00 0C */ bne lbl_80057330
/* 80057328 000528E8 38 60 00 00 */ li r3, 0
@@ -21636,7 +21636,7 @@ lbl_800577AC:
/* 800577C0 00052D80 38 80 00 0C */ li r4, 0xc
/* 800577C4 00052D84 90 C1 00 0C */ stw r6, 0xc(r1)
/* 800577C8 00052D88 38 A0 00 00 */ li r5, 0
/* 800577CC 00052D8C 4B FB 69 1D */ bl func_8000E0E8
/* 800577CC 00052D8C 4B FB 69 1D */ bl cpuSetRegisterCP0
/* 800577D0 00052D90 2C 03 00 00 */ cmpwi r3, 0
/* 800577D4 00052D94 40 82 00 0C */ bne lbl_800577E0
/* 800577D8 00052D98 38 60 00 00 */ li r3, 0
@@ -21677,7 +21677,7 @@ lbl_80057834:
/* 80057850 00052E10 7C E6 33 78 */ or r6, r7, r6
/* 80057854 00052E14 90 A1 00 08 */ stw r5, 8(r1)
/* 80057858 00052E18 90 C1 00 0C */ stw r6, 0xc(r1)
/* 8005785C 00052E1C 4B FB 68 8D */ bl func_8000E0E8
/* 8005785C 00052E1C 4B FB 68 8D */ bl cpuSetRegisterCP0
/* 80057860 00052E20 7C 03 00 D0 */ neg r0, r3
/* 80057864 00052E24 7C 00 1B 78 */ or r0, r0, r3
/* 80057868 00052E28 54 03 0F FE */ srwi r3, r0, 0x1f
include/cpu.h
+28 -8
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@@ -15,7 +15,7 @@ typedef s32 (*sd_func_t)(void* obj, u32 addr, s64* src);
typedef struct {
/* 0x0000 */ u32 unk_0;
/* 0x0004 */ void *unk_4;
/* 0x0008 */ s32 unk_8;
/* 0x0008 */ u32 unk_8;
/* 0x000C */ lb_func_t lb;
/* 0x0010 */ lh_func_t lh;
/* 0x0014 */ lw_func_t lw;
@@ -25,7 +25,10 @@ typedef struct {
/* 0x0024 */ sw_func_t sw;
/* 0x0028 */ sd_func_t sd;
/* 0x002C */ void *unk_0x2C;
/* 0x0030 */ char unk_0x30[0x10];
/* 0x0030 */ s32 unk_0x30;
/* 0x0034 */ s32 unk_0x34;
/* 0x0038 */ s32 unk_0x38;
/* 0x003C */ s32 unk_0x3C;
} cpu_dev_t; // size = 0x40
#define SM_BLK_CNT 192
@@ -41,14 +44,25 @@ typedef union {
f64 fd;
} reg64_t;
typedef struct {
reg64_t unk_0x00;
reg64_t unk_0x08;
reg64_t unk_0x10;
reg64_t unk_0x18;
reg64_t unk_0x20;
typedef union {
struct {
reg64_t unk_0x00;
reg64_t unk_0x08;
reg64_t unk_0x10;
reg64_t unk_0x18;
reg64_t unk_0x20;
};
reg64_t regs[5];
u32 regs32[10];
} unk_cpu_0x248;
typedef struct {
/* 0x0000 */ reg64_t entry_lo[2];
/* 0x0010 */ reg64_t entry_hi;
/* 0x0018 */reg64_t page_mask;
/* 0x0020 */reg64_t unk_0x20;
} cpu_tlb_t; // size = 0x28
typedef void *(*cpu_execute_func_t)();
typedef struct {
@@ -82,7 +96,13 @@ typedef struct {
/* 0x00044 */ char unk_0x44[0x4]; // maybe pad?
/* 0x00048 */ reg64_t gpr[32];
/* 0x00148 */ reg64_t fpr[32];
union {
/* 0x00248 */ unk_cpu_0x248 unk_0x248[0x30];
u32 unk_0x248regs[480];
u32 unk_0x248da[48][10];
reg64_t unk_0x248r[48][5];
cpu_tlb_t tlb[48];
};
/* 0x009C8 */ u32 fscr[32];
/* 0x00A48 */ reg64_t cp0[32];
/* 0x00B48 */ cpu_execute_func_t execute_opcode;
include/mips.h
+12
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@@ -156,18 +156,30 @@
#define MIPS_IMM(inst) ((s16)(inst & 0xFFFF))
#define MIPS_SA(inst ) ((inst >> 6) & 0x1F)
#define CP0_INDEX 0
#define CP0_RANDOM 1
#define CP0_ENTRYLO0 2
#define CP0_ENTRYLO1 3
#define CP0_CONTEXT 4
#define CP0_PAGEMASK 5
#define CP0_WIRED 6
#define CP0_BADVADDR 8
#define CP0_COUNT 9
#define CP0_ENTRYHI 10
#define CP0_COMPARE 11
#define CP0_STATUS 12
#define CP0_CAUSE 13
#define CP0_EPC 14
#define CP0_PRID 15
#define CP0_CONFIG 16
#define CP0_LLADDR
#define CP0_WATCHLO 18
#define CP0_WATCHI 19
#define CP0_XCONTEXT 20
#define CP0_PERR 26
#define CP0_CACHEERR 27
#define CP0_TAGLO 28
#define CP0_TAGHI 29
#define CP0_ERROREPC 30
#define STATUS_IE (1 << 0)
include/rom.h
+1
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@@ -166,5 +166,6 @@ typedef enum {
s32 romCopy(rom_class_t* rom, void* dst, u32 addr, s32 len, unk_rom_callback arg4);
s32 romGetBuffer(rom_class_t* rom, void** param_2, u32 addr, s32* param_4);
s32 romUpdate(rom_class_t* rom);
#endif
src/virtual_console/cpu.c
+1324 -400
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