mirror of
https://github.com/zeldaret/oot-vc.git
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KrimtonZ
124 lines
2.8 KiB
C
124 lines
2.8 KiB
C
#ifndef _MIPS_H
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#define _MIPS_H
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#define MIPS_OP(inst) ((inst >> 0x1A) & 0x3F)
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#define OPC_SPECIAL 0
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#define OPC_REGIMM 1
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#define OPC_J 2
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#define OPC_JAL 3
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#define OPC_BEQ 4
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#define OPC_BNE 5
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#define OPC_BLEZ 6
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#define OPC_BGTZ 7
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#define OPC_ADDI 8
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#define OPC_ADDIU 9
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#define OPC_SLTI 10
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#define OPC_SLTIU 11
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#define OPC_ANDI 12
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#define OPC_ORI 13
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#define OPC_XORI 14
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#define OPC_LUI 15
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#define OPC_CP0 16
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#define OPC_CP1 17
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#define SPEC_FUNCT(inst) ((inst >> 0) & 0x3F)
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#define SPEC_SLL 0
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#define SPEC_SRL 2
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#define SPEC_SRA 3
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#define SPEC_SLLV 4
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#define SPEC_SRLV 6
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#define SPEC_SRAV 7
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#define SPEC_JR 8
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#define SPEC_JALR 9
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#define SPEC_SYSCALL 12
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#define SPEC_BREAK 13
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#define SPEC_MFHI 16
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#define SPEC_MTHI 17
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#define SPEC_MFLO 18
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#define SPEC_MTLO 19
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#define SPEC_DSLLV 20
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#define SPEC_DSRLV 22
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#define SPEC_DSRAV 23
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#define SPEC_MULT 24
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#define SPEC_MULTU 25
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#define SPEC_DIV 26
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#define SPEC_DIVU 27
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#define SPEC_DMULT 28
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#define SPEC_DMULTU 29
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#define SPEC_DDIV 30
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#define SPEC_DDIVU 31
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#define SPEC_ADD 32
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#define SPEC_ADDU 33
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#define SPEC_SUB 34
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#define SPEC_SUBU 35
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#define SPEC_AND 36
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#define SPEC_OR 37
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#define SPEC_XOR 38
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#define SPEC_NOR 39
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#define SPEC_SLT 42
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#define SPEC_SLTU 43
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#define SPEC_DADD 44
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#define SPEC_DADDU 45
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#define SPEC_DSUB 46
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#define SPEC_DSUBU 47
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#define SPEC_TGE 48
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#define SPEC_TGEU 49
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#define SPEC_TLT 50
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#define SPEC_TLTU 51
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#define SPEC_TEQ 52
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#define SPEC_TNE 54
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#define SPEC_DSLL 56
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#define SPEC_DSRL 58
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#define SPEC_DSRA 59
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#define SPEC_DSLL32 60
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#define SPEC_DSRL32 62
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#define SPEC_DSRA32 63
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#define REGIMM_SUB(inst) ((inst >> 16) & 0x1F)
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#define REGIMM_BLTZ 0
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#define REGIMM_BGEZ 1
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#define REGIMM_BLTZL 2
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#define REGIMM_BGEZL 3
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#define REGIMM_TGEI 8
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#define REGIMM_TGEIU 9
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#define REGIMM_TLTI 10
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#define REGIMM_TLTIU 11
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#define REGIMM_TEQI 12
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#define REGIMM_TNEI 14
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#define REGIMM_BLTZAL 16
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#define REGIMM_BGEZAL 17
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#define REGIMM_BLTZALL 18
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#define REGIMM_BGEZALL 19
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#define MIPS_RD(inst) ((inst >> 0xB) & 0x1F)
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#define MIPS_RT(inst) ((inst >> 0x10) & 0x1F)
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#define MIPS_RS(inst) ((inst >> 0x15) & 0x1F)
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#define MIPS_FDT(inst) ((inst >> 0) & 0x7FF)
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#define MIPS_FR(inst) ((inst >> 0x15) & 0x1F)
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#define MIPS_FT(inst) ((inst >> 0x10) & 0x1F)
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#define MIPS_FS(inst) ((inst >> 0xB) & 0x1F)
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#define MIPS_FD(inst) ((inst >> 6) & 0x1F)
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#define MIPS_FSUB(inst) ((inst >> 0x15) & 0x1F)
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#define MIPS_FFMT(inst) ((inst >> 0x15) & 0x1F)
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#define MIPS_FFUNC(inst) ((inst >> 0x0) & 0x3F)
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#define MIPS_FCC(inst) ((inst >> 8) & 7)
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#define MIPS_FFMT3(inst) ((inst >> 0) & 7)
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#define MIPS_FOP4(inst) ((inst >> 3) & 7)
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#define MIPS_FMT_SINGLE 16
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#define MIPS_FMT_DOUBLE 17
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#define MIPS_FMT_WORD 20
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#define MIPS_FMT_DBLWORD 21
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#define MIPS_FSUB_MFC 0
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#define MIPS_FSUB_DMFC 1
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#define MIPS_FSUB_CFC 2
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#define MIPS_FSUB_MTC 4
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#define MIPS_FSUB_DMTC 5
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#define MIPS_FSUB_CTC 6
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#define MIPS_IMM(inst) ((s16)(inst & 0xFFFF))
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#define MIPS_SA(inst ) ((inst >> 6) & 0x1F)
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#endif |