zeldaret/oot-vc
1
0
Fork 0
mirror of https://github.com/zeldaret/oot-vc.git synced 2026-10-02 15:50:29 -04:00
Code Issues Packages Projects Releases Wiki Activity

wip

Browse Source
This commit is contained in:
KrimtonZ
2021-05-11 11:33:56 -05:00
parent d4dfa34a21
commit e70fe00a28
5 changed files with 1536 additions and 371 deletions
Download Patch File Download Diff File Expand all files Collapse all files
asm/non_matchings/virtual_console/cpu/cpuExecuteOpcode.s
+8 -8
View File
@@ -3045,7 +3045,7 @@ lbl_8003854C:
/* 80038670 00033C30 7C 9A 02 14 */ add r4, r26, r0
/* 80038674 00033C34 80 64 01 48 */ lwz r3, 0x148(r4)
/* 80038678 00033C38 80 84 01 4C */ lwz r4, 0x14c(r4)
/* 8003867C 00033C3C 48 11 AC C5 */ bl func_80153340
/* 8003867C 00033C3C 48 11 AC C5 */ bl __cvt_sll_dbl
/* 80038680 00033C40 48 12 C9 11 */ bl sqrt
/* 80038684 00033C44 48 11 AE 21 */ bl __cvt_dbl_usll
/* 80038688 00033C48 56 C0 EE 38 */ rlwinm r0, r22, 0x1d, 0x18, 0x1c
@@ -3057,7 +3057,7 @@ lbl_8003854C:
/* 800386A0 00033C60 7C 9A 02 14 */ add r4, r26, r0
/* 800386A4 00033C64 80 64 01 48 */ lwz r3, 0x148(r4)
/* 800386A8 00033C68 80 84 01 4C */ lwz r4, 0x14c(r4)
/* 800386AC 00033C6C 48 11 AC 95 */ bl func_80153340
/* 800386AC 00033C6C 48 11 AC 95 */ bl __cvt_sll_dbl
/* 800386B0 00033C70 FC 20 0A 10 */ fabs f1, f1
/* 800386B4 00033C74 48 11 AD F1 */ bl __cvt_dbl_usll
/* 800386B8 00033C78 56 C0 EE 38 */ rlwinm r0, r22, 0x1d, 0x18, 0x1c
@@ -3107,7 +3107,7 @@ lbl_8003854C:
/* 80038768 00033D28 7C 9A 02 14 */ add r4, r26, r0
/* 8003876C 00033D2C 80 64 01 48 */ lwz r3, 0x148(r4)
/* 80038770 00033D30 80 84 01 4C */ lwz r4, 0x14c(r4)
/* 80038774 00033D34 48 11 AB CD */ bl func_80153340
/* 80038774 00033D34 48 11 AB CD */ bl __cvt_sll_dbl
/* 80038778 00033D38 48 12 BE E5 */ bl ceil
/* 8003877C 00033D3C 48 11 AD 29 */ bl __cvt_dbl_usll
/* 80038780 00033D40 56 C0 EE 38 */ rlwinm r0, r22, 0x1d, 0x18, 0x1c
@@ -3119,7 +3119,7 @@ lbl_8003854C:
/* 80038798 00033D58 7C 9A 02 14 */ add r4, r26, r0
/* 8003879C 00033D5C 80 64 01 48 */ lwz r3, 0x148(r4)
/* 800387A0 00033D60 80 84 01 4C */ lwz r4, 0x14c(r4)
/* 800387A4 00033D64 48 11 AB 9D */ bl func_80153340
/* 800387A4 00033D64 48 11 AB 9D */ bl __cvt_sll_dbl
/* 800387A8 00033D68 48 12 C0 F5 */ bl floor
/* 800387AC 00033D6C 48 11 AC F9 */ bl __cvt_dbl_usll
/* 800387B0 00033D70 56 C0 EE 38 */ rlwinm r0, r22, 0x1d, 0x18, 0x1c
@@ -3145,7 +3145,7 @@ lbl_8003854C:
/* 80038800 00033DC0 7C 9A 02 14 */ add r4, r26, r0
/* 80038804 00033DC4 80 64 01 48 */ lwz r3, 0x148(r4)
/* 80038808 00033DC8 80 84 01 4C */ lwz r4, 0x14c(r4)
/* 8003880C 00033DCC 48 11 AB 35 */ bl func_80153340
/* 8003880C 00033DCC 48 11 AB 35 */ bl __cvt_sll_dbl
/* 80038810 00033DD0 48 12 BE 4D */ bl ceil
/* 80038814 00033DD4 FC 00 08 1E */ fctiwz f0, f1
/* 80038818 00033DD8 56 C0 EE 38 */ rlwinm r0, r22, 0x1d, 0x18, 0x1c
@@ -3158,7 +3158,7 @@ lbl_8003854C:
/* 80038834 00033DF4 7C 9A 02 14 */ add r4, r26, r0
/* 80038838 00033DF8 80 64 01 48 */ lwz r3, 0x148(r4)
/* 8003883C 00033DFC 80 84 01 4C */ lwz r4, 0x14c(r4)
/* 80038840 00033E00 48 11 AB 01 */ bl func_80153340
/* 80038840 00033E00 48 11 AB 01 */ bl __cvt_sll_dbl
/* 80038844 00033E04 48 12 C0 59 */ bl floor
/* 80038848 00033E08 FC 00 08 1E */ fctiwz f0, f1
/* 8003884C 00033E0C 56 C0 EE 38 */ rlwinm r0, r22, 0x1d, 0x18, 0x1c
@@ -3171,7 +3171,7 @@ lbl_8003854C:
/* 80038868 00033E28 7C 9A 02 14 */ add r4, r26, r0
/* 8003886C 00033E2C 80 64 01 48 */ lwz r3, 0x148(r4)
/* 80038870 00033E30 80 84 01 4C */ lwz r4, 0x14c(r4)
/* 80038874 00033E34 48 11 AB 7D */ bl func_801533F0
/* 80038874 00033E34 48 11 AB 7D */ bl __cvt_sll_flt
/* 80038878 00033E38 56 C0 EE 38 */ rlwinm r0, r22, 0x1d, 0x18, 0x1c
/* 8003887C 00033E3C 7C 7A 02 14 */ add r3, r26, r0
/* 80038880 00033E40 D0 23 01 4C */ stfs f1, 0x14c(r3)
@@ -3180,7 +3180,7 @@ lbl_8003854C:
/* 8003888C 00033E4C 7C 9A 02 14 */ add r4, r26, r0
/* 80038890 00033E50 80 64 01 48 */ lwz r3, 0x148(r4)
/* 80038894 00033E54 80 84 01 4C */ lwz r4, 0x14c(r4)
/* 80038898 00033E58 48 11 AA A9 */ bl func_80153340
/* 80038898 00033E58 48 11 AA A9 */ bl __cvt_sll_dbl
/* 8003889C 00033E5C 56 C0 EE 38 */ rlwinm r0, r22, 0x1d, 0x18, 0x1c
/* 800388A0 00033E60 7C 7A 02 14 */ add r3, r26, r0
/* 800388A4 00033E64 D8 23 01 48 */ stfd f1, 0x148(r3)
asm/virtual_console/code_800825B0.s
+2 -2
View File
@@ -237381,7 +237381,7 @@ lbl_80153338:
/* 80153338 0014E8F8 7C 63 2E 30 */ sraw r3, r3, r5
/* 8015333C 0014E8FC 4E 80 00 20 */ blr
glabel func_80153340
glabel __cvt_sll_dbl
/* 80153340 0014E900 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 80153344 0014E904 54 65 00 01 */ rlwinm. r5, r3, 0, 0, 0
/* 80153348 0014E908 41 82 00 0C */ beq lbl_80153354
@@ -237431,7 +237431,7 @@ lbl_801533DC:
/* 801533E8 0014E9A8 38 21 00 10 */ addi r1, r1, 0x10
/* 801533EC 0014E9AC 4E 80 00 20 */ blr
glabel func_801533F0
glabel __cvt_sll_flt
/* 801533F0 0014E9B0 94 21 FF F0 */ stwu r1, -0x10(r1)
/* 801533F4 0014E9B4 54 65 00 01 */ rlwinm. r5, r3, 0, 0, 0
/* 801533F8 0014E9B8 41 82 00 0C */ beq lbl_80153404
include/cpu.h
+9 -9
View File
@@ -3,19 +3,19 @@
#include "tree.h"
typedef s32 (*lb_func_t)(void* obj, u32 addr, s8* dst);
typedef s32 (*lh_func_t)(void* obj, u32 addr, s16* dst);
typedef s32 (*lw_func_t)(void* obj, u32 addr, s32* dst);
typedef s32 (*ld_func_t)(void* obj, u32 addr, s64* dst);
typedef s32 (*sb_func_t)(void* obj, u32 addr, s8* src);
typedef s32 (*sh_func_t)(void* obj, u32 addr, s16* src);
typedef s32 (*sw_func_t)(void* obj, u32 addr, s32* src);
typedef s32 (*sd_func_t)(void* obj, u32 addr, s64* src);
typedef s32 (*lb_func_t)(void* obj, s32 addr, s8* dst);
typedef s32 (*lh_func_t)(void* obj, s32 addr, s16* dst);
typedef s32 (*lw_func_t)(void* obj, s32 addr, s32* dst);
typedef s32 (*ld_func_t)(void* obj, s32 addr, s64* dst);
typedef s32 (*sb_func_t)(void* obj, s32 addr, s8* src);
typedef s32 (*sh_func_t)(void* obj, s32 addr, s16* src);
typedef s32 (*sw_func_t)(void* obj, s32 addr, s32* src);
typedef s32 (*sd_func_t)(void* obj, s32 addr, s64* src);
typedef struct {
/* 0x0000 */ u32 unk_0;
/* 0x0004 */ void *unk_4;
/* 0x0008 */ u32 unk_8;
/* 0x0008 */ s32 unk_8;
/* 0x000C */ lb_func_t lb;
/* 0x0010 */ lh_func_t lh;
/* 0x0014 */ lw_func_t lw;
include/mips.h
+124
View File
@@ -0,0 +1,124 @@
#ifndef _MIPS_H
#define _MIPS_H
#define MIPS_OP(inst) ((inst >> 0x1A) & 0x3F)
#define OPC_SPECIAL 0
#define OPC_REGIMM 1
#define OPC_J 2
#define OPC_JAL 3
#define OPC_BEQ 4
#define OPC_BNE 5
#define OPC_BLEZ 6
#define OPC_BGTZ 7
#define OPC_ADDI 8
#define OPC_ADDIU 9
#define OPC_SLTI 10
#define OPC_SLTIU 11
#define OPC_ANDI 12
#define OPC_ORI 13
#define OPC_XORI 14
#define OPC_LUI 15
#define OPC_CP0 16
#define OPC_CP1 17
#define SPEC_FUNCT(inst) ((inst >> 0) & 0x3F)
#define SPEC_SLL 0
#define SPEC_SRL 2
#define SPEC_SRA 3
#define SPEC_SLLV 4
#define SPEC_SRLV 6
#define SPEC_SRAV 7
#define SPEC_JR 8
#define SPEC_JALR 9
#define SPEC_SYSCALL 12
#define SPEC_BREAK 13
#define SPEC_MFHI 16
#define SPEC_MTHI 17
#define SPEC_MFLO 18
#define SPEC_MTLO 19
#define SPEC_DSLLV 20
#define SPEC_DSRLV 22
#define SPEC_DSRAV 23
#define SPEC_MULT 24
#define SPEC_MULTU 25
#define SPEC_DIV 26
#define SPEC_DIVU 27
#define SPEC_DMULT 28
#define SPEC_DMULTU 29
#define SPEC_DDIV 30
#define SPEC_DDIVU 31
#define SPEC_ADD 32
#define SPEC_ADDU 33
#define SPEC_SUB 34
#define SPEC_SUBU 35
#define SPEC_AND 36
#define SPEC_OR 37
#define SPEC_XOR 38
#define SPEC_NOR 39
#define SPEC_SLT 42
#define SPEC_SLTU 43
#define SPEC_DADD 44
#define SPEC_DADDU 45
#define SPEC_DSUB 46
#define SPEC_DSUBU 47
#define SPEC_TGE 48
#define SPEC_TGEU 49
#define SPEC_TLT 50
#define SPEC_TLTU 51
#define SPEC_TEQ 52
#define SPEC_TNE 54
#define SPEC_DSLL 56
#define SPEC_DSRL 58
#define SPEC_DSRA 59
#define SPEC_DSLL32 60
#define SPEC_DSRL32 62
#define SPEC_DSRA32 63
#define REGIMM_SUB(inst) ((inst >> 16) & 0x1F)
#define REGIMM_BLTZ 0
#define REGIMM_BGEZ 1
#define REGIMM_BLTZL 2
#define REGIMM_BGEZL 3
#define REGIMM_TGEI 8
#define REGIMM_TGEIU 9
#define REGIMM_TLTI 10
#define REGIMM_TLTIU 11
#define REGIMM_TEQI 12
#define REGIMM_TNEI 14
#define REGIMM_BLTZAL 16
#define REGIMM_BGEZAL 17
#define REGIMM_BLTZALL 18
#define REGIMM_BGEZALL 19
#define MIPS_RD(inst) ((inst >> 0xB) & 0x1F)
#define MIPS_RT(inst) ((inst >> 0x10) & 0x1F)
#define MIPS_RS(inst) ((inst >> 0x15) & 0x1F)
#define MIPS_FDT(inst) ((inst >> 0) & 0x7FF)
#define MIPS_FR(inst) ((inst >> 0x15) & 0x1F)
#define MIPS_FT(inst) ((inst >> 0x10) & 0x1F)
#define MIPS_FS(inst) ((inst >> 0xB) & 0x1F)
#define MIPS_FD(inst) ((inst >> 6) & 0x1F)
#define MIPS_FSUB(inst) ((inst >> 0x15) & 0x1F)
#define MIPS_FFMT(inst) ((inst >> 0x15) & 0x1F)
#define MIPS_FFUNC(inst) ((inst >> 0x0) & 0x3F)
#define MIPS_FCC(inst) ((inst >> 8) & 7)
#define MIPS_FFMT3(inst) ((inst >> 0) & 7)
#define MIPS_FOP4(inst) ((inst >> 3) & 7)
#define MIPS_FMT_SINGLE 16
#define MIPS_FMT_DOUBLE 17
#define MIPS_FMT_WORD 20
#define MIPS_FMT_DBLWORD 21
#define MIPS_FSUB_MFC 0
#define MIPS_FSUB_DMFC 1
#define MIPS_FSUB_CFC 2
#define MIPS_FSUB_MTC 4
#define MIPS_FSUB_DMTC 5
#define MIPS_FSUB_CTC 6
#define MIPS_IMM(inst) ((s16)(inst & 0xFFFF))
#define MIPS_SA(inst ) ((inst >> 6) & 0x1F)
#endif
src/virtual_console/cpu.c
+1393 -352
View File
File diff suppressed because it is too large Load Diff