feat(phase-32): T3 (4) — main: func_80039B20 (79 ins) BANKED byte-identical 143dbb89 via gate_main — the S80 permuter plateau at 7 was an ALIAS FLAG, not a scheduler tie

- the redundant D_80073140[i] re-read was spelled *(s32*)(base1 + i*4): a cast-wrapped PLUS is DENIED the /s
  (MEM_IN_STRUCT_P) grant (expr.c:4570-4576, §30a#1), so true_dependence kept the edge to the fixed-address
  D_800C7D20 store and pinned the re-read below it. ((s32*)base1)[i] makes the INDIRECT_REF operand a top-level
  PLUS_EXPR -> /s granted -> the load hoists into the D_800C7D20 load-delay slot. Zero drift, first compile.
  Load-bearing kept: $6/$7 pins on i/off (-23 without), the volatile launder on the D_80073140 base (-39 without).
- lesson for the router: "redundant re-read scheduled at point-of-use" -> §30 first, never the permuter (it cannot
  reach an alias flag from C — why S80's ILS plateaued at 7 from a seed of 7). Harvest note in .run/P32/t3/.
- rtu_match MATCH 79/79 (coordinator-verified); gate_main --apply: 1/1 compatible, BANKED, main byte-identical

src/800_c.c

@@ -3311,7 +3311,47 @@ void func_80039300(void) {
 
 INCLUDE_ASM("asm/nonmatchings/800_c", func_80039308);
 
-INCLUDE_ASM("asm/nonmatchings/800_c", func_80039B20);
+extern s32 D_80073140[];
+extern u8 *D_800762B0;
+extern s32 D_800C7D20;
+extern u8 D_800762B4[];
+extern s32 D_800A2B98;
+extern u8 D_800C6DD0[];
+extern u8 D_800C6DD4[];
+
+void func_80039B20(s32 *arg0, s16 arg1) {
+    register s32 i __asm__("$6");
+    register s32 off __asm__("$7");
+    u8 c;
+    s32 t1;
+
+    i = 0;
+    t1 = (s32)arg0 + arg1 * 26;
+    c = *(u8 *)((*arg0)++);
+    off = 0;
+    do {
+        if (*(u8 *)(t1 + i + 0x23) != 0 && (*(s16 *)(D_800C6DD4 + off) == c)) {
+            u8 *p = D_800C6DD0 + (s16)i * 0x60;
+            if (p[0x5A] != 0) {
+                s16 f6 = *(s16 *)(p + 6);
+                s32 off2 = f6 * 26;
+                s32 base = *(s32 *)(p + 0x50);
+                *(u8 *)(base + off2 + (s16)i + 0x23) = 0;
+                p[0x5A] = 0;
+            }
+            {
+                s32 base1 = (s32)D_80073140;
+                __asm__ __volatile__("" : "=r"(base1) : "0"(base1));
+                D_800C7D20 &= ~((s32 *)base1)[i];
+                D_800A2B98 |= ((s32 *)base1)[i];
+            }
+            D_800762B0[i] = 2;
+            D_800762B4[i] = 0;
+        }
+        i++;
+        off += 0x60;
+    } while (i < 0x10);
+}
 
 void func_80039C5C(s32 *param_1) {
     *param_1 += 2;