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T7.1.c3: gte_consolidate --keep-levers; batch c3b1: 40 files consolidated, oracle IDENTICAL

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This commit is contained in:
Drew T
2026-10-02 18:32:34 -06:00
parent 346a0dd7b4
commit 46ba9f1b16
45 changed files with 335 additions and 1171 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.run/P36/delever/calibration.json
+156 -156
View File
@@ -1,7 +1,7 @@
{
"head": "ceb2633385",
"head": "8c3937da22",
"stamp": "588cbf38c6e4",
"generated": "2026-10-02 14:33",
"generated": "2026-10-02 18:30",
"aliases": [
"main",
"md_SC07_004",
@@ -21,176 +21,176 @@
"main": {
"objects": 85,
"identical": 85,
"seconds": 6.957000000000001,
"mean_s": 0.082
"seconds": 10.391999999999998,
"mean_s": 0.122
},
"md_SC07_004": {
"objects": 1,
"identical": 1,
"seconds": 0.517,
"mean_s": 0.517
"seconds": 0.689,
"mean_s": 0.689
},
"ov_SC03_015": {
"objects": 32,
"identical": 32,
"seconds": 5.021999999999999,
"mean_s": 0.157
"seconds": 6.799000000000002,
"mean_s": 0.212
},
"ov_SC04_011": {
"objects": 28,
"identical": 28,
"seconds": 4.2109999999999985,
"mean_s": 0.15
"seconds": 5.675000000000001,
"mean_s": 0.203
}
},
"per_object_seconds": {
"build/src/800.o": 0.741,
"build/src/800_b.o": 0.075,
"build/src/800_b_2.o": 0.326,
"build/src/800_b_o0a.o": 0.075,
"build/src/800_c.o": 0.211,
"build/src/800b2.o": 0.083,
"build/src/apicard1.o": 0.084,
"build/src/apicard2.o": 0.1,
"build/src/apicard3.o": 0.066,
"build/src/apicard4.o": 0.081,
"build/src/apicard5.o": 0.083,
"build/src/apicard6.o": 0.07,
"build/src/apicard7.o": 0.092,
"build/src/boot.o": 0.087,
"build/src/gap.o": 0.081,
"build/src/libapi1.o": 0.063,
"build/src/libapi2.o": 0.06,
"build/src/libc2_1.o": 0.063,
"build/src/libc2_2.o": 0.062,
"build/src/libcd1.o": 0.08,
"build/src/libcd2.o": 0.064,
"build/src/libetc.o": 0.064,
"build/src/libgpu.o": 0.063,
"build/src/libgpu2.o": 0.068,
"build/src/libgs1.o": 0.074,
"build/src/libgs2.o": 0.064,
"build/src/libgs3.o": 0.061,
"build/src/libgs4.o": 0.069,
"build/src/libgs5.o": 0.058,
"build/src/libgs6.o": 0.078,
"build/src/libgs7.o": 0.063,
"build/src/libgs8.o": 0.064,
"build/src/libgte1.o": 0.063,
"build/src/libgte10.o": 0.059,
"build/src/libgte11.o": 0.065,
"build/src/libgte12.o": 0.063,
"build/src/libgte13.o": 0.059,
"build/src/libgte14.o": 0.062,
"build/src/libgte15.o": 0.057,
"build/src/libgte16.o": 0.06,
"build/src/libgte17.o": 0.06,
"build/src/libgte18.o": 0.077,
"build/src/libgte19.o": 0.064,
"build/src/libgte2.o": 0.061,
"build/src/libgte20.o": 0.062,
"build/src/libgte21.o": 0.063,
"build/src/libgte22.o": 0.063,
"build/src/libgte23.o": 0.087,
"build/src/libgte24.o": 0.066,
"build/src/libgte25.o": 0.057,
"build/src/libgte26.o": 0.064,
"build/src/libgte27.o": 0.074,
"build/src/libgte28.o": 0.075,
"build/src/libgte29.o": 0.064,
"build/src/800.o": 1.016,
"build/src/800_b.o": 0.15,
"build/src/800_b_2.o": 0.487,
"build/src/800_b_o0a.o": 0.072,
"build/src/800_c.o": 0.344,
"build/src/800b2.o": 0.081,
"build/src/apicard1.o": 0.077,
"build/src/apicard2.o": 0.078,
"build/src/apicard3.o": 0.074,
"build/src/apicard4.o": 0.221,
"build/src/apicard5.o": 0.129,
"build/src/apicard6.o": 0.072,
"build/src/apicard7.o": 0.199,
"build/src/boot.o": 0.219,
"build/src/gap.o": 0.201,
"build/src/libapi1.o": 0.211,
"build/src/libapi2.o": 0.201,
"build/src/libc2_1.o": 0.199,
"build/src/libc2_2.o": 0.194,
"build/src/libcd1.o": 0.215,
"build/src/libcd2.o": 0.19,
"build/src/libetc.o": 0.199,
"build/src/libgpu.o": 0.14,
"build/src/libgpu2.o": 0.154,
"build/src/libgs1.o": 0.103,
"build/src/libgs2.o": 0.087,
"build/src/libgs3.o": 0.082,
"build/src/libgs4.o": 0.087,
"build/src/libgs5.o": 0.083,
"build/src/libgs6.o": 0.092,
"build/src/libgs7.o": 0.083,
"build/src/libgs8.o": 0.08,
"build/src/libgte1.o": 0.078,
"build/src/libgte10.o": 0.072,
"build/src/libgte11.o": 0.076,
"build/src/libgte12.o": 0.086,
"build/src/libgte13.o": 0.085,
"build/src/libgte14.o": 0.088,
"build/src/libgte15.o": 0.1,
"build/src/libgte16.o": 0.089,
"build/src/libgte17.o": 0.092,
"build/src/libgte18.o": 0.089,
"build/src/libgte19.o": 0.099,
"build/src/libgte2.o": 0.088,
"build/src/libgte20.o": 0.089,
"build/src/libgte21.o": 0.095,
"build/src/libgte22.o": 0.096,
"build/src/libgte23.o": 0.088,
"build/src/libgte24.o": 0.073,
"build/src/libgte25.o": 0.088,
"build/src/libgte26.o": 0.086,
"build/src/libgte27.o": 0.082,
"build/src/libgte28.o": 0.084,
"build/src/libgte29.o": 0.08,
"build/src/libgte3.o": 0.091,
"build/src/libgte30.o": 0.064,
"build/src/libgte4.o": 0.065,
"build/src/libgte5.o": 0.063,
"build/src/libgte6.o": 0.065,
"build/src/libgte7.o": 0.061,
"build/src/libgte8.o": 0.064,
"build/src/libgte9.o": 0.064,
"build/src/libmcrd1.o": 0.077,
"build/src/libmcrd2.o": 0.066,
"build/src/libpad1.o": 0.07,
"build/src/libpad2.o": 0.072,
"build/src/sgap.o": 0.079,
"build/src/sgap_2.o": 0.068,
"build/src/sgap_3.o": 0.074,
"build/src/sgap_4.o": 0.073,
"build/src/sgap_5.o": 0.065,
"build/src/sgap_6.o": 0.064,
"build/src/sgap_8.o": 0.073,
"build/src/snd1.o": 0.096,
"build/src/snd10.o": 0.074,
"build/src/snd11.o": 0.07,
"build/src/snd12.o": 0.071,
"build/src/snd2.o": 0.07,
"build/src/snd3.o": 0.066,
"build/src/snd4.o": 0.068,
"build/src/snd5.o": 0.063,
"build/src/snd6.o": 0.074,
"build/src/snd7.o": 0.063,
"build/src/snd8.o": 0.063,
"build/src/snd9.o": 0.063,
"build/src/md_SC07_004/md_SC07_004.o": 0.517,
"build/src/ov_SC03_015/ov_SC03_015.o": 0.143,
"build/src/ov_SC03_015/ov_SC03_015_after.o": 0.517,
"build/src/ov_SC03_015/ov_SC03_015_jr_8012ACE0.o": 0.404,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135888.o": 0.071,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135A4C.o": 0.071,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135D20.o": 0.139,
"build/src/ov_SC03_015/ov_SC03_015_jr_801380E0.o": 0.176,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013C98C.o": 0.138,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013F350.o": 0.089,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013FFD8.o": 0.075,
"build/src/ov_SC03_015/ov_SC03_015_jr_80140608.o": 0.194,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015444C.o": 0.083,
"build/src/ov_SC03_015/ov_SC03_015_jr_80154C24.o": 0.182,
"build/src/ov_SC03_015/ov_SC03_015_jr_801588CC.o": 0.097,
"build/src/ov_SC03_015/ov_SC03_015_jr_80159C84.o": 0.078,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015A3C8.o": 0.084,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015AE2C.o": 0.109,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015C32C.o": 0.498,
"build/src/ov_SC03_015/ov_SC03_015_jr_8016AB6C.o": 0.267,
"build/src/ov_SC03_015/ov_SC03_015_jr_80171B4C.o": 0.111,
"build/src/ov_SC03_015/ov_SC03_015_jr_801734BC.o": 0.215,
"build/src/ov_SC03_015/ov_SC03_015_jr_801789AC.o": 0.075,
"build/src/ov_SC03_015/ov_SC03_015_jr_80178D40.o": 0.113,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017A4AC.o": 0.085,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.o": 0.175,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.o": 0.212,
"build/src/ov_SC03_015/ov_SC03_015_jr_80184440.o": 0.063,
"build/src/ov_SC03_015/ov_SC03_015_jr_801848E4.o": 0.281,
"build/src/ov_SC03_015/ov_SC03_015_o0b.o": 0.057,
"build/src/ov_SC03_015/ov_SC03_015_o0c.o": 0.071,
"build/src/ov_SC03_015/ov_SC03_015_o0d.o": 0.067,
"build/src/ov_SC03_015/ov_SC03_015_o0e.o": 0.082,
"build/src/ov_SC04_011/ov_SC04_011.o": 0.134,
"build/src/ov_SC04_011/ov_SC04_011_after.o": 0.43,
"build/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.o": 0.358,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135888.o": 0.062,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135A4C.o": 0.057,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135D20.o": 0.134,
"build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.147,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.o": 0.123,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.089,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.073,
"build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.189,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.082,
"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.174,
"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.106,
"build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.074,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.074,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.102,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.36,
"build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.228,
"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.103,
"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.178,
"build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.072,
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.11,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.08,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.106,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.446,
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.06,
"build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.06
"build/src/libgte30.o": 0.08,
"build/src/libgte4.o": 0.092,
"build/src/libgte5.o": 0.08,
"build/src/libgte6.o": 0.083,
"build/src/libgte7.o": 0.093,
"build/src/libgte8.o": 0.093,
"build/src/libgte9.o": 0.082,
"build/src/libmcrd1.o": 0.107,
"build/src/libmcrd2.o": 0.08,
"build/src/libpad1.o": 0.082,
"build/src/libpad2.o": 0.099,
"build/src/sgap.o": 0.088,
"build/src/sgap_2.o": 0.098,
"build/src/sgap_3.o": 0.086,
"build/src/sgap_4.o": 0.095,
"build/src/sgap_5.o": 0.079,
"build/src/sgap_6.o": 0.079,
"build/src/sgap_8.o": 0.087,
"build/src/snd1.o": 0.084,
"build/src/snd10.o": 0.078,
"build/src/snd11.o": 0.081,
"build/src/snd12.o": 0.075,
"build/src/snd2.o": 0.091,
"build/src/snd3.o": 0.076,
"build/src/snd4.o": 0.078,
"build/src/snd5.o": 0.087,
"build/src/snd6.o": 0.084,
"build/src/snd7.o": 0.084,
"build/src/snd8.o": 0.089,
"build/src/snd9.o": 0.088,
"build/src/md_SC07_004/md_SC07_004.o": 0.689,
"build/src/ov_SC03_015/ov_SC03_015.o": 0.204,
"build/src/ov_SC03_015/ov_SC03_015_after.o": 0.674,
"build/src/ov_SC03_015/ov_SC03_015_jr_8012ACE0.o": 0.517,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135888.o": 0.089,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135A4C.o": 0.106,
"build/src/ov_SC03_015/ov_SC03_015_jr_80135D20.o": 0.188,
"build/src/ov_SC03_015/ov_SC03_015_jr_801380E0.o": 0.222,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013C98C.o": 0.182,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013F350.o": 0.144,
"build/src/ov_SC03_015/ov_SC03_015_jr_8013FFD8.o": 0.12,
"build/src/ov_SC03_015/ov_SC03_015_jr_80140608.o": 0.276,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015444C.o": 0.147,
"build/src/ov_SC03_015/ov_SC03_015_jr_80154C24.o": 0.266,
"build/src/ov_SC03_015/ov_SC03_015_jr_801588CC.o": 0.152,
"build/src/ov_SC03_015/ov_SC03_015_jr_80159C84.o": 0.116,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015A3C8.o": 0.115,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015AE2C.o": 0.149,
"build/src/ov_SC03_015/ov_SC03_015_jr_8015C32C.o": 0.628,
"build/src/ov_SC03_015/ov_SC03_015_jr_8016AB6C.o": 0.395,
"build/src/ov_SC03_015/ov_SC03_015_jr_80171B4C.o": 0.151,
"build/src/ov_SC03_015/ov_SC03_015_jr_801734BC.o": 0.284,
"build/src/ov_SC03_015/ov_SC03_015_jr_801789AC.o": 0.097,
"build/src/ov_SC03_015/ov_SC03_015_jr_80178D40.o": 0.154,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017A4AC.o": 0.112,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.o": 0.245,
"build/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.o": 0.267,
"build/src/ov_SC03_015/ov_SC03_015_jr_80184440.o": 0.086,
"build/src/ov_SC03_015/ov_SC03_015_jr_801848E4.o": 0.351,
"build/src/ov_SC03_015/ov_SC03_015_o0b.o": 0.078,
"build/src/ov_SC03_015/ov_SC03_015_o0c.o": 0.09,
"build/src/ov_SC03_015/ov_SC03_015_o0d.o": 0.083,
"build/src/ov_SC03_015/ov_SC03_015_o0e.o": 0.111,
"build/src/ov_SC04_011/ov_SC04_011.o": 0.194,
"build/src/ov_SC04_011/ov_SC04_011_after.o": 0.559,
"build/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.o": 0.464,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135888.o": 0.082,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135A4C.o": 0.083,
"build/src/ov_SC04_011/ov_SC04_011_jr_80135D20.o": 0.171,
"build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.22,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.o": 0.174,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.117,
"build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.111,
"build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.267,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.118,
"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.246,
"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.134,
"build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.11,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.108,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.139,
"build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.474,
"build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.299,
"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.142,
"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.242,
"build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.105,
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.135,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.106,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.14,
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.574,
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.083,
"build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.078
},
"ok": true,
"seconds": 2.1
"seconds": 2.8
}
.run/P36/delever/ledger.jsonl
+50
View File
File diff suppressed because one or more lines are too long
.run/P36/gte/canonical.json
+1 -1
View File
@@ -1,5 +1,5 @@
{
"generated": "2026-10-02 18:23",
"generated": "2026-10-02 18:31",
"canonical": {
"08008ce80c008de810008ee8|0|1": {
"name": "gte_stsxy3_f3",
.run/P36/gte/sig_cache.json
+13 -1
View File
@@ -138,5 +138,17 @@
"mfc2 $12, $9\nmfc2 $13, $10\nmfc2 $14, $11\nsh $12, 0($4)\nsh $13, 2($4)\nsh $14, 4($4)": "00480c4800500d4800580e4800008ca402008da404008ea4",
"swc2 $19, 0($4)": "000093e8",
"mfc2 $12, $19\nnop\nsra $12, $12, 2\nsw $12, 0($4)\n": "00980c480000000083600c0000008cac",
"lwc2 $9, 0($4)\nlwc2 $10, 4($4)\nlwc2 $11, 8($4)\nnop\nnop\nsqr 1\n": "000089c804008ac808008bc800000000000000002804a84a"
"lwc2 $9, 0($4)\nlwc2 $10, 4($4)\nlwc2 $11, 8($4)\nnop\nnop\nsqr 1\n": "000089c804008ac808008bc800000000000000002804a84a",
"mtc2 $0, $8\n\nlwc2 $6, 0($4)\n\nlwc2 $28, 0($5)": "00408048000086c80000bcc8",
"move $12, $4\n\nswc2 $29, 0($12)": "2160800000009de9",
"nop\n\tnop\n\tdpcl": "00000000000000002900684a",
"lwc2 $9, 0($4)\n\tlwc2 $10, 4($4)\n\tlwc2 $11, 8($4)": "000089c804008ac808008bc8",
"nop\n\tnop\n\tsqr 0": "00000000000000002804a04a",
".set\tnoreorder\nlw $12, 0($4)\nlw $13, 4($4)\nctc2 $12, $0\nctc2 $13, $1\nlw $12, 8($4)\nlw $13, 12($4)\nlw $14, 16($4)\nctc2 $12, $2\nctc2 $13, $3\nctc2 $14, $4\nlwc2 $0, 0($5)\nlwc2 $1, 4($5)\nnop\nnop\nmvmva 1, 0, 0, 3, 0\nswc2 $25, 0($6)\nswc2 $26, 4($6)\nswc2 $27, 8($6)\n.set\treorder\n": "00008c8c04008d8c0000cc480008cd4808008c8c0c008d8c10008e8c0010cc480018cd480020ce480000a0c80400a1c800000000000000001260484a0000d9e80400dae80800dbe8",
"mtc2 $0, $8\n\tlwc2 $6, 0($4)\n\tlwc2 $28, 0($5)": "00408048000086c80000bcc8",
"move $12, $4\n\tswc2 $29, 0($12)": "2160800000009de9",
"lwc2 $0, 0($4)\n\tlwc2 $1, 4($4)": "000080c8040081c8",
"nop\n\tnop\n\trtps": "00000000000000000100184a",
"cfc2 $12, $31\n\tnop\n\tsw $12, 0($4)": "00f84c480000000000008cac",
"lw $2, 0($4);lw $3, 4($4);ctc2 $2, $0;ctc2 $3, $1;lw $2, 8($4);lw $3, 12($4);lw $24, 16($4);ctc2 $2, $2;ctc2 $3, $3;ctc2 $24, $4;lw $2, 20($4);lw $3, 24($4);ctc2 $2, $5;lw $24, 28($4);ctc2 $3, $6;ctc2 $24, $7": "0000828c0400838c0000c2480008c3480800828c0c00838c1000988c0010c2480018c3480020d8481400828c1800838c0028c2481c00988c0030c3480038d848"
}
src/800.c
+10 -347
View File
@@ -42,71 +42,7 @@ void func_800123F0(s32 param_1, s32 param_2)
*(s16 *)((s32)matrix + 0x0E) = 0;
*(s16 *)((s32)matrix + 0x10) = 0x1000;
__asm__ __volatile__ (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 16;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 18;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 20;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2)"
:
: "r"(s1)
: "$12", "$13", "$14", "$2"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_8b56(s1);
func_8001282C(s1);
}
@@ -142,71 +78,7 @@ void func_80012558(s32 param_1, s32 param_2)
*(s16 *)((s32)matrix + 0x0E) = 0;
*(s16 *)((s32)matrix + 0x10) = cos_val;
__asm__ __volatile__ (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 16;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 18;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 20;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2)"
:
: "r"(s1)
: "$12", "$13", "$14", "$2"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_8b56(s1);
func_8001282C(s1);
}
@@ -242,71 +114,7 @@ void func_800126C4(s32 param_1, s32 param_2)
*(s16 *)((s32)matrix + 0x0E) = sin_val;
*(s16 *)((s32)matrix + 0x10) = cos_val;
__asm__ __volatile__ (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 16;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 18;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 20;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2)"
:
: "r"(s1)
: "$12", "$13", "$14", "$2"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_8b56(s1);
func_8001282C(s1);
}
@@ -762,8 +570,8 @@ s32 func_80013478(void) {
diff[1] = a0[3] - a1[1];
diff[2] = a0[5] - a1[2];
__asm__ volatile("lwc2 $9, 0(%0)\n\tlwc2 $10, 4(%0)\n\tlwc2 $11, 8(%0)" : : "r"(diff));
__asm__ volatile("nop\n\tnop\n\tsqr 0");
gte_ldlvl(diff);
gte_sqr_a07d();
gte_stlvnl(result);
return result[0] + result[1] + result[2];
@@ -800,70 +608,7 @@ void func_800134FC(s16 param_1, s32 param_2, s32 param_3)
*(s16 *)((s32)m1 + 0x0A) = v1;
*(s16 *)((s32)m1 + 0x0C) = 0;
__asm__ __volatile__ (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"lhu $12, 0(%1);"
"lhu $13, 6(%1);"
"lhu $14, 12(%1);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 50;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, $sp, 18;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 52;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, $sp, 20;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2)"
:
: "r"(m0), "r"(m1)
: "$12", "$13", "$14"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_3eb0(m0, m1);
func_8001282C(m0);
func_800484EC(m0, param_2, param_3);
@@ -1242,28 +987,7 @@ void func_80014094(s32 *arg0, void *arg1) {
void func_800140B8(s32 a0, s32 a1, s32 a2)
{
__asm__ __volatile__(
".set\tnoreorder\n"
"lw $12, 0($4)\n"
"lw $13, 4($4)\n"
"ctc2 $12, $0\n"
"ctc2 $13, $1\n"
"lw $12, 8($4)\n"
"lw $13, 12($4)\n"
"lw $14, 16($4)\n"
"ctc2 $12, $2\n"
"ctc2 $13, $3\n"
"ctc2 $14, $4\n"
"lwc2 $0, 0($5)\n"
"lwc2 $1, 4($5)\n"
"nop\n"
"nop\n"
"mvmva 1, 0, 0, 3, 0\n"
"swc2 $25, 0($6)\n"
"swc2 $26, 4($6)\n"
"swc2 $27, 8($6)\n"
".set\treorder\n"
: : : "$12", "$13", "$14", "memory");
gte_lwx2_ctc2x2_lwx3_ctc2x3_fc24();
*(s32 *)a2 <<= 16;
*(s32 *)(a2 + 4) <<= 16;
*(s32 *)(a2 + 8) <<= 16;
@@ -4215,7 +3939,7 @@ void func_8001751C(s32 *arg0, s32 arg1)
d1 = p + 20;
d2 = p + 32;
gte_stsxy3(d0, d1, d2);
__asm__ volatile ("swc2 $8, 0( %0 )" : : "r"(&sz) : "memory");
gte_stdp(&sz);
gte_stflg(&flag);
gte_stszotz(&otz);
} else {
@@ -9510,68 +9234,7 @@ void func_8001D70C(s32 param_1)
sc[7] = 0;
sc[8] = 0x1000;
__asm__ volatile (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 0x30;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 0x32;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, $sp, 0x12;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 0x34;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, $sp, 0x14;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
: : "r"((s32)matrix) : "$12", "$13", "$14", "$2", "memory");
gte_lwx2_ctc2x2_lwx3_ctc2x3_b751((s32)matrix);
*(s32 *)((u8 *)matrix + 0x14) = *(s16 *)(param_1 + 8);
*(s32 *)((u8 *)matrix + 0x18) = *(s16 *)(param_1 + 10);
@@ -14105,7 +13768,7 @@ void func_80023BF0(s32 arg0)
gte_ldv0(&v);
gte_rtps();
gte_stsxy(&xy);
__asm__ volatile("swc2 $8, 0(%0)" : : "r"(&sxy2) : "memory");
gte_stdp(&sxy2);
gte_stflg(&mac0);
gte_stszotz(&z);
if (z <= 0) {
src/md_MAIN_031/md_MAIN_031.c
-21
View File
@@ -344,31 +344,10 @@ void func_800CB5C8(s32 arg0, s32 arg1) {
/* GTE VARIANT `gte_SetRotMatrix_m`: memory beyond Sony's `gte_SetRotMatrix` — a scheduling steer, its uses are marked (P36 T5) */
#define gte_SetRotMatrix_m(p) __asm__ __volatile__( \
"lw $12, 0(%0)\n" \
"lw $13, 4(%0)\n" \
"ctc2 $12, $0\n" \
"ctc2 $13, $1\n" \
"lw $12, 8(%0)\n" \
"lw $13, 12(%0)\n" \
"lw $14, 16(%0)\n" \
"ctc2 $12, $2\n" \
"ctc2 $13, $3\n" \
"ctc2 $14, $4\n" \
: : "r"(p) : "$12", "$13", "$14", "memory")
/* GTE VARIANT `gte_ldv0_m`: memory beyond Sony's `gte_ldv0` — a scheduling steer, its uses are marked (P36 T5) */
#define gte_ldv0_m(p) __asm__ __volatile__( \
"lwc2 $0, 0(%0)\n" \
"lwc2 $1, 4(%0)\n" \
: : "r"(p) : "memory")
/* GTE VARIANT `gte_rtv0_m`: memory beyond Sony's `gte_rtv0` — a scheduling steer, its uses are marked (P36 T5) */
#define gte_rtv0_m() __asm__ __volatile__( \
"nop\n" \
"nop\n" \
"mvmva 1, 0, 0, 3, 0\n" \
: : : "memory")
extern s32 func_80017DC4(void *a0, void *a1);
src/ov_MAIN_012/ov_MAIN_012_jr_8013C98C.c
+2 -2
View File
@@ -1442,9 +1442,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_000/ov_SC01_000_jr_8013C98C.c
+2 -2
View File
@@ -1505,9 +1505,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_001/ov_SC01_001_jr_8013C98C.c
+2 -2
View File
@@ -1492,9 +1492,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_004/ov_SC01_004_jr_8013C98C.c
+2 -2
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@@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_005/ov_SC01_005_jr_8013C98C.c
+2 -2
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@@ -1492,9 +1492,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_008/ov_SC01_008_jr_8013C98C.c
+2 -2
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@@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_009/ov_SC01_009_jr_8013C98C.c
+2 -2
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@@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_074/ov_SC01_074_jr_8013C98C.c
+2 -2
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@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_077/ov_SC01_077.c
+2 -2
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@@ -715,9 +715,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_080/ov_SC01_080_jr_8013C98C.c
+2 -2
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@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC01_084/ov_SC01_084_jr_8013C98C.c
+2 -2
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@@ -1496,9 +1496,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_000/ov_SC02_000_jr_8013C98C.c
+2 -2
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@@ -1493,9 +1493,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_004/ov_SC02_004_jr_8013C98C.c
+2 -2
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@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_005/ov_SC02_005_jr_8013C98C.c
+2 -2
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@@ -1496,9 +1496,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_011/ov_SC02_011_jr_8013C98C.c
+2 -2
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@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_015/ov_SC02_015_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_016/ov_SC02_016_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_017/ov_SC02_017_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_021/ov_SC02_021_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_026/ov_SC02_026_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_026/ov_SC02_026_jr_8017C180.c
+4 -33
View File
@@ -2683,13 +2683,6 @@ extern void func_8017C0E4(void *a0);
#define gte_stsxy3_f4(r0) __asm__ volatile ( \
"swc2 $12, 8( %0 );" \
"swc2 $13, 12( %0 );" \
"swc2 $14, 16( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
@@ -3083,19 +3076,8 @@ int func_8017D948(short *a0)
data[0] = D_80126CAC - a0[0];
data[1] = 0;
data[2] = D_80126CB0 - a0[2];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return (data[0] + data[1] + data[2]) - 0x10001U <= 0x8FFE;
}
@@ -3108,19 +3090,8 @@ int func_8017D9D8(short *a0) {
data[0] = D_80126CAC - a0[3];
data[1] = 0;
data[2] = D_80126CB0 - a0[7];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return (data[0] + data[1] + data[2]) > 0x8FFFF;
}
src/ov_SC02_027/ov_SC02_027_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_028/ov_SC02_028_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_031/ov_SC02_031_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_035/ov_SC02_035_jr_8013C98C.c
+2 -2
View File
@@ -1494,9 +1494,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_037/ov_SC02_037_jr_8013C98C.c
+2 -2
View File
@@ -1440,9 +1440,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_039/ov_SC02_039_jr_8013C98C.c
+2 -2
View File
@@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC02_039/ov_SC02_039_jr_8017BEBC.c
+1 -72
View File
@@ -2693,13 +2693,6 @@ extern void func_8017BEB4(void);
#define gte_stsxy3_f4(r0) __asm__ volatile ( \
"swc2 $12, 8( %0 );" \
"swc2 $13, 12( %0 );" \
"swc2 $14, 16( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
@@ -3021,71 +3014,7 @@ void func_8017D7D0(s32 param_1, s32 *param_2)
*(short *)((s32)matrix_stack + 0x0E) = 0;
*(short *)((s32)matrix_stack + 0x10) = cos_val;
__asm__ volatile (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 0x10;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 0x12;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 0x2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 0x14;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu %0, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0)"
: "=r"(s1)
: "0"(s1)
: "$12", "$13", "$14", "$2"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1);
}
src/ov_SC02_041/ov_SC02_041_jr_8013C98C.c
+2 -2
View File
@@ -1491,9 +1491,9 @@ void func_8013D9B0(int param_1)
r = pix & 0x1f;
g = pix & 0x3e0;
b = pix & 0x7c00;
__asm__ __volatile__("mtc2 $0, $8\n\tlwc2 $6, 0(%0)\n\tlwc2 $28, 0(%1)" :: "r"(fc), "r"(&gte[1]) : "memory"); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_mtc2_lwc2x2_1fc7(fc, &gte[1]); // !FAKE: asm gte_ldIR0z+gte_ldrgb+gte_ldIRGB — the header spells these as three volatile asms (sched.c:1957 barriers), so the IRGB address lands after lwc2 $6, and a pointer set before mtc2 has life 4 and is hoisted (loop.c:1631); one asm keeps its addiu adjacent (life 1) and before mtc2 (P36 S103 c47 minimum-lever)
gte_dpcl();
__asm__ __volatile__("move $12, %0\n\tswc2 $29, 0($12)" :: "r"(&gte[2]) : "$12", "memory"); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
gte_move_swc2_e610(&gte[2]); // !FAKE: asm gte_stORGB — the header macro does not write $12 itself; the target's move t4,v0 needs it (S103 c17; the header respelling is Drew's T5 call) (P36 S103 c47 minimum-lever)
out = gte[2];
tr = out & 0x1f;
tg = out & 0x3e0;
src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c
+3 -27
View File
@@ -5215,39 +5215,15 @@ void func_8017FB04(s32 s1)
s2 = s1 + 0xFC;
v0 = s3 + 0x18;
__asm__ volatile(
"lw %0, 0(%3);"
"lw %1, 4(%3);"
"ctc2 %0, $0;"
"ctc2 %1, $1;"
"lw %0, 8(%3);"
"lw %1, 12(%3);"
"lw %2, 16(%3);"
"ctc2 %0, $2;"
"ctc2 %1, $3;"
"ctc2 %2, $4;"
"lw %0, 20(%3);"
"lw %1, 24(%3);"
"ctc2 %0, $5;"
"lw %2, 28(%3);"
"ctc2 %1, $6;"
"ctc2 %2, $7"
: "=&r"(t4), "=&r"(t5), "=&r"(t6)
: "r"(v0));
gte_lwx2_ctc2x2_lwx3_ctc2x3_42e3(t4, t5, t6, v0);
__asm__ volatile(
"lwc2 $0, 0(%0);"
"lwc2 $1, 4(%0);"
"nop;"
"nop;"
"rtps" : : "r"(s2) );
gte_ldv0(s2); gte_rtps();
a0 = (s32)&stack[0];
gte_stsxy(a0);
v0 = (s32)&stack[2];
__asm__ volatile("cfc2 %0, $31; nop; sw %0, 0(%1)"
: "=&r"(t4) : "r"(v0) : "memory");
gte_cfc2_sw_4531(t4, v0);
v1 = 0x80000000;
if ((s32)stack[2] < 0) {
src/ov_SC04_006/ov_SC04_006_jr_8017BEBC.c
+3 -85
View File
@@ -2679,13 +2679,6 @@ extern void func_8017BEB4(void);
#define gte_stsxy3_f4(r0) __asm__ volatile ( \
"swc2 $12, 8( %0 );" \
"swc2 $13, 12( %0 );" \
"swc2 $14, 16( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
@@ -3320,71 +3313,7 @@ void func_8017DBC8(s32 param_1, s32 *param_2)
*(short *)((s32)matrix_stack + 0x0E) = 0;
*(short *)((s32)matrix_stack + 0x10) = cos_val;
__asm__ volatile (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 0x10;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 0x12;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 0x2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 0x14;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu %0, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0)"
: "=r"(s1)
: "0"(s1)
: "$12", "$13", "$14", "$2"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1);
}
@@ -4471,19 +4400,8 @@ int func_8017F43C(short *a0) {
data[0] = a0[3] - a0[68];
data[1] = 0;
data[2] = a0[7] - a0[70];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return (data[0] + data[2]) <= 0x18FFFF;
}
src/ov_SC05_001/ov_SC05_001_jr_8017BEBC.c
+5 -91
View File
@@ -4420,19 +4420,8 @@ int func_8017F150(short *a0) {
data[0] = D_80126CAC - a0[0];
data[1] = 0;
data[2] = D_80126CB0 - a0[2];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return (data[0] + data[1] + data[2]) - 0x90001U < 0x18FFF;
}
@@ -4447,19 +4436,8 @@ int func_8017F1E4(short *a0) {
data[0] = D_80126CAC - a0[3];
data[1] = 0;
data[2] = D_80126CB0 - a0[7];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return 0x143FFF < (data[0] + data[1] + data[2]);
}
@@ -5838,71 +5816,7 @@ void func_80180FFC(s32 param_1, s32 *param_2)
*(short *)((s32)matrix_stack + 0x0E) = 0;
*(short *)((s32)matrix_stack + 0x10) = cos_val;
__asm__ volatile (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 0x10;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 0x12;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 0x2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 0x14;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu %0, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0)"
: "=r"(s1)
: "0"(s1)
: "$12", "$13", "$14", "$2"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1);
}
src/ov_SC05_005/ov_SC05_005_jr_8017D898.c
+2 -85
View File
@@ -2698,13 +2698,6 @@ extern void func_8017D824(void *param_1);
#define gte_stsxy3_f4(r0) __asm__ volatile ( \
"swc2 $12, 8( %0 );" \
"swc2 $13, 12( %0 );" \
"swc2 $14, 16( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
@@ -3238,71 +3231,7 @@ void func_8017F2E8(s32 param_1, s32 *param_2)
*(short *)((s32)matrix_stack + 0x0E) = 0;
*(short *)((s32)matrix_stack + 0x10) = cos_val;
__asm__ volatile (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 0x10;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 0x12;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 0x2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 0x14;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu %0, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0)"
: "=r"(s1)
: "0"(s1)
: "$12", "$13", "$14", "$2"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1);
}
@@ -4850,19 +4779,7 @@ s32 func_80181828(void *arg0) {
v.vz = (s16)D_80126B66 - raw[2];
/* gte SQR on the XZ difference vector (in place) */
__asm__ volatile (
"lwc2 $9, 0( %0 );"
"lwc2 $10, 4( %0 );"
"lwc2 $11, 8( %0 );"
"nop;"
"nop;"
"sqr 0;"
"swc2 $25, 0( %0 );"
"swc2 $26, 4( %0 );"
"swc2 $27, 8( %0 )"
:
: "r"(&v)
: "$9", "$10", "$11", "memory");
gte_lwc2x3_sqr_swc2x3_c9fc(&v);
if (r * r <= v.vx + v.vz) {
return 0;
src/ov_SC06_000/ov_SC06_000_jr_8017AE2C.c
+7 -85
View File
@@ -7647,13 +7647,9 @@ void func_80182E38(int param_1)
}
*(short *)(sv + 4) = v0;
func_8004978C((s16 *)(CAST_ALIAS(int, param_1, 0x20) + 0x10), mat);
__asm__ __volatile__(
"lw $12, 0(%0)\n" "lw $13, 4(%0)\n"
"ctc2 $12, $0\n" "ctc2 $13, $1\n"
"lw $12, 8(%0)\n" "lw $13, 12(%0)\n" "lw $14, 16(%0)\n"
"ctc2 $12, $2\n" "ctc2 $13, $3\n" "ctc2 $14, $4\n" : : "r"(mat) : "$12", "$13", "$14" );
__asm__ __volatile__("lwc2 $0, 0(%0)\n" "lwc2 $1, 4(%0)\n" : : "r"(sv) );
__asm__ __volatile__("nop\n" "nop\n" "mvmva 1, 0, 0, 3, 0\n" );
gte_SetRotMatrix(mat);
gte_ldv0(sv);
gte_rtv0();
gte_stsv(sv);
((Unkstruct_800B5CB8 *)param_1)->unk6 = *(unsigned short *)(((Unkstruct_800B5CB8 *)param_1)->unk64 + 6) + *(unsigned short *)(sv + 0);
((Unkstruct_800B5CB8 *)param_1)->unkA = *(unsigned short *)(((Unkstruct_800B5CB8 *)param_1)->unk64 + 10) + *(unsigned short *)(sv + 2);
@@ -8156,20 +8152,10 @@ void func_80183C9C(void *a0)
func_8004978C((s16 *)(((Unkstruct_800B5CB8 *)self)->unk20 + 0x10), &mat);
__asm__ __volatile__(
"lw $12, 0(%0)\n"
"lw $13, 4(%0)\n"
"ctc2 $12, $0\n"
"ctc2 $13, $1\n"
"lw $12, 8(%0)\n"
"lw $13, 12(%0)\n"
"lw $14, 16(%0)\n"
"ctc2 $12, $2\n"
"ctc2 $13, $3\n"
"ctc2 $14, $4\n" : : "r"(&mat) : "$12", "$13", "$14" );
gte_SetRotMatrix(&mat);
__asm__ __volatile__("lwc2 $0, 0(%0)\nlwc2 $1, 4(%0)" : : "r"(&D_8018C7BC[((Unkstruct_800B5CB8 *)self)->unk70 * 4]) );
__asm__ __volatile__("nop\nnop\nmvmva 1, 0, 0, 3, 0" );
gte_ldv0(&D_8018C7BC[((Unkstruct_800B5CB8 *)self)->unk70 * 4]);
gte_rtv0();
gte_stsv(res);
((Unkstruct_800B5CB8 *)self)->unk6 = *(u16 *)(((Unkstruct_800B5CB8 *)self)->unk64 + 0x6) + res[0];
@@ -9722,71 +9708,7 @@ void func_80185F48(s32 param_1, s32 *param_2)
*(short *)((s32)matrix_stack + 0x0E) = 0;
*(short *)((s32)matrix_stack + 0x10) = cos_val;
__asm__ volatile (
"lw $12, 0(%0);"
"lw $13, 4(%0);"
"ctc2 $12, $0;"
"ctc2 $13, $1;"
"lw $12, 8(%0);"
"lw $13, 12(%0);"
"lw $14, 16(%0);"
"ctc2 $12, $2;"
"ctc2 $13, $3;"
"ctc2 $14, $4;"
"addiu $2, $sp, 0x10;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0);"
"addiu $2, $sp, 0x12;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu $2, %0, 0x2;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0($2);"
"sh $13, 6($2);"
"sh $14, 12($2);"
"addiu $2, $sp, 0x14;"
"lhu $12, 0($2);"
"lhu $13, 6($2);"
"lhu $14, 12($2);"
"mtc2 $12, $9;"
"mtc2 $13, $10;"
"mtc2 $14, $11;"
"nop;"
"nop;"
"mvmva 1, 0, 3, 3, 0;"
"addiu %0, %0, 4;"
"mfc2 $12, $9;"
"mfc2 $13, $10;"
"mfc2 $14, $11;"
"sh $12, 0(%0);"
"sh $13, 6(%0);"
"sh $14, 12(%0)"
: "=r"(s1)
: "0"(s1)
: "$12", "$13", "$14", "$2"
);
gte_lwx2_ctc2x2_lwx3_ctc2x3_2c4d(s1, s1);
}
src/ov_SC06_018/ov_SC06_018_jr_8017C24C.c
+4 -33
View File
@@ -2680,13 +2680,6 @@ extern void func_8017C090(void *a0);
#define gte_stsxy3_f4(r0) __asm__ volatile ( \
"swc2 $12, 8( %0 );" \
"swc2 $13, 12( %0 );" \
"swc2 $14, 16( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
@@ -2966,19 +2959,8 @@ int func_8017D7E0(short *a0) {
data[0] = D_80126CAC - a0[0];
data[1] = 0;
data[2] = D_80126CB0 - a0[2];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return (data[0] + data[1] + data[2]) - 0x90001U < 0x18FFF;
}
@@ -2991,19 +2973,8 @@ int func_8017D874(short *a0) {
data[0] = D_80126CAC - a0[3];
data[1] = 0;
data[2] = D_80126CB0 - a0[7];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return data[0] + data[1] + data[2] > 0xFFFFF;
}
src/ov_SC06_020/ov_SC06_020_jr_8017C24C.c
+2 -23
View File
@@ -2680,13 +2680,6 @@ extern void func_8017C090(void *a0);
#define gte_stsxy3_f4(r0) __asm__ volatile ( \
"swc2 $12, 8( %0 );" \
"swc2 $13, 12( %0 );" \
"swc2 $14, 16( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
@@ -3083,14 +3076,7 @@ s32 func_8017DA50(s16 *arg) {
s32 u = arg[2];
sp[2] = t - u;
}
__asm__ __volatile__(
"lwc2 $9, 0(%0)\n"
"lwc2 $10, 4(%0)\n"
"lwc2 $11, 8(%0)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : "r"(sp) : "$9", "$10", "$11", "memory");
gte_lwc2x3_sqr_e416(sp);
gte_stlvnl(sp);
return !(0x14FFE < sp[0] + sp[1] + sp[2] + 0xFFF9BFFF);
@@ -3116,14 +3102,7 @@ s32 func_8017DAE4(s16 *arg) {
s32 u = arg[7];
sp[2] = t - u;
}
__asm__ __volatile__(
"lwc2 $9, 0(%0)\n"
"lwc2 $10, 4(%0)\n"
"lwc2 $11, 8(%0)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : "r"(sp) : "$9", "$10", "$11", "memory");
gte_lwc2x3_sqr_e416(sp);
gte_stlvnl(sp);
return sp[0] + sp[1] + sp[2] > 0xC3FFF;
src/ov_SC06_032/ov_SC06_032_jr_8017C24C.c
+2 -20
View File
@@ -2676,13 +2676,6 @@ extern void func_8017C090(void *a0);
#define gte_stsxy3_f4(r0) __asm__ volatile ( \
"swc2 $12, 8( %0 );" \
"swc2 $13, 12( %0 );" \
"swc2 $14, 16( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
@@ -2955,19 +2948,8 @@ int func_8017D77C(short *a0) {
data[0] = D_80126CAC - a0[0];
data[1] = 0;
data[2] = D_80126CB0 - a0[2];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return (data[0] + data[1] + data[2]) - 0x64001U <= 0x14FFE;
}
src/ov_SC06_033/ov_SC06_033_jr_8017C24C.c
+4 -33
View File
@@ -2685,13 +2685,6 @@ extern void func_8017C090(void *a0);
#define gte_stsxy3_f4(r0) __asm__ volatile ( \
"swc2 $12, 8( %0 );" \
"swc2 $13, 12( %0 );" \
"swc2 $14, 16( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
@@ -3174,19 +3167,8 @@ int func_8017DC30(short *a0) {
data[0] = D_80126CAC - a0[0];
data[1] = 0;
data[2] = D_80126CB0 - a0[2];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return (data[0] + data[1] + data[2]) + 0xFFF9BFFFU <= 0x14FFE;
}
@@ -3199,19 +3181,8 @@ int func_8017DCC4(s16 *a0) {
data[0] = D_80126CAC - a0[3];
data[1] = 0;
data[2] = D_80126CB0 - a0[7];
__asm__ __volatile__(
"lwc2 $9, 0($sp)\n"
"lwc2 $10, 4($sp)\n"
"lwc2 $11, 8($sp)\n"
"nop\n"
"nop\n"
"sqr 0\n"
: : : "$9", "$10", "$11", "memory");
__asm__ __volatile__(
"swc2 $25, 0($sp)\n"
"swc2 $26, 4($sp)\n"
"swc2 $27, 8($sp)\n"
: : : "memory");
gte_lwc2x3_sqr_6a00();
gte_swc2x3_66ca();
return 0xC3FFF < data[0] + data[1] + data[2];
}
tools/gte_consolidate.py
+14 -4
View File
@@ -318,7 +318,7 @@ def inventory(jobs=12, quiet=False):
sg = signature(inner)
except Exception as ex: # noqa: BLE001
sg = dict(bytes=f"ERROR: {ex}"[:100], ok=False, nout=0, nin=0, clob=[], tmpl="", ins=[], outs=[])
direct.append(dict(tu=tu, line=s["line"], col=s["col"], fn=s.get("fn"), inner=inner, sig=sg, marked=s.get("marked", False),
direct.append(dict(tu=tu, line=s["line"], col=s["col"], fn=s.get("fn"), inner=inner, sig=sg, marked=s.get("marked", False), kind=s["kind"],
kw=re.sub(r"\s+", " ", m[pos:o]).strip()))
_save_cache()
inv = dict(generated=time.strftime("%Y-%m-%d %H:%M"), definitions=defs, direct=direct, uses=dict(uses))
@@ -848,8 +848,9 @@ def direct_rewrite(s, canon):
return "lever", f"{names[0]}+{variant_name(names[1], t2['clob'], vclob)}", extra or sorted(set(clob) - set(sg["clob"]))
def file_edits(tu, raw, p, canon, label):
"""[(start, end, repl)] + the record (per definition / use / direct statement) for one file's consolidation."""
def file_edits(tu, raw, p, canon, label, keep_levers=False):
"""[(start, end, repl)] + the record (per definition / use / direct statement) for one file's consolidation.
keep_levers (T7.1.c3): a direct lever (census gte-lever, or a statement only a lever variant matches) keeps its text and marker (T8's)."""
m = dl.same_len_mask(raw)
ls = dl.line_starts(raw)
edits, rec = [], dict(deleted=0, renamed_defs=0, use_renames=0, direct_calls=0, direct_levers=0, direct_none=0, marked=0, defs=[], direct=[])
@@ -924,6 +925,9 @@ def file_edits(tu, raw, p, canon, label):
rec["direct"].append(dict(line=s["line"], action="refused", why="statement not found at the census position"))
continue
how, text, name = direct_rewrite(s, canon)
if keep_levers and (how == "lever" or s.get("kind") == lc.GTE_LEVER_KIND):
rec["direct"].append(dict(line=s["line"], action="lever-kept", how=how))
continue
eol = raw.find("\n", e)
eol = len(raw) if eol < 0 else eol
tail = raw[e:eol].strip(" \t\r;")
@@ -1038,7 +1042,7 @@ def apply_batch(a):
except (Refuse, dl.Refuse) as ex:
d["trial"] = f"REFUSED {ex}"
try:
edits, rec = file_edits(tu, raw, plan_tu, canon, a.label)
edits, rec = file_edits(tu, raw, plan_tu, canon, a.label, keep_levers=a.keep_levers)
except Refuse as ex:
row.update(verdict="REFUSED", why=str(ex))
log(f" {tu}: REFUSED {ex}")
@@ -1497,6 +1501,11 @@ def selftest():
outl = dl.apply_edits(fxl, file_edits("fl.c", fxl, pl, canon2, "self")[0])
if not re.search(r"\n gte_ldv0_m\(v\); // !FAKE: gte via gte_ldv0_m — clobbers memory .*3\.39 T7\.1 self.*\n\}", outl) or "old" in outl:
fail(f"direct lever respelled to its header variant, marked once:\n{outl}")
if dl.apply_edits(fxl, file_edits("fl.c", fxl, pl, canon2, "self", keep_levers=True)[0]) != fxl:
fail("--keep-levers: a direct lever must keep its text and marker")
pk = dict(defs=[], direct=[dict(pl["direct"][0], kind=lc.GTE_LEVER_KIND)], renames={})
if dl.apply_edits(fxl, file_edits("fl.c", fxl, pk, canon2, "self", keep_levers=True)[0]) != fxl:
fail("--keep-levers: a census gte-lever statement must keep its text")
print(f"gte_consolidate --selftest: {'OK' if ok else 'FAIL'} — signatures rtps={s1['bytes'][16:24]} ldv0={s4['bytes'][:16]}; table {len(canon2['canonical'])} canonical / {len(canon2['variants'])} variant; fixture edits {len(edits)}")
return ok
@@ -1514,6 +1523,7 @@ def main():
ap.add_argument("--label", default=None)
ap.add_argument("--only", nargs="*", default=None)
ap.add_argument("--rejudge", action="store_true")
ap.add_argument("--keep-levers", action="store_true", help="--apply: leave direct lever statements (census gte-lever) as they are (T8 owns them)")
ap.add_argument("--dirty-ok", action="store_true", help="--remark on a tree the scrub just modified (one fleet run for both)")
ap.add_argument("-j", "--jobs", type=int, default=12)
a = ap.parse_args()