mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-09-27 14:02:04 -04:00
phase-36: S104 s104_e13 — func_80185574 banked at 0 through the whole-object gate + propagated — 3 pins → 0: the parameter copy deleted, one value per variable (sched.c:2469-2547 → the three-quantity order, local-alloc.c:1486-1500)
This commit is contained in:
Drew T
@@ -0,0 +1,50 @@
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void func_801842E0(void) {
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s32 t;
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s32 y;
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t = D_800B99DA;
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if (t != D_8018EF88) {
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y = (s16)D_80126B62;
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D_8018EF88 = t;
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if (y >= -0x7FF) {
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t = D_8018EF84;
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} else if (y < -0xC00) {
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t = D_8018EF84;
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} else {
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SV3_8012CC88 sp10;
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SV3_8012CC88 sp18;
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sp10.vx = D_80126B5E;
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sp10.vy = 0;
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sp10.vz = D_80126B66;
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sp18.vx = 0x11;
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sp18.vz = -0x3AA;
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sp18.vy = 0;
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t = func_800132BC((s32)&sp10, (s32)&sp18);
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}
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if (t >= D_8018EF84) {
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func_8002D4C8(4, 0x5E5);
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} else {
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t = D_8018EF84 - t - 0x10000;
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if (t < 0) {
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t = -t;
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}
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t = t * 127 / D_8018EF84;
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if (t <= 0) {
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t = 0;
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} else if (t >= 0x80) {
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t = 0x7F;
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}
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if (D_801270C8 != 0) {
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t /= 2;
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}
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func_8002D4C8(0x5E5, (u16)(t | 0x1000));
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}
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}
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}
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@@ -0,0 +1,57 @@
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# func_801842E0 — e13 (P36 T7 S104) — score 34 (sweep best 20) -> 0, ZERO levers (was: NEEDED pins `$3`, `$5` + a NEEDED `launder`)
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(a) Residual: 86/86 insns, two defects. (1) A register permutation over the whole function: the main value `t`
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(the `D_800B99DA` stamp, then the call result / `D_8018EF84`, then the volume) sits in `a1` instead of `v1` (x25) and the
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second variable (`(s16)D_80126B62`, then `D_8018EF84`) in `v1` instead of `a0` (x13). (2) ORDER at the tail: the target
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emits `li a0,1509; ori a1,v1,0x1000; andi a1,a1,0xffff; jal`, the lever-free text puts `li a0,1509` after the `ori`.
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(b) Pass/decision (dump-verified: `scratch/dumps_b0` (body_free, 34), `dumps_f1` (b0 + move 1, 2), `dumps_f3` (b0 + both, 0);
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`tools/alloc_table.py`):
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1. global.c preferences. `t = a0 - t; t -= 0x10000;` sets `t` from `(minus a0 t)` — `set_preference`
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(global.c:1535; for a non-copy the source is `XEXP (src, 0)` = `a0`, a global pseudo, so no hard-register
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preference) — then from `t + K` (itself). The only hard preference `t` (r72) gets is `a1`, from `a1p = t | 0x1000`
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(a1p is local-allocated into `a1`): b0 table "r72 prefers a1" -> `find_reg` gives `a1`. Written as ONE expression
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`t = a0 - t - 0x10000;`, expand makes the inner difference a fresh block-local temp (f1 r89, local-alloc puts it in
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`v1`) and `t = r89 + K` adds the preference `v1`: f1 "r72 prefers v1,a1". `find_reg`'s preference scan runs from hard
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reg 0 upward (global.c:1039-1068), so `v1` (3) wins over `a1` (5). With `t` in `v1` for its whole life, the other
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global (r73, `a0`) now conflicts with `v1` (f1 "r73 conflicts v0,v1") and takes `a0` — both halves of the permutation
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close with this one move (34 -> 2). Same channel as e7's func_801831FC (a second preference from a fresh temp).
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2. sched1's birthing boost. `a1p = t | 0x1000; a1p = (u16)a1p;` sets `a1p` twice (`reg_n_sets == 2`), so the `ori`
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is not a birthing insn (`birthing_insn_p`, sched.c:2469-2490) and gets no `adjust_priority` boost
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(sched.c:2507-2547): f1 `.sched` block 17 `ready list at T-3: 187 (1) 182 (1), now 187 182` — the `li a0,1509`
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(187) takes the later slot. With one set (`a1p = t | 0x1000; func_8002D4C8(0x5E5, (u16)a1p);`, or the value
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inline) the `ori` is birthing: f3 `T-3: 183 (1) 179 (7f000001), now 179 183` — the `ori` goes last, `li a0` first
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= the target. The tree's launder on `a0 = 0x5E5` faked the same reordering.
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(c) Moves — the minimum proof (b0 + two edits = `scratch/f3.c`, 0):
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- `t = a0 - t; t -= 0x10000;` -> `t = a0 - t - 0x10000;` (alone: 34 -> 2);
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- the call's `u16` narrowing at the call, not as a second assignment (`a1p = (u16)a1p;` deleted; f4 with only the
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`a0 = 0x5E5` temp removed stays 2, f3 = 0).
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body.c (`scratch/n3.c`, 0) is the readable text built around those two facts: `D_8018EF84` read at each use, the
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`(s16)D_80126B62` in its own `s32 y`, `if (t < 0) t = -t; t = t * 127 / D_8018EF84;` for the hand-expanded
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abs/shift-subtract, `t /= 2` for the hand-rolled `(u32)t >> 31` rounding shift, and
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`func_8002D4C8(0x5E5, (u16)(t | 0x1000));` (the spelling func_801831FC uses for the same call). The nested
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`if (y >= -0x7FF) … else if (y < -0xC00) …` with the duplicated `t = D_8018EF84;` is kept: `||` lets gcc fold the
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two tests into one unsigned range check (n1/A7: 6/10, `addiu 3072; andi 0xffff; sltiu 1025`).
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Ablations from body.c (`scratch/abl/`, all proven on bytes): the split subtraction 33; the hand abs 12;
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`t = t * 127; t = t / D;` 3; the call temps (`a0 = 0x5E5; a1p = …; a1p = (u16)a1p;`) 2; the hand `/2` 1; `||` range 10;
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`s16 y = D_80126B62` 10 (`lhu; sll; sra` — S104 d13's re-extension; `(s16)` into an `s32` gives `lh`). Neutral (0):
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a `lim = D_8018EF84` local, or reusing `y` for it.
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(d) GENERATOR PROPOSAL: when a variable is updated by two consecutive statements (`t = a - t; t -= K;`, `t = f(t); t op= K;`)
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and the residual is a whole-function register swap of that variable, fold them into one expression (`t = a - t - K;`)
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— the inner temp's local-alloc register becomes `t`'s first global preference (global.c:1535, :1039-1068); and when a
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call argument is narrowed by a second assignment (`x = e; x = (u16)x; f(…, x)`) with an ORDER residual on the
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neighbouring argument's `li`, move the cast into the call (one set -> sched1-birthing, sched.c:2469-2490).
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(e) Did not work: n1 (`||` range test) 6; n2/n4 (`s16 y`) 10; every ablation above. The sweep's best (R12 width + R6
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inline, 20) touched neither the two-statement update nor the second set of `a1p`.
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(f) Method: the allocation table's "prefers" column (b0 `a1` only, f1 `v1,a1`) and the `.sched` ready-list lines gave
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both mechanisms in two dumps, but the close came first from writing the natural C (n1 = 6 on the first try) and then
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ablating it — a residual of 34 with a clean permutation looked like a priority problem and was a preference problem.
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The METHOD rows for "a hand-rolled shift as a real division" (e7 func_801831FC) and "narrow at the call" were the
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right ones; neither is needed for the bytes here (f3 keeps the hand shapes), they are readability.
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(g) Structs: no. Both decisions are about scalar locals (a global allocno's copy preference; sched1's set count). The
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body touches only globals and two `SV3_8012CC88` stack vectors, which are already struct-typed.
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@@ -0,0 +1,12 @@
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void func_80185574(s32 arg0) {
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*(s16 *)(arg0 + 0x5C) = 0;
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*(s16 *)(arg0 + 0x98) = 0;
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*(s32 *)(arg0 + 0x1C) = 0;
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if (*(s16 *)(arg0 + 0xAA) == 0) {
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*(s16 *)(arg0 + 0x100) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18);
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*(s32 *)(arg0 + 0xDC) &= ~0x80;
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} else {
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*(s16 *)(arg0 + 0x104) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18);
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*(s32 *)(arg0 + 0xDC) |= 0x80;
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}
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}
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@@ -0,0 +1,60 @@
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# func_80185574 — e13 (P36 T7 S104) — score 16 (sweep best 4) -> 0, ZERO levers (was: NEEDED pins `$0`, `$2`, `$3`)
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(a) Residual: two defects, 22/22 insns. (1) The else arm reads the object through `a0` (the incoming parameter) while
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the target reads it through `a1` in both arms (`move a1,a0` in the prologue, `a0` reused for the `-129` mask).
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(2) A v0/v1 permutation in each arm: target then-arm `lw v1,0x20 / lw v0,0xDC / lhu v1 / and v0,v0,a0`, else-arm
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`lw v0,0x20 / lw v1,0xDC / lhu v0 / ori v1`; lever-free text the opposite in both.
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(b) Pass/decision (dump-verified: `scratch/dumps_b1` (param copy deleted, decompiler temps) vs `scratch/dumps_c3` (body.c)):
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1. `self = arg0 + 0;` makes two pseudos (param r72-equivalent + the copy); cse's canonical-register choice
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(`make_regs_eqv`, cse.c:826-862) leaves the else arm reading the parameter pseudo, which global puts in `a0`.
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One pseudo (use the parameter directly, METHOD d24) lives across the then arm where local-alloc has put the
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mask in `a0`, so it conflicts with `a0` and lands in `a1` in both arms (b1: the `a0` reads are gone, 16 -> REG-only).
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c4/c5 (body.c + `s32 arg0 = a + 0;` / `= a;`): 4 — the copy is part of the joint close.
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2. The decompiler REUSES one variable for the pointer and the halfword read through it (`p = *(s32 *)(self+0x20);
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p = *(u16 *)(p + 0x18);`) and `g` for the flag word and its `|= 0x80` result — each has `reg_n_sets == 2`, so
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sched1's `birthing_insn_p` (sched.c:2469-2490) is false for those loads and `adjust_priority` (sched.c:2507-2547)
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gives them no boost. b1 `.sched` block 1: `ready list at T-5: 40 (2) 30 (7f000001), now 30 40` — the mask `li`
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(insn 30) is launched late, the pointer load (33) first. With one pseudo per value every load is birthing
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(c3 `.sched`: `T-5: 36 (7f000001) 29 (7f000001) … 29 has a greater potential hazard`) and the mask `li` ends up
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FIRST in the block.
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That changes the quantity NUMBERING (birth order) of the block's three local-alloc quantities, and a block with
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exactly three quantities is ordered by the hand-written sort at local-alloc.c:1486-1500, which compares quantity
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NUMBERS 0/1/2, not positions in `qty_order`: b1 {q0 pointer/value (4 refs), q1 flag+and, q2 mask} ends [q0,q1,q2]
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-> pointer `v0`, flag `v1`, mask `a0` (`.lreg`: "Register 77 in 2 / 78 in 3 / 73 in 4"); c3 {q0 mask, q1 pointer
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tied to the u16 value, q2 flag tied to the and result} ends [q2,q1,q0] -> flag `v0`, pointer `v1`, mask `a0`
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(`.lreg`: "78 in 2 / 76 in 3 / 80 in 4") = the target. Same for the else arm (c3: pointer/value r81/r82 in 2,
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flag r83/r84 in 3).
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3. The halfword copy must be written BEFORE the read-modify-write of `+0xDC`: the target does the `lhu` before the
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`sw 220`, and a scalar store through the object vs a load through `*(obj+0x20)` may alias (`true_dependence`,
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sched.c:817-841), so a source order with the RMW first keeps the load after the store (enum `AB__*` 6, `*__AB` 7 COUNT).
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(c) Moves (joint):
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- delete `self = arg0 + 0;` and use the parameter directly (d24);
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- one value per name: the pointer, its halfword, the flag word each its own value — body.c inlines them all
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(`*(s16 *)(arg0 + 0x100) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18); *(s32 *)(arg0 + 0xDC) &= ~0x80;`), the spelling
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the neighbour func_80185494 uses for the same `+0x20 -> +0x18` halfword; the `mask`/`flag` locals are gone and the
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test reads `*(s16 *)(arg0 + 0xAA)` inline (c3 = 0);
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- the halfword store first, the `+0xDC` RMW second, in both arms.
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Enumeration (`scratch/gen.py` -> `scratch/enum/`, 143 bodies, `scratch/enum_scores.txt`): every arm spelling that
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reads the halfword into its own value before the RMW scores 0 in combination (42 of 143: `BA`, `vu16A`, `vs32A`,
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`tmpPVF` (decompiler temps with the pointer and value split), `fB`, `pfB`, `mBA`); every spelling that keeps the RMW
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first or reuses `p` does not. Kept a `s32 flag` local: c1 = 0; declared `s16 flag = …` (c2): 1.
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(d) GENERATOR PROPOSAL: when a local is assigned twice in a straight-line block (`p = *(T *)(x + K); p = *(U *)(p + J);`
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or `g = load; g |= C; store g`) and the residual is a register permutation in that block, give each assignment its own
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value (inline or a fresh name) — both sets become sched1-birthing (sched.c:2469-2490), which reorders the block and
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therefore local-alloc's quantity NUMBERS, which is all a three-quantity block's order depends on (local-alloc.c:1486-1500).
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(e) Did not work: b1 (param copy deleted only) 16; c4/c5 (body.c with the param copy kept) 4 REG; every `AB`/`pA`/
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`fpA`/`tmpPF`/`tmpPF2`/`mAB` arm (store order or reused pointer) 6/7/13. The sweep's R7/R8/R5/R9/R10/R18 reached 4.
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(f) Method: METHOD c1/c8/d15 ("a local REUSED … split it") was the row; the new fact is that here the split acts through
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sched1's birthing boost and the three-quantity sort's use of quantity numbers, not through death counts — the
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allocation table (global) is blind to it; the `.sched` ready-list lines and `.lreg` "Register N in R" lines settled it.
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An enumeration over arm spellings (143 bodies, ~1 min) found it before any reading.
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(g) Structs: no. The decisions are sched1's birthing test (a register's set count) and local-alloc's quantity numbering;
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the object (`s16 +0x5C/+0x98/+0xAA/+0x100/+0x104`, `s32 +0x1C/+0xDC`, `+0x20` pointer to a record with `u16 +0x18`)
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as a struct would change spelling only. (The `+0x18` load vs the `+0xDC` store ordering is already what the source
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order gives; an in-struct marking would only matter if the store came first.)
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+173
-173
@@ -1,7 +1,7 @@
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{
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"head": "7e7d9c523",
|
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"head": "c37ef9c15",
|
||||
"stamp": "15956e4a96c4",
|
||||
"generated": "2026-09-11 02:04",
|
||||
"generated": "2026-09-11 02:05",
|
||||
"aliases": [
|
||||
"main",
|
||||
"ov_SC03_014",
|
||||
@@ -21,205 +21,205 @@
|
||||
"main": {
|
||||
"objects": 85,
|
||||
"identical": 85,
|
||||
"seconds": 6.5459999999999985,
|
||||
"mean_s": 0.077
|
||||
"seconds": 6.725000000000002,
|
||||
"mean_s": 0.079
|
||||
},
|
||||
"ov_SC03_014": {
|
||||
"objects": 32,
|
||||
"identical": 32,
|
||||
"seconds": 4.541,
|
||||
"mean_s": 0.142
|
||||
"seconds": 4.6339999999999995,
|
||||
"mean_s": 0.145
|
||||
},
|
||||
"ov_SC03_015": {
|
||||
"objects": 32,
|
||||
"identical": 32,
|
||||
"seconds": 4.361000000000001,
|
||||
"mean_s": 0.136
|
||||
"seconds": 4.427999999999998,
|
||||
"mean_s": 0.138
|
||||
},
|
||||
"ov_SC04_011": {
|
||||
"objects": 28,
|
||||
"identical": 28,
|
||||
"seconds": 3.834,
|
||||
"seconds": 3.846,
|
||||
"mean_s": 0.137
|
||||
}
|
||||
},
|
||||
"per_object_seconds": {
|
||||
"build/src/800.o": 0.722,
|
||||
"build/src/800_b.o": 0.073,
|
||||
"build/src/800_b_2.o": 0.305,
|
||||
"build/src/800_b_o0a.o": 0.059,
|
||||
"build/src/800_c.o": 0.194,
|
||||
"build/src/800b2.o": 0.073,
|
||||
"build/src/apicard1.o": 0.058,
|
||||
"build/src/apicard2.o": 0.062,
|
||||
"build/src/apicard3.o": 0.059,
|
||||
"build/src/apicard4.o": 0.069,
|
||||
"build/src/apicard5.o": 0.059,
|
||||
"build/src/apicard6.o": 0.079,
|
||||
"build/src/apicard7.o": 0.064,
|
||||
"build/src/boot.o": 0.093,
|
||||
"build/src/gap.o": 0.094,
|
||||
"build/src/libapi1.o": 0.062,
|
||||
"build/src/libapi2.o": 0.057,
|
||||
"build/src/libc2_1.o": 0.066,
|
||||
"build/src/libc2_2.o": 0.057,
|
||||
"build/src/libcd1.o": 0.071,
|
||||
"build/src/libcd2.o": 0.057,
|
||||
"build/src/libetc.o": 0.055,
|
||||
"build/src/libgpu.o": 0.067,
|
||||
"build/src/libgpu2.o": 0.064,
|
||||
"build/src/libgs1.o": 0.068,
|
||||
"build/src/libgs2.o": 0.06,
|
||||
"build/src/libgs3.o": 0.063,
|
||||
"build/src/libgs4.o": 0.066,
|
||||
"build/src/libgs5.o": 0.061,
|
||||
"build/src/libgs6.o": 0.076,
|
||||
"build/src/libgs7.o": 0.065,
|
||||
"build/src/libgs8.o": 0.06,
|
||||
"build/src/libgte1.o": 0.059,
|
||||
"build/src/libgte10.o": 0.058,
|
||||
"build/src/800.o": 0.741,
|
||||
"build/src/800_b.o": 0.078,
|
||||
"build/src/800_b_2.o": 0.312,
|
||||
"build/src/800_b_o0a.o": 0.064,
|
||||
"build/src/800_c.o": 0.184,
|
||||
"build/src/800b2.o": 0.095,
|
||||
"build/src/apicard1.o": 0.064,
|
||||
"build/src/apicard2.o": 0.069,
|
||||
"build/src/apicard3.o": 0.091,
|
||||
"build/src/apicard4.o": 0.076,
|
||||
"build/src/apicard5.o": 0.082,
|
||||
"build/src/apicard6.o": 0.092,
|
||||
"build/src/apicard7.o": 0.073,
|
||||
"build/src/boot.o": 0.112,
|
||||
"build/src/gap.o": 0.08,
|
||||
"build/src/libapi1.o": 0.065,
|
||||
"build/src/libapi2.o": 0.059,
|
||||
"build/src/libc2_1.o": 0.063,
|
||||
"build/src/libc2_2.o": 0.062,
|
||||
"build/src/libcd1.o": 0.067,
|
||||
"build/src/libcd2.o": 0.062,
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"build/src/ov_SC03_015/ov_SC03_015_o0e.o": 0.068,
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"build/src/ov_SC04_011/ov_SC04_011.o": 0.118,
|
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"build/src/ov_SC04_011/ov_SC04_011_after.o": 0.409,
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"build/src/ov_SC04_011/ov_SC04_011_jr_80135888.o": 0.041,
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"build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.147,
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"build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.075,
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"build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.163,
|
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"build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.069,
|
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"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.155,
|
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"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.089,
|
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"build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.061,
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"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.071,
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"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.088,
|
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|
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"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.098,
|
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"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.161,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.167,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.094,
|
||||
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|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.065,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.082,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.354,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.21,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.101,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.182,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.052,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.096,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.061,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.09,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.415,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.056,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.09,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.062,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.092,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.414,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.049,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.059
|
||||
},
|
||||
"ok": true,
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -7572,34 +7572,15 @@ void func_80185494(s32 a0) {
|
||||
|
||||
|
||||
void func_80185574(s32 arg0) {
|
||||
s32 self;
|
||||
register s32 zr __asm__("$0"); // !FAKE: pin $0 — NEEDED DIFFERS (P36 rung B tus8)
|
||||
s32 mask;
|
||||
s32 flag;
|
||||
|
||||
self = arg0 + zr;
|
||||
flag = *(s16 *)(self + 0xAA);
|
||||
*(s16 *)(self + 0x5C) = 0;
|
||||
*(s16 *)(self + 0x98) = 0;
|
||||
*(s32 *)(self + 0x1C) = 0;
|
||||
if (flag == 0) {
|
||||
s32 p;
|
||||
register s32 f __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus8)
|
||||
mask = ~0x80;
|
||||
p = *(s32 *)(self + 0x20);
|
||||
f = *(s32 *)(self + 0xDC);
|
||||
p = *(u16 *)(p + 0x18);
|
||||
*(s32 *)(self + 0xDC) = f & mask;
|
||||
*(s16 *)(self + 0x100) = p;
|
||||
*(s16 *)(arg0 + 0x5C) = 0;
|
||||
*(s16 *)(arg0 + 0x98) = 0;
|
||||
*(s32 *)(arg0 + 0x1C) = 0;
|
||||
if (*(s16 *)(arg0 + 0xAA) == 0) {
|
||||
*(s16 *)(arg0 + 0x100) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18);
|
||||
*(s32 *)(arg0 + 0xDC) &= ~0x80;
|
||||
} else {
|
||||
s32 q;
|
||||
register s32 g __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus8)
|
||||
q = *(s32 *)(self + 0x20);
|
||||
g = *(s32 *)(self + 0xDC);
|
||||
q = *(u16 *)(q + 0x18);
|
||||
g |= 0x80;
|
||||
*(s32 *)(self + 0xDC) = g;
|
||||
*(s16 *)(self + 0x104) = q;
|
||||
*(s16 *)(arg0 + 0x104) = *(u16 *)(*(s32 *)(arg0 + 0x20) + 0x18);
|
||||
*(s32 *)(arg0 + 0xDC) |= 0x80;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user