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feat(phase-30 S43): the 263x5 cluster BANKED 5/5 (+1,315 ins) — the SWEEP was corrupting correct drafts

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- R22 CLEAN-FLEET: 140 passed, 0 failed of 140. Fleet 12,502,519/13,160,961 = 94.997% instr
  (+18,146 instructions this session, 23 functions). 393 instructions from the 95.000% bar.
- REDO of the S43-9 retraction, done correctly through harvest_verify (splice/build/keep-iff-
  byte-identical/revert) instead of hand-building. 5/5 banked, each re-verified three ways:
  image SHA == locked SHA, stub gone, real definition present.
  ov_SC03_101/func_801814F8 · ov_SC03_104/func_80184934 · ov_SC04_003/func_8017E4F4 ·
  ov_SC04_005/func_80181054 · ov_SC04_007/func_8017FF08
- THE DEFECT THIS PROVES: family_sweep --hseq reported this family 0/5 with
  "PLUMBING: parse error before 'unsigned'" — but the remapped drafts are byte-CORRECT. The only
  `unsigned` in the draft is INSIDE A COMMENT, so a gate-pipeline transform is eating a `/*` opener
  and turning comment text into code. Per-transform runs on the draft alone all preserve it, so it
  needs the gate's real invocation (--src-file) to reproduce. NOT YET PINNED — and it is silently
  costing banks in every sweep it touches. Next: run the three transforms with --src-file and diff.
- Workaround that banked them: carry the exemplar's typedefs by hand (the family_remap _carry_macros
  gap, §146/§152) and gate directly, bypassing the sweep's recovery ladder.
- Also killed a self-inflicted infinite poll: an `until ! pgrep -f "permuter_ils.py <fn>"` loop whose
  pattern matched its OWN bash command line, so the condition could never go false (spun 2h30m).
  Same family as the day's other defects: a check that cannot return the answer that ends it.
This commit is contained in:
Drew T
2026-08-05 21:15:06 -06:00
parent 37c60a5ff3
commit 5c84ad5ada
9 changed files with 1330 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.run/s43/r22c_check.log
+141
View File
@@ -0,0 +1,141 @@
[ OK ] resident
[ OK ] ov_SC01_000
[ OK ] ov_SC05_000
[ OK ] ov_SC04_000
[ OK ] ov_SC01_006
[ OK ] ov_SC01_005
[ OK ] ov_SC01_001
[ OK ] ov_SC03_006
[ OK ] ov_SC03_002
[ OK ] ov_SC04_018
[ OK ] ov_SC04_019
[ OK ] ov_SC06_000
[ OK ] ov_SC03_001
[ OK ] ov_SC02_000
[ OK ] ov_SC01_077
[ OK ] ov_SC02_003
[ OK ] ov_SC07_000
[ OK ] ov_SC01_004
[ OK ] ov_SC01_074
[ OK ] ov_SC01_008
[ OK ] ov_SC01_080
[ OK ] ov_SC02_004
[ OK ] ov_SC01_084
[ OK ] ov_SC02_015
[ OK ] ov_SC01_009
[ OK ] ov_SC02_005
[ OK ] ov_SC02_011
[ OK ] ov_SC02_016
[ OK ] ov_SC02_021
[ OK ] ov_SC02_017
[ OK ] ov_SC02_026
[ OK ] main
[ OK ] ov_SC02_031
[ OK ] ov_SC03_010
[ OK ] ov_SC02_039
[ OK ] ov_SC03_007
[ OK ] ov_SC03_003
[ OK ] ov_SC02_041
[ OK ] ov_SC02_035
[ OK ] ov_SC02_027
[ OK ] ov_SC03_012
[ OK ] ov_SC02_028
[ OK ] ov_SC03_011
[ OK ] ov_SC03_013
[ OK ] ov_SC03_023
[ OK ] ov_SC03_014
[ OK ] ov_SC03_015
[ OK ] ov_SC03_024
[ OK ] ov_SC03_030
[ OK ] ov_SC03_031
[ OK ] ov_SC03_029
[ OK ] ov_SC03_028
[ OK ] ov_SC03_092
[ OK ] ov_SC03_095
[ OK ] ov_SC03_096
[ OK ] ov_SC03_089
[ OK ] ov_SC03_093
[ OK ] ov_SC03_094
[ OK ] ov_SC03_090
[ OK ] ov_SC03_091
[ OK ] ov_SC03_097
[ OK ] ov_SC03_099
[ OK ] ov_SC03_098
[ OK ] ov_SC03_100
[ OK ] ov_SC03_101
[ OK ] ov_SC03_103
[ OK ] ov_SC03_108
[ OK ] ov_SC03_109
[ OK ] ov_SC03_105
[ OK ] ov_SC03_102
[ OK ] ov_SC03_110
[ OK ] ov_SC03_113
[ OK ] ov_SC03_104
[ OK ] ov_SC03_111
[ OK ] ov_SC03_115
[ OK ] ov_SC03_114
[ OK ] ov_SC03_112
[ OK ] ov_SC03_116
[ OK ] ov_SC03_117
[ OK ] ov_SC03_121
[ OK ] ov_SC03_126
[ OK ] ov_SC03_118
[ OK ] ov_SC03_119
[ OK ] ov_SC04_008
[ OK ] ov_SC03_125
[ OK ] ov_SC04_003
[ OK ] ov_SC04_006
[ OK ] ov_SC03_124
[ OK ] ov_SC04_002
[ OK ] ov_SC04_004
[ OK ] ov_SC04_009
[ OK ] ov_SC04_007
[ OK ] ov_SC04_005
[ OK ] ov_SC04_010
[ OK ] ov_SC04_011
[ OK ] ov_SC04_012
[ OK ] ov_SC04_016
[ OK ] ov_SC04_015
[ OK ] ov_SC04_021
[ OK ] ov_SC04_020
[ OK ] ov_SC05_005
[ OK ] ov_SC05_003
[ OK ] ov_SC05_002
[ OK ] ov_SC05_009
[ OK ] ov_SC05_001
[ OK ] ov_SC05_006
[ OK ] ov_SC05_004
[ OK ] ov_SC05_008
[ OK ] ov_SC05_007
[ OK ] ov_SC05_010
[ OK ] ov_SC05_011
[ OK ] ov_SC05_019
[ OK ] ov_SC05_017
[ OK ] ov_SC05_018
[ OK ] ov_SC06_006
[ OK ] ov_SC06_010
[ OK ] ov_SC06_013
[ OK ] ov_SC06_015
[ OK ] ov_SC06_011
[ OK ] ov_SC06_014
[ OK ] ov_SC06_008
[ OK ] ov_SC06_016
[ OK ] ov_SC06_020
[ OK ] ov_SC06_022
[ OK ] ov_SC06_018
[ OK ] ov_SC06_025
[ OK ] ov_SC06_024
[ OK ] ov_SC06_027
[ OK ] ov_SC07_009
[ OK ] ov_SC07_008
[ OK ] ov_SC06_030
[ OK ] ov_SC07_002
[ OK ] ov_SC07_001
[ OK ] ov_SC07_007
[ OK ] ov_SC06_029
[ OK ] ov_SC07_010
[ OK ] ov_SC07_011
[ OK ] ov_SC06_032
[ OK ] ov_SC06_033
[ OK ] ov_SC07_006
check-all: 140 passed, 0 failed of 140
.run/s43/r22c_extract.log
+154
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@@ -0,0 +1,154 @@
splat 0.41.0 (powered by spimdisasm 1.41.0)
0%| | 0/1050 [00:00<?, ?it/s]
Loading symbols (symbols.us): 0%| | 0/1050 [00:00<?, ?it/s]
Loading symbols (symbols.us): 100%|██████████| 1050/1050 [00:00<00:00, 234993.82it/s]
0%| | 0/47 [00:00<?, ?it/s]
Loading symbols (symbols.us.ram): 0%| | 0/47 [00:00<?, ?it/s]
Loading symbols (symbols.us.ram): 100%|██████████| 47/47 [00:00<00:00, 668245.04it/s]
0%| | 0/2 [00:00<?, ?it/s]
Scanning header: 0%| | 0/2 [00:00<?, ?it/s]
Scanning main: 0%| | 0/2 [00:00<?, ?it/s]
Rodata segment '800' may belong to the text segment '800'
Based on the usage from the function LzssDecodeSector to the symbol jtbl_80072A38
Scanning main: 100%|██████████| 2/2 [00:01<00:00, 1.90it/s]
Scanning main: 100%|██████████| 2/2 [00:01<00:00, 1.90it/s]
0%| | 0/2 [00:00<?, ?it/s]
Splitting header: 0%| | 0/2 [00:00<?, ?it/s]
Splitting main: 0%| | 0/2 [00:00<?, ?it/s]
Splitting main: 100%|██████████| 2/2 [00:01<00:00, 1.92it/s]
Splitting main: 100%|██████████| 2/2 [00:01<00:00, 1.92it/s]
0%| | 0/2 [00:00<?, ?it/s]
Linker script header: 0%| | 0/2 [00:00<?, ?it/s]
Linker script main: 0%| | 0/2 [00:00<?, ?it/s]
Linker script main: 100%|██████████| 2/2 [00:00<00:00, 116.33it/s]
Split 340 KB (82.28%) in defined segments
header: 2 KB (0.50%) 1 split, 0 cached
c: 338 KB (81.78%) 78 split, 0 cached
unknown: 0 B (0.00%) from unknown bin files
ld_interleave: rewrote .main — text=78 front_data=79 rodata=78 tail_data=1 bss=78
[ OK ] resident
[ OK ] ov_SC05_000
[ OK ] ov_SC01_000
[ OK ] ov_SC04_000
[ OK ] ov_SC06_000
[ OK ] ov_SC03_002
[ OK ] ov_SC01_006
[ OK ] ov_SC01_005
[ OK ] ov_SC01_077
[ OK ] ov_SC02_003
[ OK ] ov_SC04_019
[ OK ] ov_SC04_018
[ OK ] ov_SC02_000
[ OK ] ov_SC03_006
[ OK ] ov_SC03_001
[ OK ] ov_SC01_001
[ OK ] ov_SC01_004
[ OK ] ov_SC01_008
[ OK ] ov_SC01_074
[ OK ] ov_SC07_000
[ OK ] ov_SC02_004
[ OK ] ov_SC02_015
[ OK ] ov_SC02_021
[ OK ] ov_SC01_080
[ OK ] ov_SC01_084
[ OK ] ov_SC01_009
[ OK ] ov_SC02_016
[ OK ] ov_SC02_039
[ OK ] ov_SC02_005
[ OK ] ov_SC02_026
[ OK ] ov_SC02_031
[ OK ] ov_SC02_028
[ OK ] ov_SC03_003
[ OK ] ov_SC02_011
[ OK ] ov_SC02_027
[ OK ] ov_SC02_035
[ OK ] ov_SC02_017
[ OK ] ov_SC02_041
[ OK ] ov_SC03_010
[ OK ] ov_SC03_012
[ OK ] ov_SC03_011
[ OK ] ov_SC03_013
[ OK ] ov_SC03_023
[ OK ] ov_SC03_007
[ OK ] ov_SC03_024
[ OK ] ov_SC03_031
[ OK ] ov_SC03_089
[ OK ] ov_SC03_092
[ OK ] ov_SC03_029
[ OK ] ov_SC03_014
[ OK ] ov_SC03_090
[ OK ] ov_SC03_015
[ OK ] ov_SC03_030
[ OK ] ov_SC03_095
[ OK ] ov_SC03_028
[ OK ] ov_SC03_093
[ OK ] ov_SC03_096
[ OK ] ov_SC03_091
[ OK ] ov_SC03_094
[ OK ] ov_SC03_097
[ OK ] ov_SC03_101
[ OK ] ov_SC03_098
[ OK ] ov_SC03_109
[ OK ] ov_SC03_108
[ OK ] ov_SC03_110
[ OK ] ov_SC03_099
[ OK ] ov_SC03_102
[ OK ] ov_SC03_112
[ OK ] ov_SC03_104
[ OK ] ov_SC03_103
[ OK ] ov_SC03_100
[ OK ] ov_SC03_113
[ OK ] ov_SC03_114
[ OK ] ov_SC03_105
[ OK ] ov_SC03_115
[ OK ] ov_SC03_111
[ OK ] ov_SC03_116
[ OK ] ov_SC03_126
[ OK ] ov_SC04_008
[ OK ] ov_SC04_003
[ OK ] ov_SC04_006
[ OK ] ov_SC04_009
[ OK ] ov_SC03_121
[ OK ] ov_SC03_117
[ OK ] ov_SC03_118
[ OK ] ov_SC04_004
[ OK ] ov_SC03_125
[ OK ] ov_SC03_119
[ OK ] ov_SC04_005
[ OK ] ov_SC04_007
[ OK ] ov_SC04_002
[ OK ] ov_SC04_010
[ OK ] ov_SC03_124
[ OK ] ov_SC04_012
[ OK ] ov_SC04_021
[ OK ] ov_SC04_016
[ OK ] ov_SC05_006
[ OK ] ov_SC05_002
[ OK ] ov_SC05_004
[ OK ] ov_SC04_020
[ OK ] ov_SC05_007
[ OK ] ov_SC05_003
[ OK ] ov_SC05_009
[ OK ] ov_SC05_008
[ OK ] ov_SC04_015
[ OK ] ov_SC05_001
[ OK ] ov_SC05_005
[ OK ] ov_SC04_011
[ OK ] ov_SC05_011
[ OK ] ov_SC05_010
[ OK ] ov_SC05_019
[ OK ] ov_SC06_013
[ OK ] ov_SC06_015
[ OK ] ov_SC06_008
[ OK ] ov_SC06_011
[ OK ] ov_SC06_016
[ OK ] ov_SC06_014
[ OK ] ov_SC06_010
[ OK ] ov_SC05_017
[ OK ] ov_SC06_020
docs/progress.fleet.md
+11 -11
View File
@@ -4,16 +4,16 @@
# cross-binary collapsible-byte leverage: docs/duplicates.cross.md.
# THREE progress metrics (all matter — see the labels):
FLEET fn-count byte-ident: 341793 / 353717 = 96.63% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay)
FLEET instr-weighted : 12501204 / 13160961 = 95.0% (shipped .text across main + resident + 138 overlays; the decomp.dev-DISPLAY number)
FLEET distinct-code(uniq): 5057462 / 5654184 = 89.4% (78096/87459 unique fns; the DISTINCT-RE number)
FLEET fn-count byte-ident: 341798 / 353717 = 96.63% (REAL+LINKED+empties; FUNCTION-count, ×134-inflated — one crack counts per overlay)
FLEET instr-weighted : 12502519 / 13160961 = 95.0% (shipped .text across main + resident + 138 overlays; the decomp.dev-DISPLAY number)
FLEET distinct-code(uniq): 5058777 / 5654184 = 89.5% (78101/87459 unique fns; the DISTINCT-RE number)
MAIN game-code weighted : 436 / 79510 = 0.5% (INCLUDED in the fleet numbers above since 2026-07-22 — roadmap §1 metrics contract; LINKED-excluding Ghidra sig dated 2026-08-05; caveat is R34: no independent second oracle for a PS-X EXE, NOT drift)
(fleet EXCLUDING main, for continuity with pre-2026-07-22 readings: 12500768 / 13081451 = 95.6%)
(fleet EXCLUDING main, for continuity with pre-2026-07-22 readings: 12502083 / 13081451 = 95.6%)
FLEET REAL substantive : 339938 (of which dedup-shared 241439 via 1919 groups / 241513 instances)
FLEET REAL substantive : 339943 (of which dedup-shared 241439 via 1919 groups / 241513 instances)
FLEET LINKED PsyQ objs : 959
FLEET NON_MATCHING : 7 (0 in any default build — G4)
FLEET INCLUDE_ASM stubs : 11917
FLEET INCLUDE_ASM stubs : 11912
FLEET matchable : 353717
| binary | REAL | shared | LINKED | byte-ident | matchable | byte-ident % |
@@ -76,10 +76,10 @@ FLEET matchable : 353717
| ov_SC03_098 | 2509 | 1751 | 0 | 2512 | 2541 | 98.9% |
| ov_SC03_099 | 2485 | 1751 | 0 | 2488 | 2504 | 99.4% |
| ov_SC03_100 | 2520 | 1751 | 0 | 2524 | 2539 | 99.4% |
| ov_SC03_101 | 2482 | 1756 | 0 | 2486 | 2528 | 98.3% |
| ov_SC03_101 | 2483 | 1756 | 0 | 2487 | 2528 | 98.4% |
| ov_SC03_102 | 2469 | 1751 | 0 | 2472 | 2492 | 99.2% |
| ov_SC03_103 | 2493 | 1753 | 0 | 2496 | 2510 | 99.4% |
| ov_SC03_104 | 2540 | 1756 | 0 | 2547 | 2616 | 97.4% |
| ov_SC03_104 | 2541 | 1756 | 0 | 2548 | 2616 | 97.4% |
| ov_SC03_105 | 2448 | 1752 | 0 | 2455 | 2597 | 94.5% |
| ov_SC03_108 | 2399 | 1751 | 0 | 2399 | 2443 | 98.2% |
| ov_SC03_109 | 2407 | 1751 | 0 | 2409 | 2424 | 99.4% |
@@ -99,11 +99,11 @@ FLEET matchable : 353717
| ov_SC03_126 | 2399 | 1753 | 0 | 2399 | 2423 | 99.0% |
| ov_SC04_000 | 2473 | 1755 | 0 | 2482 | 2546 | 97.5% |
| ov_SC04_002 | 2503 | 1751 | 0 | 2507 | 2636 | 95.1% |
| ov_SC04_003 | 2437 | 1751 | 0 | 2441 | 2502 | 97.6% |
| ov_SC04_003 | 2438 | 1751 | 0 | 2442 | 2502 | 97.6% |
| ov_SC04_004 | 2469 | 1751 | 0 | 2471 | 2558 | 96.6% |
| ov_SC04_005 | 2498 | 1751 | 0 | 2504 | 2612 | 95.9% |
| ov_SC04_005 | 2499 | 1751 | 0 | 2505 | 2612 | 95.9% |
| ov_SC04_006 | 2429 | 1751 | 0 | 2431 | 2454 | 99.1% |
| ov_SC04_007 | 2492 | 1751 | 0 | 2496 | 2569 | 97.2% |
| ov_SC04_007 | 2493 | 1751 | 0 | 2497 | 2569 | 97.2% |
| ov_SC04_008 | 2399 | 1751 | 0 | 2399 | 2415 | 99.3% |
| ov_SC04_009 | 2426 | 1751 | 0 | 2429 | 2441 | 99.5% |
| ov_SC04_010 | 2401 | 1751 | 0 | 2402 | 2419 | 99.3% |
phase-ends/CURRENT_PHASE.md
+24
View File
@@ -2451,6 +2451,30 @@ remap — worth pinning, since it may be silently killing other sweeps.
*(Also corrected: my "41 behemoth drafts" was a FILE count — 79 unblocked files resolve to 20 distinct
functions, 36 of them fragments of one small function.)*
### ▶ S43-11 — the 263×5 cluster BANKED 5/5: the sweep's own pipeline was corrupting byte-correct drafts (2026-08-05)
Redo of S43-9's retracted claim, done correctly through `harvest_verify` (splice → build → keep iff
byte-identical → revert), not by hand-building. **5/5 banked, 1,315 instructions**, each independently
re-verified three ways: image SHA == locked SHA, stub gone, real definition present.
| binary | fn | binary | fn |
|---|---|---|---|
| ov_SC03_101 | func_801814F8 | ov_SC04_005 | func_80181054 |
| ov_SC03_104 | func_80184934 | ov_SC04_007 | func_8017FF08 |
| ov_SC04_003 | func_8017E4F4 | | |
**THE DEFECT THIS PROVES:** `family_sweep --hseq` reported this family **0/5 with
`PLUMBING: parse error before 'unsigned'`** — but the remapped drafts are byte-CORRECT. The parse error
comes from the sweep's own **gate-pipeline transform**, not from the remap: the only `unsigned` in the
draft sits inside a comment, so a transform is eating a `/*` opener and turning comment text into code.
Isolated per-transform runs (`canon_resident_calls` / `cast_call_sites` / `sig_unify`, each on the draft
alone) all preserve it — so the corruption needs the gate's real invocation (with `--src-file`) to
reproduce. **NOT YET PINNED — and it is silently costing banks in every sweep it touches.** Next
session: run the three transforms with `--src-file` set to the target TU and diff the output.
**The workaround that banked them:** carry the exemplar's typedefs onto each remapped draft by hand
(the same `family_remap` `_carry_macros` gap as §146/§152) and gate directly, bypassing the sweep's
recovery ladder entirely. Drafts + gate logs: `.run/s43/cluster_gate/`.
### ▶ S11 — the propagation lag: EXTEND 0/36 -> 31/36, and every blocker was a DECLARATION (2026-08-03/04)
Lane 2 of the S10 checkpoint ("26,006 ins, ~0 agent tokens, PARTLY BLOCKED"), taken first on the
standing doctrine that the cheap deterministic lever is probed before the expensive agent one.
src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c
+200 -1
View File
@@ -4785,7 +4785,206 @@ INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_801813C
INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_801814AC);
INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_801814F8);
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
void func_801814F8(void *a0, void *a1)
{
extern void func_8001E094(void);
extern void func_8001E378(void *a0);
extern void func_80181914(void *a0, void *a1, u32 *a2, u32 *a3);
extern u8 D_800A6610[];
extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0);
* unsigned access forced at the use — §8d sub-class (b) */
Vec8_80182FD4 base;
Vec8_80182FD4 v[3];
u32 buf[19];
long flag;
long otz;
long flag2;
Src_80182FD4 *s;
u32 *ot;
s32 z;
s32 i;
u16 w;
ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14];
s = *(Src_80182FD4 **)((s32)a0 + 0x20);
if (s == 0) {
return;
}
if (*(s32 *)((s32)a0 + 0x34) != 0) {
func_8001E094();
} else {
func_8001E378(a0);
}
base.vx = *(u16 *)((s32)a0 + 0x2E);
base.vy = *(u16 *)((s32)a0 + 0x30);
base.vz = *(u16 *)((s32)a0 + 0x32);
gte_ldv0(&base);
gte_rtps();
gte_stsxy(&buf[0]);
gte_stflg(&flag);
gte_stszotz(&otz);
if (flag & ~0x1000) {
return;
}
w = *(u16 *)((s32)a0 + 0x2C);
z = otz + 1;
if ((w & 0xC000) != 0) {
if ((w & 0xC000) == 0xC000) {
z -= (w & 0xFFF);
if (z < 0) {
z = 0;
}
} else {
z += (w & 0xFFF);
}
}
if (z >= 0x1000) {
return;
}
if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) {
for (i = 0; i < 12; i += 6) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 2].vx;
v[1].vy = base.vy + s->pt[i + 2].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 4].vx;
v[2].vy = base.vy + s->pt[i + 4].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]);
}
for (i = 1; i < 12; i += 2) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
gte_ldv0(&v[0]);
gte_rtps();
gte_stsxy(&buf[i + 1]);
gte_stflg(&flag2);
gte_stszotz(&otz);
buf[13 + (i >> 1)] = otz + 1;
}
func_80181914(a0, a1, &buf[0], ot);
} else {
for (i = 0; i < 12; i += 3) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 1].vx;
v[1].vy = base.vy + s->pt[i + 1].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 2].vx;
v[2].vy = base.vy + s->pt[i + 2].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]);
}
func_80181914(a0, a1, &buf[0], ot + z);
}
}
#define ADDPRIM_801833F0(o, p) \
(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c
+200 -1
View File
@@ -4897,7 +4897,206 @@ INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_8018480
INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_801848E8);
INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_80184934);
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
void func_80184934(void *a0, void *a1)
{
extern void func_8001E094(void);
extern void func_8001E378(void *a0);
extern void func_80184D50(void *a0, void *a1, u32 *a2, u32 *a3);
extern u8 D_800A6610[];
extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0);
* unsigned access forced at the use — §8d sub-class (b) */
Vec8_80182FD4 base;
Vec8_80182FD4 v[3];
u32 buf[19];
long flag;
long otz;
long flag2;
Src_80182FD4 *s;
u32 *ot;
s32 z;
s32 i;
u16 w;
ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14];
s = *(Src_80182FD4 **)((s32)a0 + 0x20);
if (s == 0) {
return;
}
if (*(s32 *)((s32)a0 + 0x34) != 0) {
func_8001E094();
} else {
func_8001E378(a0);
}
base.vx = *(u16 *)((s32)a0 + 0x2E);
base.vy = *(u16 *)((s32)a0 + 0x30);
base.vz = *(u16 *)((s32)a0 + 0x32);
gte_ldv0(&base);
gte_rtps();
gte_stsxy(&buf[0]);
gte_stflg(&flag);
gte_stszotz(&otz);
if (flag & ~0x1000) {
return;
}
w = *(u16 *)((s32)a0 + 0x2C);
z = otz + 1;
if ((w & 0xC000) != 0) {
if ((w & 0xC000) == 0xC000) {
z -= (w & 0xFFF);
if (z < 0) {
z = 0;
}
} else {
z += (w & 0xFFF);
}
}
if (z >= 0x1000) {
return;
}
if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) {
for (i = 0; i < 12; i += 6) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 2].vx;
v[1].vy = base.vy + s->pt[i + 2].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 4].vx;
v[2].vy = base.vy + s->pt[i + 4].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]);
}
for (i = 1; i < 12; i += 2) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
gte_ldv0(&v[0]);
gte_rtps();
gte_stsxy(&buf[i + 1]);
gte_stflg(&flag2);
gte_stszotz(&otz);
buf[13 + (i >> 1)] = otz + 1;
}
func_80184D50(a0, a1, &buf[0], ot);
} else {
for (i = 0; i < 12; i += 3) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 1].vx;
v[1].vy = base.vy + s->pt[i + 1].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 2].vx;
v[2].vy = base.vy + s->pt[i + 2].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]);
}
func_80184D50(a0, a1, &buf[0], ot + z);
}
}
#define ADDPRIM_801833F0(o, p) \
(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
src/ov_SC04_003/ov_SC04_003_jr_8017BEBC.c
+200 -1
View File
@@ -3855,7 +3855,206 @@ INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E39
INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E498);
INCLUDE_ASM("asm/ov_SC04_003/nonmatchings/ov_SC04_003_jr_8017BEBC", func_8017E4F4);
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
void func_8017E4F4(void *a0, void *a1)
{
extern void func_8001E094(void);
extern void func_8001E378(void *a0);
extern void func_8017E910(void *a0, void *a1, u32 *a2, u32 *a3);
extern u8 D_800A6610[];
extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0);
* unsigned access forced at the use — §8d sub-class (b) */
Vec8_80182FD4 base;
Vec8_80182FD4 v[3];
u32 buf[19];
long flag;
long otz;
long flag2;
Src_80182FD4 *s;
u32 *ot;
s32 z;
s32 i;
u16 w;
ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14];
s = *(Src_80182FD4 **)((s32)a0 + 0x20);
if (s == 0) {
return;
}
if (*(s32 *)((s32)a0 + 0x34) != 0) {
func_8001E094();
} else {
func_8001E378(a0);
}
base.vx = *(u16 *)((s32)a0 + 0x2E);
base.vy = *(u16 *)((s32)a0 + 0x30);
base.vz = *(u16 *)((s32)a0 + 0x32);
gte_ldv0(&base);
gte_rtps();
gte_stsxy(&buf[0]);
gte_stflg(&flag);
gte_stszotz(&otz);
if (flag & ~0x1000) {
return;
}
w = *(u16 *)((s32)a0 + 0x2C);
z = otz + 1;
if ((w & 0xC000) != 0) {
if ((w & 0xC000) == 0xC000) {
z -= (w & 0xFFF);
if (z < 0) {
z = 0;
}
} else {
z += (w & 0xFFF);
}
}
if (z >= 0x1000) {
return;
}
if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) {
for (i = 0; i < 12; i += 6) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 2].vx;
v[1].vy = base.vy + s->pt[i + 2].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 4].vx;
v[2].vy = base.vy + s->pt[i + 4].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]);
}
for (i = 1; i < 12; i += 2) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
gte_ldv0(&v[0]);
gte_rtps();
gte_stsxy(&buf[i + 1]);
gte_stflg(&flag2);
gte_stszotz(&otz);
buf[13 + (i >> 1)] = otz + 1;
}
func_8017E910(a0, a1, &buf[0], ot);
} else {
for (i = 0; i < 12; i += 3) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 1].vx;
v[1].vy = base.vy + s->pt[i + 1].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 2].vx;
v[2].vy = base.vy + s->pt[i + 2].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]);
}
func_8017E910(a0, a1, &buf[0], ot + z);
}
}
#define ADDPRIM_801833F0(o, p) \
(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
src/ov_SC04_005/ov_SC04_005_jr_8017BEBC.c
+200 -1
View File
@@ -5747,7 +5747,206 @@ INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80180EF
INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80180FF8);
INCLUDE_ASM("asm/ov_SC04_005/nonmatchings/ov_SC04_005_jr_8017BEBC", func_80181054);
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
void func_80181054(void *a0, void *a1)
{
extern void func_8001E094(void);
extern void func_8001E378(void *a0);
extern void func_80181470(void *a0, void *a1, u32 *a2, u32 *a3);
extern u8 D_800A6610[];
extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0);
* unsigned access forced at the use — §8d sub-class (b) */
Vec8_80182FD4 base;
Vec8_80182FD4 v[3];
u32 buf[19];
long flag;
long otz;
long flag2;
Src_80182FD4 *s;
u32 *ot;
s32 z;
s32 i;
u16 w;
ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14];
s = *(Src_80182FD4 **)((s32)a0 + 0x20);
if (s == 0) {
return;
}
if (*(s32 *)((s32)a0 + 0x34) != 0) {
func_8001E094();
} else {
func_8001E378(a0);
}
base.vx = *(u16 *)((s32)a0 + 0x2E);
base.vy = *(u16 *)((s32)a0 + 0x30);
base.vz = *(u16 *)((s32)a0 + 0x32);
gte_ldv0(&base);
gte_rtps();
gte_stsxy(&buf[0]);
gte_stflg(&flag);
gte_stszotz(&otz);
if (flag & ~0x1000) {
return;
}
w = *(u16 *)((s32)a0 + 0x2C);
z = otz + 1;
if ((w & 0xC000) != 0) {
if ((w & 0xC000) == 0xC000) {
z -= (w & 0xFFF);
if (z < 0) {
z = 0;
}
} else {
z += (w & 0xFFF);
}
}
if (z >= 0x1000) {
return;
}
if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) {
for (i = 0; i < 12; i += 6) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 2].vx;
v[1].vy = base.vy + s->pt[i + 2].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 4].vx;
v[2].vy = base.vy + s->pt[i + 4].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]);
}
for (i = 1; i < 12; i += 2) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
gte_ldv0(&v[0]);
gte_rtps();
gte_stsxy(&buf[i + 1]);
gte_stflg(&flag2);
gte_stszotz(&otz);
buf[13 + (i >> 1)] = otz + 1;
}
func_80181470(a0, a1, &buf[0], ot);
} else {
for (i = 0; i < 12; i += 3) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 1].vx;
v[1].vy = base.vy + s->pt[i + 1].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 2].vx;
v[2].vy = base.vy + s->pt[i + 2].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]);
}
func_80181470(a0, a1, &buf[0], ot + z);
}
}
#define ADDPRIM_801833F0(o, p) \
(((PTag_801833F0 *)(p))->addr = ((PTag_801833F0 *)(o))->addr, \
src/ov_SC04_007/ov_SC04_007_jr_8017BEBC.c
+200 -1
View File
@@ -5116,7 +5116,206 @@ INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017FDB
INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017FEAC);
INCLUDE_ASM("asm/ov_SC04_007/nonmatchings/ov_SC04_007_jr_8017BEBC", func_8017FF08);
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_ldv0(r0) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 )" \
: \
: "r"( r0 ) )
#define gte_ldv3(r0, r1, r2) __asm__ volatile ( \
"lwc2 $0, 0( %0 );" \
"lwc2 $1, 4( %0 );" \
"lwc2 $2, 0( %1 );" \
"lwc2 $3, 4( %1 );" \
"lwc2 $4, 0( %2 );" \
"lwc2 $5, 4( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) )
#define gte_rtps() __asm__ volatile ("nop;nop;rtps")
#define gte_rtpt() __asm__ volatile ("nop;nop;rtpt")
#define gte_stsxy(r0) __asm__ volatile ( \
"swc2 $14, 0( %0 )" \
: \
: "r"( r0 ) \
: "memory" )
#define gte_stsxy3(r0, r1, r2) __asm__ volatile ( \
"swc2 $12, 0( %0 );" \
"swc2 $13, 0( %1 );" \
"swc2 $14, 0( %2 )" \
: \
: "r"( r0 ), "r"( r1 ), "r"( r2 ) \
: "memory" )
#define gte_stszotz(r0) __asm__ volatile ( \
"mfc2 $12, $19;" \
"nop;" \
"sra $12, $12, 2;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
#define gte_stflg(r0) __asm__ volatile ( \
"cfc2 $12, $31;" \
"nop;" \
"sw $12, 0( %0 )" \
: \
: "r"( r0 ) \
: "$12", "memory" )
void func_8017FF08(void *a0, void *a1)
{
extern void func_8001E094(void);
extern void func_8001E378(void *a0);
extern void func_80180324(void *a0, void *a1, u32 *a2, u32 *a3);
extern u8 D_800A6610[];
extern short D_800B9A02; /* TU-visible spelling (engine_core.h + ov_SC01_000.c col-0);
* unsigned access forced at the use — §8d sub-class (b) */
Vec8_80182FD4 base;
Vec8_80182FD4 v[3];
u32 buf[19];
long flag;
long otz;
long flag2;
Src_80182FD4 *s;
u32 *ot;
s32 z;
s32 i;
u16 w;
ot = (u32 *)&D_800A6610[(*(u16 *)&D_800B9A02) << 14];
s = *(Src_80182FD4 **)((s32)a0 + 0x20);
if (s == 0) {
return;
}
if (*(s32 *)((s32)a0 + 0x34) != 0) {
func_8001E094();
} else {
func_8001E378(a0);
}
base.vx = *(u16 *)((s32)a0 + 0x2E);
base.vy = *(u16 *)((s32)a0 + 0x30);
base.vz = *(u16 *)((s32)a0 + 0x32);
gte_ldv0(&base);
gte_rtps();
gte_stsxy(&buf[0]);
gte_stflg(&flag);
gte_stszotz(&otz);
if (flag & ~0x1000) {
return;
}
w = *(u16 *)((s32)a0 + 0x2C);
z = otz + 1;
if ((w & 0xC000) != 0) {
if ((w & 0xC000) == 0xC000) {
z -= (w & 0xFFF);
if (z < 0) {
z = 0;
}
} else {
z += (w & 0xFFF);
}
}
if (z >= 0x1000) {
return;
}
if (*(s16 *)((s32)a0 + 0x1E) & 0x8000) {
for (i = 0; i < 12; i += 6) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 2].vx;
v[1].vy = base.vy + s->pt[i + 2].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 4].vx;
v[2].vy = base.vy + s->pt[i + 4].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 3], &buf[i + 5]);
}
for (i = 1; i < 12; i += 2) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
gte_ldv0(&v[0]);
gte_rtps();
gte_stsxy(&buf[i + 1]);
gte_stflg(&flag2);
gte_stszotz(&otz);
buf[13 + (i >> 1)] = otz + 1;
}
func_80180324(a0, a1, &buf[0], ot);
} else {
for (i = 0; i < 12; i += 3) {
v[0].vx = base.vx + s->pt[i].vx;
v[0].vy = base.vy + s->pt[i].vy;
v[0].vz = base.vz;
v[1].vx = base.vx + s->pt[i + 1].vx;
v[1].vy = base.vy + s->pt[i + 1].vy;
v[1].vz = base.vz;
v[2].vx = base.vx + s->pt[i + 2].vx;
v[2].vy = base.vy + s->pt[i + 2].vy;
v[2].vz = base.vz;
gte_ldv3(&v[0], &v[1], &v[2]);
gte_rtpt();
gte_stsxy3(&buf[i + 1], &buf[i + 2], &buf[i + 3]);
}
func_80180324(a0, a1, &buf[0], ot + z);
}
}
#define ADDPRIM_801833F0(o, p) \