mirror/BFM-decomp
1
0
Fork 0
mirror of https://github.com/Druthulu/BFM-decomp synced 2026-09-26 13:33:34 -04:00
Code Issues Packages Projects Releases Wiki Activity

feat(decomp): worker gate — +1 fns x0 propagated (fleet 99.2%)

Browse Source
This commit is contained in:
Drew T
2026-08-30 22:15:26 -06:00
parent 21d7d8675d
commit 6f51dbf267
3 changed files with 56 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
config/overlays.mk
+2 -2
View File
@@ -134,7 +134,7 @@ ov_SC03_001_ELF := $(ov_SC03_001_OUT).elf
ov_SC03_001_MAPFILE := $(ov_SC03_001_OUT).map
ov_SC03_001_LD_SCRIPT := $(ov_SC03_001_OUT).ld
ov_SC03_001_SPLAT_YAML := config/splat.ov_SC03_001.yaml
ov_SC03_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_001.o,ov_SC03_001_jr_8012ACE0.o,tail2.data.o,ov_SC03_001_jr_80135888.o,tail3.data.o,ov_SC03_001_jr_80135A4C.o,tail4.data.o,ov_SC03_001_jr_80135D20.o,tail5.data.o,ov_SC03_001_jr_801380E0.o,ov_SC03_001_o0c.o,tail6.data.o,ov_SC03_001_jr_8013F350.o,tail7.data.o,ov_SC03_001_jr_8013FFD8.o,tail8.data.o,ov_SC03_001_jr_80140608.o,tail9.data.o,ov_SC03_001_jr_8015444C.o,ov_SC03_001_jr_80154C24.o,ov_SC03_001_jr_801588CC.o,ov_SC03_001_jr_80159C84.o,tail10.data.o,ov_SC03_001_jr_8015A3C8.o,tail11.data.o,ov_SC03_001_jr_8015AE2C.o,tail12.data.o,ov_SC03_001_jr_8015C32C.o,tail13.data.o,ov_SC03_001_jr_8016AB6C.o,tail14.data.o,ov_SC03_001_jr_80171B4C.o,ov_SC03_001_jr_801734BC.o,tail15.data.o,ov_SC03_001_jr_801789AC.o,ov_SC03_001_jr_80178D40.o,tail16.data.o,ov_SC03_001_jr_8017A4AC.o,tail17.data.o,ov_SC03_001_jr_8017AE2C.o,tail18.data.o,ov_SC03_001_jr_80184DDC.o,tail19.data.o,ov_SC03_001_jr_80184F64.o,tail20.data.o,ov_SC03_001_jr_8018631C.o,ov_SC03_001_jr_801870B0.o,ov_SC03_001_jr_80188830.o,tail21.data.o,ov_SC03_001_jr_80189030.o,tail22.data.o,ov_SC03_001_jr_8018A3A8.o,ov_SC03_001_jr_8018B8DC.o,tail23.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
ov_SC03_001_JTBL_INTERLEAVE := --order tail.data.o,ov_SC03_001.o,ov_SC03_001_jr_8012ACE0.o,tail2.data.o,ov_SC03_001_jr_80135888.o,tail3.data.o,ov_SC03_001_jr_80135A4C.o,tail4.data.o,ov_SC03_001_jr_80135D20.o,tail5.data.o,ov_SC03_001_jr_801380E0.o,ov_SC03_001_o0c.o,tail6.data.o,ov_SC03_001_jr_8013F350.o,tail7.data.o,ov_SC03_001_jr_8013FFD8.o,tail8.data.o,ov_SC03_001_jr_80140608.o,tail9.data.o,ov_SC03_001_jr_8015444C.o,ov_SC03_001_jr_80154C24.o,ov_SC03_001_jr_801588CC.o,ov_SC03_001_jr_80159C84.o,tail10.data.o,ov_SC03_001_jr_8015A3C8.o,tail11.data.o,ov_SC03_001_jr_8015AE2C.o,tail12.data.o,ov_SC03_001_jr_8015C32C.o,tail13.data.o,ov_SC03_001_jr_8016AB6C.o,tail14.data.o,ov_SC03_001_jr_80171B4C.o,ov_SC03_001_jr_801734BC.o,tail15.data.o,ov_SC03_001_jr_801789AC.o,ov_SC03_001_jr_80178D40.o,tail16.data.o,ov_SC03_001_jr_8017A4AC.o,tail17.data.o,ov_SC03_001_jr_8017AE2C.o,ov_SC03_001_jr_80184DDC.o,tail18.data.o,ov_SC03_001_jr_80184F64.o,tail19.data.o,ov_SC03_001_jr_8018631C.o,ov_SC03_001_jr_801870B0.o,ov_SC03_001_jr_80188830.o,tail20.data.o,ov_SC03_001_jr_80189030.o,tail21.data.o,ov_SC03_001_jr_8018A3A8.o,ov_SC03_001_jr_8018B8DC.o,tail22.data.o,trailing.o # Phase-26 §8 jtbl-rodata carve
build/src/ov_SC03_001/ov_SC03_001.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
build/src/ov_SC03_001/ov_SC03_001_jr_8012ACE0.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0xcc,+0xe0
build/src/ov_SC03_001/ov_SC03_001_jr_80135D20.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x18
@@ -147,7 +147,7 @@ build/src/ov_SC03_001/ov_SC03_001_jr_80159C84.o: JTBL_PADS := 0,4 # §8e pads (
build/src/ov_SC03_001/ov_SC03_001_jr_8015AE2C.o: JTBL_PADS := 0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC03_001/ov_SC03_001_jr_8016AB6C.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x20
build/src/ov_SC03_001/ov_SC03_001_jr_80178D40.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x178
build/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.o: JTBL_PADS := 0,0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14,+0x34
build/src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.o: JTBL_PADS := 0,0,0,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14,+0x34,+0x4c
build/src/ov_SC03_001/ov_SC03_001_jr_80184F64.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x14
build/src/ov_SC03_001/ov_SC03_001_jr_8018A3A8.o: JTBL_PADS := 0,0 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38
build/src/ov_SC03_001/ov_SC03_001_o0c.o: JTBL_PADS := 0,4,4,4 # §8e pads (jtbl_carve.py) tables=+0x0,+0x38,+0xa8,+0x118
config/splat.ov_SC03_001.yaml
+5 -6
View File
@@ -169,20 +169,19 @@ segments:
- [0xc4bac, .rodata, ov_SC03_001_jr_8017A4AC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc4c38, data, tail17]
- [0xc4c3c, .rodata, ov_SC03_001_jr_8017AE2C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc4c84, data, tail18]
- [0xc4c9c, .rodata, ov_SC03_001_jr_80184DDC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc4cb0, data, tail19]
- [0xc4cb0, data, tail18]
- [0xc4cb4, .rodata, ov_SC03_001_jr_80184F64] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc4d30, data, tail20]
- [0xc4d30, data, tail19]
- [0xc4dc0, .rodata, ov_SC03_001_jr_8018631C] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc4dd4, .rodata, ov_SC03_001_jr_801870B0] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc4dec, .rodata, ov_SC03_001_jr_80188830] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc4e08, data, tail21]
- [0xc4e08, data, tail20]
- [0xc50a8, .rodata, ov_SC03_001_jr_80189030] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc50bc, data, tail22]
- [0xc50bc, data, tail21]
- [0xc5130, .rodata, ov_SC03_001_jr_8018A3A8] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc5188, .rodata, ov_SC03_001_jr_8018B8DC] # Phase-26 §8 jtbl-rodata carve (jtbl_carve.py)
- [0xc51e4, data, tail23]
- [0xc51e4, data, tail22]
- [0xC730C, bin, trailing] # final 3 bytes (EOF not 4-aligned; spimdisasm drops a partial word)
- [0xC730F] # EOF marker = the 0.4.dec byte length
# @TRAILING@ (above) is replaced by tools/new_overlay.sh: for a non-4-aligned overlay it becomes
src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c
+49 -1
View File
@@ -8406,7 +8406,55 @@ void func_80182B78(void *arg0) {
}
INCLUDE_ASM("asm/ov_SC03_001/nonmatchings/ov_SC03_001_jr_8017AE2C", func_80182BB8);
extern s32 func_80187A64(s32 a0);
extern s32 func_801886A0(s32 a0);
extern u8 D_801B9360[];
extern u8 D_801B93A4[];
extern u8 D_801B93F4[];
extern void func_80187994(s32, s32, s32, s32);
extern void func_8018268C(void *arg0);
void func_80182BB8(void *arg0)
{
switch (*(u16 *)((s32)arg0 + 0x34)) {
case 0:
if (func_801886A0(3) == 0) {
return;
}
*(u16 *)((s32)arg0 + 0x34) = 1;
func_80187994((s32)arg0, (s32)D_801B9360, 0, 0x80);
return;
case 1:
func_801886A0(3);
if (func_80187A64((s32)arg0) == 0) {
return;
}
*(u16 *)((s32)arg0 + 0x34) = 2;
func_80187994((s32)arg0, (s32)D_801B93A4, 0, 0x80);
return;
case 2:
if (func_80187A64((s32)arg0) == 0) {
return;
}
*(u16 *)((s32)arg0 + 0x34) = 3;
return;
case 3:
if (func_801886A0(0xD) == 0) {
return;
}
*(u16 *)((s32)arg0 + 0x34) = 4;
func_80187994((s32)arg0, (s32)D_801B93F4, 0, 0x80);
return;
case 4:
func_801886A0(0xD);
if (func_80187A64((s32)arg0) == 0) {
return;
}
func_8018268C(arg0);
return;
}
}
/* func_80182CC4 — guarded dispatch: ask func_8018766C(17, 0x12); if it answers