phase-36: S104 s104_e16 — func_800331D4 banked at 0 through the whole-object gate + propagated — pin → 0: return ++i (allocno_compare refs, global.c:587-603)

2026-09-30 15:36:55 -04:00 · 2026-09-11 02:33:23 -06:00
parent 8cdc076127
commit 75cb21c7a7
11 changed files with 615 additions and 188 deletions
@@ -0,0 +1,15 @@
+void func_80031B7C(void) {
+    s32 i = 0;
+    s32 one = 1;
+    s32 full = 0x7FFF;
+    u8 *p = D_800A49D2;
+
+loop:
+    if (p[4] && !p[2] && p[3]) {
+        p[2] = one;
+        *(u16 *)p = full;
+    }
+    p += 0x54;
+    i++;
+    if (i < 8) goto loop;
+}
@@ -0,0 +1,67 @@
+# func_80031B7C (src/800_b_2.c) — S104 agent e16 — CLOSED at 0, ZERO levers (1 pin -> 0)
+
+## (a) The residual
+Score 18, COUNT, 27 vs 25. Mine keeps TWO loop registers for the record pointer — the walked pointer (used by the
+`sh` at offset 0) and a second one `addiu v1,a0,2` that carries the `+2/+3/+4` byte reads and the `sb` — and steps
+both; the target walks ONE pointer `$v1` with every access an offset from it (`lbu 4/2/3(v1)`, `sb 2(v1)`, `sh 0(v1)`).
+The counter/constant register shuffle (`a0/a2/a1` vs `a1/a3/a2`) is fallout of the extra pseudo.
+
+## (b) The pass and the decision (PROVEN on the `.loop` dump, scratch/dumps_free)
+loop.c strength reduction. The `-dL` dump of the lever-free do-while says:
+`Cannot eliminate biv 75: biv used in insn 44.` (the pointer, used directly by `*(u16 *)v1 = …`) and
+`giv at 41 reduced to (reg:SI 84)` with the givs at 34/29/24 combined into it — the `p+2` address giv
+(`record_giv` loop.c:4341, `combine_givs` loop.c:5494) gets its own register while the biv stays live.
+The tree's `$3` pin worked because loop.c never treats a hard register as a biv. The target was never strength-reduced
+at all: it was not a LOOP to loop.c. `loop_optimize` counts `NOTE_INSN_LOOP_BEG` notes and returns when there are none
+(loop.c:352-361, "Don't waste time if no loops"); those notes come only from `expand_start_loop` (stmt.c:2171), i.e.
+from `for`/`while`/`do`. A backward `goto` emits no note. The constants `1` and `0x7FFF` sit in registers set before the
+loop in the target — with no loop.c there is no invariant motion, so the source itself held them in locals (a body with
+the constants written inline at the stores scores 10: they are materialised inside the loop).
+
+## (c) The move that closed it (PROVEN on bytes)
+The do-while written as the backward `goto` loop it compiles like:
+```c
+void func_80031B7C(void) {
+    s32 i = 0;
+    s32 one = 1;
+    s32 full = 0x7FFF;
+    u8 *p = D_800A49D2;
+
+loop:
+    if (p[4] && !p[2] && p[3]) {
+        p[2] = one;
+        *(u16 *)p = full;
+    }
+    p += 0x54;
+    i++;
+    if (i < 8) goto loop;
+}
+```
+Also byte-neutral (all tested at 0): the decompiler names `a0/a2/a1/v1` renamed; `u8 a2`/`u16 a1` widened to `s32`
+(the stores truncate either way); `()` -> `(void)` (the TU's own prototype at src/800_b_2.c:2049 is `(void)`).
+`if (++i < 8) goto loop;` with the pointer declared first scores 4 (ORDER) — keep `i++;` as its own statement.
+
+## (d) GENERATOR PROPOSAL
+When a COUNT residual inside a loop is an extra `addiu rX,rP,K` before the loop plus a second stepped pointer, and the
+`-dL` dump says "Cannot eliminate biv" for the pointer, AND the target hoists nothing that the source does not already
+hold in a local, rewrite the `do { … } while (c);` as `label: … if (c) goto label;` — no LOOP_BEG note, no loop.c
+(loop.c:352-361). The tell in the tree: a `$N` pin on the walked pointer of a do-while whose "constants" are locals
+initialised at the top (the decompiler's rendering of registers loaded before a non-loop.c loop).
+
+## (e) What did not work (bytes)
+- Every structured spelling keeps loop.c: a `for` with inline constants 17, `D_800A49D2[i * 0x54 + K]` indexing 21
+  (three givs), `while (1) { … if (i >= 8) break; }` 18 (still a loop note), the sweep's best (do-while block) 15.
+- The goto loop with `1`/`0x7FFF` inline at the stores: 10 (COUNT 24 — no loop.c means no hoisting, so the constants are
+  rematerialised in the body).
+
+## (f) Where the method fell short
+METHOD §14 says "goto chain -> STRUCTURED" (four closes); this one is the INVERSE — a structured loop that the original
+wrote as a backward goto. No generator emits a goto loop, and the `.loop` dump's "Cannot eliminate biv" line is the
+only place that points at it; the reading "the target has NO loop optimisation at all" (no hoisting, no reduction)
+is the check that distinguishes it from the S103 c2 `q = p + k` case.
+
+## (g) Structs
+No. Giving `D_800A4988` its 0x54-byte record type (u16 @0x4A, u8 @0x4C/0x4D/0x4E) would not remove the biv's direct use
+(the u16 field at the pointer's own offset) nor the loop note; the decision is loop.c's biv elimination, not an
+aggregate/scalar alias question. Byte-wise a struct pointer would also have to start at `D_800A49D2` (the relocation's
+symbol) to stay identical before linking.
@@ -0,0 +1,12 @@
+s32 func_800331D4(s32 arg0) {
+    u16 *p;
+    s32 i;
+
+    p = D_800A46E8;
+    for (i = 0; i < 8; i++, p += 0x2A) {
+        if ((*p & 0x3F) == 1 && p[2] == (arg0 & 0xFFFF) && (((u32)arg0 >> 16) == 0 || ((u32)arg0 >> 16) == p[3])) {
+            return ++i;
+        }
+    }
+    return 0;
+}
@@ -0,0 +1,36 @@
+# func_800331D4 (src/800_b_2.c) — S104 agent e16 — CLOSED at 0, ZERO levers (1 pin -> 0)
+
+## (a) The residual
+Score 9, REG-caller, 30 vs 30: the loop counter `i` and loop.c's second walked pointer (the `p+6` giv) swap `$a1`/`$v1`
+(target: i = `$v1`, giv = `$a1`). Count and order already identical. The exact twin of func_800348A8 (same TU, same
+`D_800A46E8` walk, only the type test differs: `(*p & 0x3F) == 1` vs `p[0] == 5`), which agent e2 closed this session.
+
+## (b) The pass and the decision
+global.c allocation order, `allocno_compare` (global.c:587-603), priority `floor_log2(refs)*refs/live`; refs counted by
+flow weighted by loop depth (flow.c:2067). In the lever-free text the giv outranks `i`, takes `$v1` first. Not re-dumped
+here — the reading is e2's (main__func_800348A8/mechanism.md (b)), and the bytes confirm it on the first `--try`.
+
+## (c) The move that closed it (PROVEN on bytes, first try)
+`return i + 1;` -> `return ++i;` — the increment adds a set and uses of `i` inside the loop (x loop depth), raising its
+priority past the giv's; combine folds `i = i + 1; $v0 = i` back into `addiu v0,v1,1`, zero bytes changed.
+Both spellings score 0: the tree's do-while with only that one line changed (scratch/min.c), and the delivered
+body.c, which also rewrites the do-while as the `for` + one `&&`/`||` condition that func_800348A8 uses (the twin's
+shape; readability).
+
+## (d) GENERATOR PROPOSAL
+When a REG residual swaps a loop counter with another loop-carried pseudo and the counter's only exit use is
+`return i + K;`, rewrite it `return ++i;` (K = 1) — and apply it to every same-TU function that walks the same global
+with that return (grep `return i + 1;` beside `D_800A46E8`).
+
+## (e) What did not work
+Nothing else tried — the first `--try` closed. The sweep (g6b/s3/s3b, 390 compiles) never mutates a return expression's
+side effects, which is why it sat at 9.
+
+## (f) Where the method fell short
+It did not: the brief named e2's close, and the twin was recognisable from the body text alone. `related.txt` lists
+func_800348A8 third (src/800_b_2.c:7060, sharing `D_800A46E8`); a twin_rescan after e2's bank would have remapped this
+one for free.
+
+## (g) Structs
+No. The decision is a refs count in global.c; the `D_800A46E8` record (0x54 bytes: u16 type @0, u16 @4, u16 @6) as a
+struct would re-spell `p[2]`/`p[3]` as fields at the same `(mem (plus p K))` addresses and change nothing here.
@@ -0,0 +1,71 @@
+void func_800336A8(Req336A8 *arg)
+{
+    Chan336A8 *ch;
+    Voice336A8 *vo;
+    u16 *p;
+    const u16 *q;
+    u32 m;
+    u32 n;
+    u32 v;
+    s32 i;
+    s32 j;
+
+    for (i = 0; i < 8; i++) {
+        if (arg->unk3A[i] == 0) {
+            continue;
+        }
+        ch = (Chan336A8 *)(D_800A4988 + i * 0x54);
+        vo = (Voice336A8 *)(D_800A4988 + 0x2A0 + i * 0x48);
+        vo->unk00 = D_80073140[ch->unk0A];
+        m = ch->unk34;
+        m = D_8006AA30[m];
+        m = m * *(s16 *)(D_800A4988 + 0x572);
+        m = m >> 7;
+        if (arg->unk16 != 0) {
+            m = m * arg->unk18;
+            m = m >> 15;
+        }
+        p = arg->unk1C;
+        for (j = 2; j >= 0; j--, p += 4) {
+            m = m * *p;
+            m = m >> 14;
+        }
+        n = ch->unk35;
+        if (n != 0) {
+            if (arg->unk38 != 0) {
+                n += arg->unk38;
+                if (n >= 0x42) {
+                    n -= 0x40;
+                    if (n >= 0x80) {
+                        n = 0x7F;
+                    }
+                } else {
+                    n = 1;
+                }
+            }
+            ch->unk52 = n;
+            if (D_800A4F19 != 0) {
+                v = (m * D_8007319E[n]) >> 14;
+                vo->unk0A = v;
+                q = D_8007319E + 1;
+                v = (m * q[0x7F - n]) >> 14;
+                vo->unk08 = v;
+            } else {
+                v = (m * D_8007321E) >> 14;
+                vo->unk0A = v;
+                vo->unk08 = v;
+            }
+        } else {
+            v = m;
+            vo->unk0A = v;
+            vo->unk08 = v;
+        }
+        vo->unk40 = ch->unk0A;
+        if (vo->unk44 != 0) {
+            vo->unk04 |= 3;
+        } else {
+            vo->unk04 = 3;
+            vo->unk44 = 1;
+        }
+    }
+}
@@ -0,0 +1,58 @@
+# func_800336A8 (src/800_b_2.c) — S104 agent e16 — CLOSED at 0, ZERO levers (1 barrier -> 0)
+
+## (a) The residual
+Score 7 lever-free (sweep best 6), COUNT 120 vs 121: ONE missing `nop` — reorg fills the `beqz v0,<mono>` delay slot of
+the `if (D_800A4F19 != 0)` stereo/mono test with the stereo arm's head `sll v0,v1,1`; the target leaves it empty. Every
+other difference is branch-offset fallout. The tree's lever was a `__asm__ __volatile__("")` at the stereo arm's head
+(ASM_INPUT stops `fill_slots_from_thread`'s scan, `stop_search_p` reorg.c:675-704).
+
+## (b) The pass and the decision
+reorg.c `fill_eager_delay_slots` (reorg.c:3632-3736): `beqz` is an EQ test, `mostly_true_jump` returns 0
+(reorg.c:1407-1408), so the owned fall-through (the stereo arm) is tried first and its head `sll v0,v1,1` is taken
+unless it "sets a resource needed at the opposite thread" (reorg.c:3368-3369, `opposite_needed` from
+`mark_target_live_regs` on the mono arm, reorg.c:2441-2766). The mono arm's head is a 2-word `lui/lhu` (not eligible), so
+nothing else can fill the slot: the target's `nop` means `v0` counted as LIVE at the mono arm.
+
+PROVEN on the `.jump2` dumps (scratch/free.j2 vs scratch/win.j2, both from `tools/cc1_dumps_tu.sh`): the only structural
+difference is where the `n == 0` arm (`v = m;` = `move v0,a1`) is laid out. Lever-free (n == 0 arm first) the mono arm
+falls straight into the shared `sh v0,10/8(a3)` tail. With the n == 0 arm LAST, the mono arm ends in `j L447` over the
+n == 0 arm's `move v0,a1` (label 280), which is the target of the `beqz v1` (n == 0) branch.
+READING (consistent with the bytes, not traced pass by pass): the `beqz v1` branch steals that `move v0,a1` from its
+owned target thread into its own slot (the target's `beqz v1,…; move v0,a1`); `update_block` (reorg.c:2233-2249) leaves
+a `(use (insn move v0,a1))` marker where the move was; once relax deletes the mono arm's `j` to the next active insn
+(reorg.c:3945-3970), the mono arm falls through that marker and `mark_target_live_regs`'s forward scan marks every
+register the marked insn sets as live (reorg.c:2696-2704) — so `v0` is in `opposite_needed` and the `sll` is refused.
+NECESSITY PROVEN on bytes (scratch/v/x1_nomove.c): the same n == 0-last layout with the n == 0 arm storing `m` directly
+(no `move v0,a1` to steal) fills the slot with the `sll` again.
+
+## (c) The move that closed it (PROVEN on bytes, `--try` 0)
+Invert the outer if/else: `if (n == 0) { v = m; … } else { clamp; stereo/mono }` ->
+`if (n != 0) { clamp; stereo/mono } else { v = m; … }`. No other change; the tree's barrier and its comment deleted.
+The bytes are identical because jump/cross-jump/reorg re-derive the same final layout (the n == 0 path still becomes
+`beqz v1,<sh tail>; move v0,a1`).
+
+## (d) GENERATOR PROPOSAL
+When the residual is ONE missing `nop` in a conditional branch's delay slot (the fall-through arm's head stolen) and the
+tree carries a zero-byte `asm("")` barrier at that arm's head, try inverting an ENCLOSING if/else whose trivial arm
+(a register copy + the same stores as a sibling arm) comes first: put the trivial arm last. Its copy gets stolen into
+the outer branch's slot, and the `update_block` USE marker (reorg.c:2233) makes the copied register live at the inner
+branch's target, which denies the steal the barrier was faking. (Arm-order/polarity is residual_moves.md row 10; this is
+the case where the arm to swap is the ENCLOSING one, not the one whose slot differs.)
+
+## (e) What did not work (bytes)
+- Inverting the D_800A4F19 test itself (`== 0` / `!D_800A4F19`, mono first): 25 (mono laid out first).
+- `switch (D_800A4F19)` default-first: 7; case-0-first: 25. A marked `do { stereo } while (0)`: 7 (notes do not stop
+  the scan; the loop's start label is unused and deleted by jump).
+- `if (D_800A4F19 == 0) { mono; goto next; } stereo`: 25. Stereo products into two temps `l`/`r`: 14.
+  `v = m;` hoisted above `if (n == 0)`: 7. `D_8007319E[0x80 - n]` without `q`: 13; `(D_8007319E + 1)[0x7F - n]`: 7.
+- The sweep (320 compiles, R5/R7/R8/R9/R10) never swaps an if/else's arms, which is the move.
+
+## (f) Where the method fell short
+The residual points at the D_800A4F19 branch; the fix is one level OUT (the enclosing `n == 0` if/else). Reading reorg's
+liveness (`mark_target_live_regs` + `update_block`'s markers) from the source is slow and the `.dbr` dump drops the USE
+markers before it is written; an enumeration of "swap every if/else's arms" would have found it in seconds. That
+enumeration belongs in the generator set (it is cheap: one compile per if/else in the body).
+
+## (g) Structs
+No. `Chan336A8`/`Voice336A8`/`Req336A8` are already structs here; the decision is reorg's register liveness across a
+branch, not an aggregate/scalar alias question.
@@ -0,0 +1,122 @@
+s32 func_80034314(u32 arg0, u8 *p, u32 arg2) {
+    u32 flags;
+    Snd54 *e;
+    Rec12 *rec;
+    u8 *q;
+    s16 *pa;
+    s32 idx;
+    s32 ret;
+    s32 i;
+    s32 j;
+    s32 b1;
+    u32 x;
+    u32 y;
+
+    y = arg0 >> 16;
+    flags = arg2;
+    x = arg0;
+    b1 = p[1];
+    if (b1 == 0) {
+        rec = &D_80068A54[p[3]];
+    } else {
+        if (D_800A4EE8 == 0) {
+            return 0;
+        }
+        if (D_800A4EF0 != b1) {
+            return 0;
+        }
+        rec = *(Rec12 **)((u8 *)D_800A4EE8 + 0x18) + p[3];
+    }
+
+    idx = func_800348A8(arg0);
+    if (idx != 0) {
+        ret = idx;
+        idx--;
+        e = (Snd54 *)((u8 *)D_800A46E8 + idx * 0x54);
+        if (flags & 0x1000) {
+            e->unk1C[0].unk06 = 1;
+            e->unk1C[0].unk02 = 0x100;
+            e->unk1C[0].unk04 = ((s32)(flags & 0x7F) * 0x3FFF) >> 7;
+            if (flags & 0x2000) {
+                e->unk38 = D_8006AED8[(flags >> 8) & 0xF];
+            } else {
+                e->unk38 = 0;
+                e->unk39 = 0;
+            }
+            return ret;
+        }
+        if (e->unk08 != 0) {
+            return 0;
+        }
+        func_80034650(e, 0);
+    } else {
+        idx = func_8003310C(rec->unk04);
+        if (idx == 0) {
+            return 0;
+        }
+        ret = idx;
+        idx--;
+        e = (Snd54 *)((u8 *)D_800A46E8 + idx * 0x54);
+    }
+
+    e->unk37 = rec->unk08;
+    e->unk34 = b1;
+    e->unk0C = rec->unk00;
+    e->unk02 = rec->unk04;
+    e->unk10 = e->unk0C;
+    e->unk04 = x;
+    e->unk06 = y;
+    e->unk14 = 1;
+    e->unk17 = p[2];
+    e->unk16 = 0;
+    e->unk18 = 0x7FFF;
+    e->unk08 = rec->unk06;
+    e->unk50 = 0;
+    e->unk52 = 0;
+
+    if (rec->unk08 & 0x10) {
+        e->unk48 = 1;
+    } else {
+        e->unk48 = 0;
+    }
+
+    if (rec->unk08 & 4) {
+        e->unk1A = 0x400;
+    } else if (rec->unk08 & 8) {
+        e->unk1A = 0x200;
+    } else {
+        e->unk1A = 0x5F;
+    }
+    e->unk36 = 0;
+
+    pa = &e->unk1C[0].unk00;
+    for (i = 0; i < 3; i++, pa = (s16 *)((u8 *)pa + 8)) {
+        pa[1] = 0x100;
+        *((u8 *)pa + 6) = 0;
+        if (i != 0) {
+            pa[0] = 0x3FFF;
+            pa[2] = 0x3FFF;
+        } else if (flags & 0x1000) {
+            pa[0] = ((flags & 0x7F) * 0x3FFF) >> 7;
+            pa[2] = ((flags & 0x7F) * 0x3FFF) >> 7;
+            if (flags & 0x2000) {
+                u8 tv = D_8006AED8[(flags >> 8) & 0xF];
+                e->unk38 = tv;
+                e->unk39 = tv;
+            }
+        } else {
+            pa[0] = 0x3FFF;
+            pa[2] = 0x3FFF;
+            e->unk38 = 0;
+            e->unk39 = 0;
+        }
+    }
+
+    q = e->unk3A;
+    for (j = 7; j >= 0; j--) {
+        *q++ = 0;
+    }
+
+    e->unk00 = 5;
+    return ret;
+}
@@ -0,0 +1,50 @@
+# func_80034314 (src/800_b_2.c) — S104 agent e16 — CLOSED at 0, ZERO levers (1 pin -> 0)
+
+## (a) The residual
+Score 27 lever-free (sweep best 23), COUNT 205 vs 207: after EACH of the two calls (`func_800348A8`, `func_8003310C`) the
+target keeps the result in a first register, tests it, and copies it to the long-lived `ret`
+(`move v1,v0; beqz v1,…; move s5,v1; addiu v1,s5,-1`); mine puts the call result straight into `ret`
+(`move s3,v0; beqz s3,…; addiu v1,s3,-1`) — one `move` missing per site. The `s3`/`s5` swap of `p` is fallout of the
+missing pseudo. (The tree faked the survivor with a `$3` pin on `idx`.)
+
+## (b) The pass and the decision (PROVEN on the `.cse` dumps, scratch/dumps_free vs scratch/dumps_win)
+cse's `(set REG0 REG1)` swap, cse.c:7440-7474: the body's `idx = f(); ret = idx;` has the copy IMMEDIATELY after the insn
+that set `idx`, and `ret` is the qty's canonical register (it lives longer and beyond the block, `make_regs_eqv`
+cse.c:840-856), so cse rewrites the pair as `ret = v0; idx = ret;` and the test to `ret == 0`
+(`.cse`: `insn 102 (set (reg 81) v0)`, `insn 105 (set (reg 80) (reg 81))`, `jump_insn 108 … (eq (reg 81) 0)`). `idx`'s
+copy is then dead (it is reassigned `ret - 1` before any read), so one register and one move vanish.
+With the copy AFTER the test (win), the insn before the copy is the jump, not the setter, so the swap's
+`prev … SET_DEST (PATTERN (prev)) == SET_SRC` test (cse.c:7463-7464) fails: `.cse` keeps `(set (reg 80) v0)`,
+`jump_insn 105 … (eq (reg 80) 0)`, `(set (reg 81) (reg 80))`. reorg then pulls each `move s5,v1` into its branch's delay
+slot (EQ site: from the fall-through head, `fill_eager_delay_slots` reorg.c:3713-3718; NE site: from the target head,
+predicted taken, reorg.c:3690-3695), which is why the copy looked like it came before the test.
+
+## (c) The moves that closed it (PROVEN on bytes; JOINT — both sites needed)
+1. `idx = func_800348A8(arg0); ret = idx; if (idx != 0) { idx = ret - 1;` ->
+   `idx = func_800348A8(arg0); if (idx != 0) { ret = idx; idx--;`
+2. `idx = func_8003310C(…); ret = idx; if (idx == 0) return 0; idx = ret - 1;` ->
+   `idx = func_8003310C(…); if (idx == 0) return 0; ret = idx; idx--;`
+Site 1 alone: 25 (worse than the start — METHOD step 5). `idx = ret - 1;` and `idx--;` both score 0; `idx--` delivered.
+Also dropped (byte-neutral): the two orphan comments "dbr fence …" and "sched fence …" — they described launder levers
+that sites.txt lists as REMOVED and that are no longer in the body (flagged here so the drop is not silent).
+
+## (d) GENERATOR PROPOSAL
+When a COUNT residual is one missing `move` right after a call (target: `move vA,v0; b?? vA; move sK,vA`) and the body
+reads `x = call(); y = x; if (x …)`, move the copy `y = x;` past the test into the arm(s) where `y` is needed (after an
+early `return`), at every such site at once: the cse.c:7440 swap needs the copy to sit immediately after its source's
+setter. (A variant of generator R21 — "separate the copy from its producer" — where the separating statement is the
+test itself; R21's reorders stay within straight-line statements and so did not reach it.)
+
+## (e) What did not work (bytes)
+- Only the first site changed: 25. `e = D + (idx - 1) * 0x54` with no `idx` reassignment: 25 (idx then dies at the copy
+  again; the target needs `idx` reassigned from `ret`).
+- The sweep's 325 compiles (width `u16` counter + do-while, decl moves, block/do-while wrappers, param copies): 23.
+
+## (f) Where the method fell short
+The residual's "register pairs" line (s5->s3, s3->v1) reads as a register permutation; the fact is a missing pseudo
+(COUNT 205 vs 207). METHOD step 2 ("COUNT FIRST") was the right entry; the S103 c-list "a copy cse deleted because the
+producer sat immediately before it" named the class — the only new part is that the fix is moving the copy past a branch.
+
+## (g) Structs
+No. `Snd54`/`Rec12` are already structs; the decision is cse's register-copy canonicalisation, not an aggregate/scalar
+alias question, and no field access is involved in the defect.
@@ -1,7 +1,7 @@
 {
- "head": "8a344a8c3",
+ "head": "8cdc07612",
 "stamp": "15956e4a96c4",
- "generated": "2026-09-11 02:28",
+ "generated": "2026-09-11 02:33",
 "aliases": [
  "main",
  "ov_SC03_014",
@@ -21,206 +21,206 @@
  "main": {
   "objects": 85,
   "identical": 85,
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-   "mean_s": 0.075
+   "seconds": 6.5950000000000015,
+   "mean_s": 0.078
  },
  "ov_SC03_014": {
   "objects": 32,
   "identical": 32,
-   "seconds": 4.447999999999999,
-   "mean_s": 0.139
+   "seconds": 4.468999999999999,
+   "mean_s": 0.14
  },
  "ov_SC03_015": {
   "objects": 32,
   "identical": 32,
-   "seconds": 4.4670000000000005,
-   "mean_s": 0.14
+   "seconds": 4.237999999999999,
+   "mean_s": 0.132
  },
  "ov_SC04_011": {
   "objects": 28,
   "identical": 28,
-   "seconds": 3.9239999999999995,
-   "mean_s": 0.14
+   "seconds": 3.7610000000000006,
+   "mean_s": 0.134
  }
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  "build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.054,
-  "build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.054
+  "build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.048
 },
 "ok": true,
 "seconds": 2.2
@@ -5654,19 +5654,14 @@ extern u16 D_800A46E8[];

 s32 func_800331D4(s32 arg0) {
    u16 *p;
-    register s32 i __asm__("$3");  // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9)
+    s32 i;

    p = D_800A46E8;
-    i = 0;
-    do {
-        if ((*p & 0x3F) == 1 && p[2] == (arg0 & 0xFFFF)) {
-            if (((u32)arg0 >> 16) == 0 || ((u32)arg0 >> 16) == p[3]) {
-                return i + 1;
-            }
+    for (i = 0; i < 8; i++, p += 0x2A) {
+        if ((*p & 0x3F) == 1 && p[2] == (arg0 & 0xFFFF) && (((u32)arg0 >> 16) == 0 || ((u32)arg0 >> 16) == p[3])) {
+            return ++i;
        }
-        i += 1;
-        p += 42;
-    } while (i < 8);
+    }
    return 0;
 }