mirror of
https://github.com/Druthulu/BFM-decomp
synced 2026-10-02 07:59:52 -04:00
phase-36: S104 d5 — func_801837E8 at 0 levers (was 1 $2 pin): the hoisted +0xFC temp folded into a compound assignment so the left side is born first (local-alloc.c:1486-1507, block_alloc's three-quantity order is by birth, not a sort); gate IDENTICAL each
This commit is contained in:
Drew T
@@ -0,0 +1,85 @@
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void func_801837E8(s32 a0) {
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s32 state;
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s32 fv;
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state = *(u16 *)(a0 + 0x34);
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if (state == 1) {
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goto case1;
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}
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if (state < 2) {
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if (state == 0) {
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goto case0;
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}
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goto tail;
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}
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if (state == 2) {
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goto case2;
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}
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if (state == 3) {
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goto case3;
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}
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goto tail;
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case0: {
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if (func_8012BEE8(a0) == 0) {
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goto tail;
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}
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*(u16 *)(a0 + 0xFC) = 0;
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*(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;
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fv = rand();
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fv = (fv & 0x1F) + 0x1E;
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goto store1c;
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}
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case1: {
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s32 v0;
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s32 p;
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v0 = *(u16 *)(a0 + 0xFC);
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p = *(s32 *)(a0 + 0x20);
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v0 = v0 + 6;
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*(u16 *)(a0 + 0xFC) = v0;
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*(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;
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if (func_8012BEE8(a0) == 0) {
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goto tail;
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}
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*(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;
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goto randtail;
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}
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case2: {
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s32 p;
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p = *(s32 *)(a0 + 0x20);
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*(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);
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if (func_8012BEE8(a0) == 0) {
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goto tail;
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}
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*(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;
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goto tail;
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}
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case3: {
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s32 v0;
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s32 p;
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v0 = *(u16 *)(a0 + 0xFC);
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p = *(s32 *)(a0 + 0x20);
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v0 = v0 - 3;
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*(u16 *)(a0 + 0xFC) = v0;
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*(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;
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if (*(s16 *)(a0 + 0xFC) >= 9) {
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goto tail;
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}
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*(u16 *)(a0 + 0x34) = 0;
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}
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randtail:
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fv = rand();
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fv = (fv & 0x3F) + 0x3C;
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store1c:
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*(s32 *)(a0 + 0x1C) = fv;
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tail:
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if (!((u32)func_80029504() < 0x492)) {
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func_8012C218((void *)a0);
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}
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}
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@@ -0,0 +1,92 @@
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# func_801837E8 (ov_SC05_018_jr_8017D604.c) — P36 T7 S104 agent d5
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**Result: score 0 in plain C, no levers** (before: 1 lever, the `register s32 p __asm__("$2")` pin in case2; after: 0).
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Took one `--try`; four spellings reach 0 (below). `PACK/body.c` = variant **b**.
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The move (case2 only): delete the hoisted temp `v0` and write the update as a compound assignment, so the `+0xFC` read comes
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after the lhs load:
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```c
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s32 p;
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p = *(s32 *)(a0 + 0x20);
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*(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);
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```
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## (a) The residual
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Same 94 instructions. In case2's block, three block-local pseudos are permuted: the pointer `p` (`lw 32(s0)`), the `+0xFC`
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value `fc` and the tied load/sum `ld/sum` (`lhu 18(p)` + the `addu`). Mine: ld/sum=$v0, fc=$v1, p=$a1. Target: p=$v0,
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ld/sum=$v1, fc=$a1. No instruction is missing (counted first: 94/94, same mnemonics in the same order).
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## (b) The pass and the decision (PROVEN on dumps + bytes)
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local-alloc, `block_alloc`, **the special case for exactly three quantities**, `local-alloc.c:1486-1507` (the same code for the
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suggested-register pass is at `:1439-1462`):
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```c
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case 3:
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if (qty_compare (0, 1) > 0) EXCHANGE (0, 1);
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if (qty_compare (1, 2) > 0) EXCHANGE (2, 1);
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case 2:
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if (qty_compare (0, 1) > 0) EXCHANGE (0, 1);
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```
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`EXCHANGE` swaps *positions* in `qty_order`, but `qty_compare` is always called on the fixed *qty numbers* 0, 1, 2, and qty
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numbers are handed out in BIRTH order while the block is scanned. This is not a sort. Worked out for a block with exactly
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three qtys (pri = `qty_compare`'s floor_log2(refs)·refs/len):
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- pri1 > pri0 and pri2 > pri1 → order [q2, q1, q0]
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- pri1 > pri0 and pri2 ≤ pri1 → order **[q0, q1, q2]** (q0 goes first even though q1 ranks higher)
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- pri1 ≤ pri0 → [q0, q1, q2], or [q0, q2, q1] when pri2 > pri1.
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So **the first-born qty is allocated first unless the priorities strictly increase in birth order.** `find_free_reg` then
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hands out the lowest free register ($2, $3, then $5, because `$a0` is live for the call argument).
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Case2's priorities (`.lreg`, block 11): p 3000 (3 refs), fc 3333/5000, ld/sum 13333/10000 (tied, 4 refs).
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- **body_free**: the source reads `v0 = +0xFC` BEFORE the lhs load, so expand emits fc, p, ld (`.rtl`); sched1 hoists p
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but ld still comes after fc. Births: q0=p, q1=fc, q2=ld/sum. 3333>3000 and 13333>3333 → [ld/sum, fc, p] → ld/sum $2, fc $3,
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p $5 (the residual).
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- **body.c**: the compound assignment evaluates its lhs first (`lhs = lhs + rhs`, PLUS_EXPR operand 0 expanded first), so
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expand emits p, ld, fc (`.rtl`). Births: q0=p, q1=ld/sum, q2=fc. 10000>3000 but 5000<10000 → [p, ld/sum, fc] → p $2,
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ld/sum $3, fc $5 = the target.
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Byte evidence: the dump of the matching body shows `;; Register 93 in 2` (p) while a correct sort would give it $5.
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body.c's own dump (`PACK/scratch/dumps_b/`) prints q0=p 3000, q1=ld/sum 10000, q2=fc 5000; the patched simulator matches it
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(0 mismatches) and the shipped one does not (3).
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**Tool defect found (`tools/localalloc_sim.py`)**: it ranks every block with a full sort, so it gets this block wrong
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(3 mismatches on the matching body, and it predicts the *residual*). A scratch copy with the three-qty rule added,
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`PACK/scratch/lsim3.py` (a 10-line change right before the `for q in ids:` allocation loop), gives 0 mismatches on every block
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of func_801837E8 in both dumps. Over the whole TU dump (1,058 blocks, via `PACK/scratch/scan.py`) the three-qty blocks with
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a mismatch drop from 10–11 of 40 to 6, and blocks of any other size stay the same. All 6 left are in func_8017D604, and the
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one I read is a separate defect: the simulator gives a qty its suggested register `$30`, which `find_free_reg` never hands out
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(eliminable/frame register, `local-alloc.c` find_free_reg `ELIMINABLE_REGS`). **Recommend promoting the three-qty rule into
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localalloc_sim.py** (it also applies to the suggested-register pass order, `:1439-1462`, which the simulator also fully sorts).
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## (c) Source moves that close it (all score 0)
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- **b** (body.c): `p = *(s32 *)(a0 + 0x20); *(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);`
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- a: `*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) += *(u16 *)(a0 + 0xFC);` (no locals)
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- e: `p = …; *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + *(u16 *)(a0 + 0xFC);` (the long form: only the operand ORDER matters)
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- d: the fully nested long form.
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Also s1/s3: the same compound with a body-local struct pointer (`p->f12 += s->fFC`) → 0.
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## (d) Generator proposal
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When a register residual is a permutation inside one basic block that has **exactly three local qtys** (the `.lreg` block
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has three `Register N in M` locals) and the first-born qty is the one the target puts in the lowest register, re-order the
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block's source so its birth order gives the three-qty rule's result: **inline a hoisted single-use rhs temp (`v = *(T*)(b+K);
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… x = x + v;`) into its use, placed after the lhs load (`x += *(T*)(b+K)`)**. More generally, try each of the 3! birth
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orders (inline or hoist the temps) and predict the result with the fixed-index rule before compiling.
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## (e) What did not work (bytes)
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- c: `p` read first, then `v0 = +0xFC`, then the long form → 5 (fc is still born before ld).
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- s2: struct pointer with the hoisted `v0` temp (`v0 = s->fFC; p->f12 += v0;`) → 5. The struct does not fix it; the order does.
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- free_000 (swap the `+` operands, `v0 + *(p+0x12)`) → 5: the tie moves (sum ties to operand 1), but fc is still born second.
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- The sweep's R8/R9 moves (history.txt, best 4) reorder statements but always keep a hoisted fc temp born before the ld.
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## (f) Where the method fell short
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- Step 1 sends me to `localalloc_sim.py` for a per-block permutation, and for exactly this shape it gives the wrong answer
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(it predicts the residual for the matching body). The fixed-index three-qty order is not in `residual_moves.md`, and no
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simulator has it. Reading `block_alloc` from its sort onward, not only `qty_compare_1`, found it.
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- The first move to try came from asking "what would the original `obj->f += self->g` look like": the decompiler's hoisted
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rhs temp was the lever, and the pin was compensating for it.
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## (g) Structs question
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No. The decision is **evaluation order** (which qty is born second), not the access type. Tested with body-local structs: a
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struct pointer with the compound assignment → 0 (s1, s3), and a struct pointer with the hoisted temp → 5 (s2). The
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`expr.c:4568-4577` aggregate channel (alias/dependence) plays no part: nothing here reorders a load across a store. Struct
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typing would help *indirectly*, though: the natural struct spelling of this line is `self->obj->f12 += self->fFC;`, which is
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the matching order, while the cast-soup decompile hoisted the rhs into a temp. So a struct pass makes the right C shape the
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obvious one. The candidate types: the actor at `a0` (u16 state `+0x34`, s32 `+0x1C`, `obj *` `+0x20`, s16 `+0xFC`, read with
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`lh` for the `< 9` test) and the object at `+0x20` (u16/s16 `+0x12`). But the pin itself did not need structs.
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+186
-186
@@ -1,7 +1,7 @@
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{
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||||
"head": "547571fd1",
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"head": "f644ecb9d",
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||||
"stamp": "15956e4a96c4",
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||||
"generated": "2026-09-10 21:10",
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"generated": "2026-09-10 21:11",
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||||
"aliases": [
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||||
"main",
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||||
"ov_SC03_014",
|
||||
@@ -21,206 +21,206 @@
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||||
"main": {
|
||||
"objects": 85,
|
||||
"identical": 85,
|
||||
"seconds": 10.635000000000002,
|
||||
"mean_s": 0.125
|
||||
"seconds": 10.268000000000004,
|
||||
"mean_s": 0.121
|
||||
},
|
||||
"ov_SC03_014": {
|
||||
"objects": 32,
|
||||
"identical": 32,
|
||||
"seconds": 7.177999999999999,
|
||||
"mean_s": 0.224
|
||||
"seconds": 6.941000000000002,
|
||||
"mean_s": 0.217
|
||||
},
|
||||
"ov_SC03_015": {
|
||||
"objects": 32,
|
||||
"identical": 32,
|
||||
"seconds": 6.9430000000000005,
|
||||
"mean_s": 0.217
|
||||
"seconds": 6.563000000000002,
|
||||
"mean_s": 0.205
|
||||
},
|
||||
"ov_SC04_011": {
|
||||
"objects": 28,
|
||||
"identical": 28,
|
||||
"seconds": 6.312,
|
||||
"mean_s": 0.225
|
||||
"seconds": 6.0840000000000005,
|
||||
"mean_s": 0.217
|
||||
}
|
||||
},
|
||||
"per_object_seconds": {
|
||||
"build/src/800.o": 1.183,
|
||||
"build/src/800_b.o": 0.169,
|
||||
"build/src/800_b_2.o": 0.616,
|
||||
"build/src/800_b_o0a.o": 0.128,
|
||||
"build/src/800_c.o": 0.32,
|
||||
"build/src/800b2.o": 0.188,
|
||||
"build/src/apicard1.o": 0.084,
|
||||
"build/src/apicard2.o": 0.104,
|
||||
"build/src/apicard3.o": 0.093,
|
||||
"build/src/apicard4.o": 0.129,
|
||||
"build/src/apicard5.o": 0.097,
|
||||
"build/src/apicard6.o": 0.117,
|
||||
"build/src/apicard7.o": 0.109,
|
||||
"build/src/boot.o": 0.146,
|
||||
"build/src/gap.o": 0.081,
|
||||
"build/src/libapi1.o": 0.083,
|
||||
"build/src/800.o": 0.987,
|
||||
"build/src/800_b.o": 0.145,
|
||||
"build/src/800_b_2.o": 0.443,
|
||||
"build/src/800_b_o0a.o": 0.125,
|
||||
"build/src/800_c.o": 0.304,
|
||||
"build/src/800b2.o": 0.099,
|
||||
"build/src/apicard1.o": 0.115,
|
||||
"build/src/apicard2.o": 0.101,
|
||||
"build/src/apicard3.o": 0.074,
|
||||
"build/src/apicard4.o": 0.081,
|
||||
"build/src/apicard5.o": 0.096,
|
||||
"build/src/apicard6.o": 0.092,
|
||||
"build/src/apicard7.o": 0.105,
|
||||
"build/src/boot.o": 0.185,
|
||||
"build/src/gap.o": 0.148,
|
||||
"build/src/libapi1.o": 0.148,
|
||||
"build/src/libapi2.o": 0.086,
|
||||
"build/src/libc2_1.o": 0.094,
|
||||
"build/src/libc2_2.o": 0.075,
|
||||
"build/src/libcd1.o": 0.111,
|
||||
"build/src/libcd2.o": 0.079,
|
||||
"build/src/libetc.o": 0.094,
|
||||
"build/src/libgpu.o": 0.143,
|
||||
"build/src/libgpu2.o": 0.101,
|
||||
"build/src/libgs1.o": 0.077,
|
||||
"build/src/libgs2.o": 0.146,
|
||||
"build/src/libgs3.o": 0.07,
|
||||
"build/src/libgs4.o": 0.106,
|
||||
"build/src/libgs5.o": 0.083,
|
||||
"build/src/libgs6.o": 0.1,
|
||||
"build/src/libgs7.o": 0.094,
|
||||
"build/src/libgs8.o": 0.114,
|
||||
"build/src/libgte1.o": 0.084,
|
||||
"build/src/libgte10.o": 0.077,
|
||||
"build/src/libgte11.o": 0.113,
|
||||
"build/src/libgte12.o": 0.092,
|
||||
"build/src/libgte13.o": 0.118,
|
||||
"build/src/libgte14.o": 0.099,
|
||||
"build/src/libgte15.o": 0.082,
|
||||
"build/src/libgte16.o": 0.091,
|
||||
"build/src/libgte17.o": 0.087,
|
||||
"build/src/libgte18.o": 0.121,
|
||||
"build/src/libgte19.o": 0.168,
|
||||
"build/src/libgte2.o": 0.092,
|
||||
"build/src/libgte20.o": 0.118,
|
||||
"build/src/libgte21.o": 0.12,
|
||||
"build/src/libgte22.o": 0.096,
|
||||
"build/src/libgte23.o": 0.124,
|
||||
"build/src/libgte24.o": 0.07,
|
||||
"build/src/libgte25.o": 0.081,
|
||||
"build/src/libgte26.o": 0.095,
|
||||
"build/src/libgte27.o": 0.122,
|
||||
"build/src/libgte28.o": 0.09,
|
||||
"build/src/libgte29.o": 0.097,
|
||||
"build/src/libgte3.o": 0.086,
|
||||
"build/src/libgte30.o": 0.08,
|
||||
"build/src/libgte4.o": 0.089,
|
||||
"build/src/libgte5.o": 0.105,
|
||||
"build/src/libgte6.o": 0.123,
|
||||
"build/src/libgte7.o": 0.092,
|
||||
"build/src/libgte8.o": 0.15,
|
||||
"build/src/libgte9.o": 0.088,
|
||||
"build/src/libmcrd1.o": 0.098,
|
||||
"build/src/libmcrd2.o": 0.118,
|
||||
"build/src/libpad1.o": 0.077,
|
||||
"build/src/libpad2.o": 0.093,
|
||||
"build/src/sgap.o": 0.137,
|
||||
"build/src/sgap_2.o": 0.095,
|
||||
"build/src/sgap_3.o": 0.094,
|
||||
"build/src/sgap_4.o": 0.122,
|
||||
"build/src/sgap_5.o": 0.13,
|
||||
"build/src/sgap_6.o": 0.088,
|
||||
"build/src/sgap_8.o": 0.111,
|
||||
"build/src/snd1.o": 0.107,
|
||||
"build/src/snd10.o": 0.109,
|
||||
"build/src/snd11.o": 0.124,
|
||||
"build/src/snd12.o": 0.11,
|
||||
"build/src/snd2.o": 0.083,
|
||||
"build/src/snd3.o": 0.088,
|
||||
"build/src/snd4.o": 0.081,
|
||||
"build/src/snd5.o": 0.114,
|
||||
"build/src/snd6.o": 0.126,
|
||||
"build/src/snd7.o": 0.084,
|
||||
"build/src/snd8.o": 0.081,
|
||||
"build/src/snd9.o": 0.095,
|
||||
"build/src/ov_SC03_014/ov_SC03_014.o": 0.289,
|
||||
"build/src/ov_SC03_014/ov_SC03_014_after.o": 0.665,
|
||||
"build/src/ov_SC03_014/ov_SC03_014_jr_8012ACE0.o": 0.571,
|
||||
"build/src/ov_SC03_014/ov_SC03_014_jr_80135888.o": 0.158,
|
||||
"build/src/ov_SC03_014/ov_SC03_014_jr_80135A4C.o": 0.088,
|
||||
"build/src/ov_SC03_014/ov_SC03_014_jr_80135D20.o": 0.174,
|
||||
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"build/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.o": 0.152,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.097,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.092,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.256,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.083,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.263,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.151,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.124,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.126,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.133,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.596,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.329,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.134,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.256,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.076,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.171,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.113,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.161,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.755,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.086,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.087
|
||||
},
|
||||
"ok": true,
|
||||
"seconds": 3.8
|
||||
|
||||
@@ -29055,3 +29055,7 @@
|
||||
{"ts": "2026-09-10 21:11:44", "label": "s104_d3", "rung": "E", "calib": {"head": "547571fd1", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_011/ov_SC06_011_jr_8017EEEC.c", "fn": "func_8017F3C8", "addr": 2149053384, "aliases": null, "header": false, "includers": 0, "nhash_before": "0ca9f9d76b6711cb03e1602d2b539a6316fec523", "nhash_after": "eb6dd7bc00bbee44c90267704ec1a8ba9707336e", "source": "propagate:src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c:func_8017FB4C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.066, "objects": ["build/src/ov_SC06_011/ov_SC06_011_jr_8017EEEC.o"], "before_text": "void func_8017F3C8(void *a0)\n{\n void *s3 = a0;\n void *s2;\n void *p;\n s32 v1;\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 bits;\n s32 s0;\n s32 s1;\n\n s2 = *(void **)((s32)s3 + 0x20);\n func_8017F5F0(s3);\n p = (*(void * *)&D_801ABBD8);\n if (p == 0) {\n goto END;\n }\n v0 = *(u16 *)((s32)s2 + 0x12) + 0x800;\n p = *(void **)((s32)p + 0x20);\n bits = *(u16 *)((s32)p + 0x12) & 0x400;\n s0 = v0 & 0xFFF;\n if (bits == 0) {\n goto ELSE;\n }\n s1 = func_80012A60(s0, 0x400);\n v0 = func_80012A60(s0, 0xC00);\n v1 = (s16)s1;\n v0 = (s16)v0;\n v0 = (v0 < v1);\n if (v0 != 0) {\n goto TRUE1;\n }\n v0 = 0x400;\n goto STORE;\nTRUE1:\n v0 = 0xC00;\n goto STORE;\nELSE:\n s1 = func_80012A60(s0, 0);\n v0 = func_80012A60(s0, 0x800);\n v1 = (s16)s1;\n v0 = (s16)v0;\n v0 = (v0 < v1);\n if (v0 != 0) {\n goto TRUE2;\n }\n *(u16 *)((s32)s2 + 0x12) = 0;\n goto END;\nTRUE2:\n v0 = 0x800;\nSTORE:\n *(u16 *)((s32)s2 + 0x12) = v0;\nEND:\n func_80171990((u8 *)s3);\n}\n", "after_text": "void func_8017F3C8(void *a0)\n{\n void *s2 = *(void **)((s32)a0 + 0x20);\n void *p;\n s32 rot;\n s32 flag;\n s32 angle;\n s32 a;\n s32 b;\n\n func_8017F5F0(a0);\n p = (void *)D_801ABBD8;\n if (p != 0) {\n rot = *(u16 *)((s32)s2 + 0x12) + 0x800;\n p = *(void **)((s32)p + 0x20);\n flag = *(u16 *)((s32)p + 0x12) & 0x400;\n angle = rot & 0xFFF;\n if (flag) {\n a = func_80012A60(angle, 0x400);\n b = func_80012A60(angle, 0xC00);\n if ((s16)a <= (s16)b) {\n *(u16 *)((s32)s2 + 0x12) = 0x400;\n } else {\n *(u16 *)((s32)s2 + 0x12) = 0xC00;\n }\n } else {\n a = func_80012A60(angle, 0);\n b = func_80012A60(angle, 0x800);\n if ((s16)a <= (s16)b) {\n *(u16 *)((s32)s2 + 0x12) = 0;\n } else {\n *(u16 *)((s32)s2 + 0x12) = 0x800;\n }\n }\n }\n func_80171990((u8 *)a0);\n}\n"}
|
||||
{"ts": "2026-09-10 21:11:45", "label": "s104_d3", "rung": "E", "calib": {"head": "547571fd1", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.c", "fn": "func_8017E7E8", "addr": 2149050344, "aliases": null, "header": false, "includers": 0, "nhash_before": "0ca9f9d76b6711cb03e1602d2b539a6316fec523", "nhash_after": "eb6dd7bc00bbee44c90267704ec1a8ba9707336e", "source": "propagate:src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c:func_8017FB4C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.152, "objects": ["build/src/ov_SC06_013/ov_SC06_013_jr_8017BEBC.o"], "before_text": "void func_8017E7E8(void *a0)\n{\n void *s3 = a0;\n void *s2;\n void *p;\n s32 v1;\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 bits;\n s32 s0;\n s32 s1;\n\n s2 = *(void **)((s32)s3 + 0x20);\n func_8017EA10(s3);\n p = (*(void * *)&D_8019AA90);\n if (p == 0) {\n goto END;\n }\n v0 = *(u16 *)((s32)s2 + 0x12) + 0x800;\n p = *(void **)((s32)p + 0x20);\n bits = *(u16 *)((s32)p + 0x12) & 0x400;\n s0 = v0 & 0xFFF;\n if (bits == 0) {\n goto ELSE;\n }\n s1 = func_80012A60(s0, 0x400);\n v0 = func_80012A60(s0, 0xC00);\n v1 = (s16)s1;\n v0 = (s16)v0;\n v0 = (v0 < v1);\n if (v0 != 0) {\n goto TRUE1;\n }\n v0 = 0x400;\n goto STORE;\nTRUE1:\n v0 = 0xC00;\n goto STORE;\nELSE:\n s1 = func_80012A60(s0, 0);\n v0 = func_80012A60(s0, 0x800);\n v1 = (s16)s1;\n v0 = (s16)v0;\n v0 = (v0 < v1);\n if (v0 != 0) {\n goto TRUE2;\n }\n *(u16 *)((s32)s2 + 0x12) = 0;\n goto END;\nTRUE2:\n v0 = 0x800;\nSTORE:\n *(u16 *)((s32)s2 + 0x12) = v0;\nEND:\n func_80171990((u8 *)s3);\n}\n", "after_text": "void func_8017E7E8(void *a0)\n{\n void *s2 = *(void **)((s32)a0 + 0x20);\n void *p;\n s32 rot;\n s32 flag;\n s32 angle;\n s32 a;\n s32 b;\n\n func_8017EA10(a0);\n p = (void *)D_8019AA90;\n if (p != 0) {\n rot = *(u16 *)((s32)s2 + 0x12) + 0x800;\n p = *(void **)((s32)p + 0x20);\n flag = *(u16 *)((s32)p + 0x12) & 0x400;\n angle = rot & 0xFFF;\n if (flag) {\n a = func_80012A60(angle, 0x400);\n b = func_80012A60(angle, 0xC00);\n if ((s16)a <= (s16)b) {\n *(u16 *)((s32)s2 + 0x12) = 0x400;\n } else {\n *(u16 *)((s32)s2 + 0x12) = 0xC00;\n }\n } else {\n a = func_80012A60(angle, 0);\n b = func_80012A60(angle, 0x800);\n if ((s16)a <= (s16)b) {\n *(u16 *)((s32)s2 + 0x12) = 0;\n } else {\n *(u16 *)((s32)s2 + 0x12) = 0x800;\n }\n }\n }\n func_80171990((u8 *)a0);\n}\n"}
|
||||
{"ts": "2026-09-10 21:11:45", "label": "s104_d3", "rung": "E", "calib": {"head": "547571fd1", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.c", "fn": "func_8017E6A4", "addr": 2149050020, "aliases": null, "header": false, "includers": 0, "nhash_before": "0ca9f9d76b6711cb03e1602d2b539a6316fec523", "nhash_after": "eb6dd7bc00bbee44c90267704ec1a8ba9707336e", "source": "propagate:src/ov_SC06_014/ov_SC06_014_jr_8017BEBC.c:func_8017FB4C", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.121, "objects": ["build/src/ov_SC06_015/ov_SC06_015_jr_8017BEBC.o"], "before_text": "void func_8017E6A4(void *a0)\n{\n void *s3 = a0;\n void *s2;\n void *p;\n s32 v1;\n register s32 v0 __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 bits;\n s32 s0;\n s32 s1;\n\n s2 = *(void **)((s32)s3 + 0x20);\n func_8017E8CC(s3);\n p = (*(void * *)&D_80194888);\n if (p == 0) {\n goto END;\n }\n v0 = *(u16 *)((s32)s2 + 0x12) + 0x800;\n p = *(void **)((s32)p + 0x20);\n bits = *(u16 *)((s32)p + 0x12) & 0x400;\n s0 = v0 & 0xFFF;\n if (bits == 0) {\n goto ELSE;\n }\n s1 = func_80012A60(s0, 0x400);\n v0 = func_80012A60(s0, 0xC00);\n v1 = (s16)s1;\n v0 = (s16)v0;\n v0 = (v0 < v1);\n if (v0 != 0) {\n goto TRUE1;\n }\n v0 = 0x400;\n goto STORE;\nTRUE1:\n v0 = 0xC00;\n goto STORE;\nELSE:\n s1 = func_80012A60(s0, 0);\n v0 = func_80012A60(s0, 0x800);\n v1 = (s16)s1;\n v0 = (s16)v0;\n v0 = (v0 < v1);\n if (v0 != 0) {\n goto TRUE2;\n }\n *(u16 *)((s32)s2 + 0x12) = 0;\n goto END;\nTRUE2:\n v0 = 0x800;\nSTORE:\n *(u16 *)((s32)s2 + 0x12) = v0;\nEND:\n func_80171990((u8 *)s3);\n}\n", "after_text": "void func_8017E6A4(void *a0)\n{\n void *s2 = *(void **)((s32)a0 + 0x20);\n void *p;\n s32 rot;\n s32 flag;\n s32 angle;\n s32 a;\n s32 b;\n\n func_8017E8CC(a0);\n p = (void *)D_80194888;\n if (p != 0) {\n rot = *(u16 *)((s32)s2 + 0x12) + 0x800;\n p = *(void **)((s32)p + 0x20);\n flag = *(u16 *)((s32)p + 0x12) & 0x400;\n angle = rot & 0xFFF;\n if (flag) {\n a = func_80012A60(angle, 0x400);\n b = func_80012A60(angle, 0xC00);\n if ((s16)a <= (s16)b) {\n *(u16 *)((s32)s2 + 0x12) = 0x400;\n } else {\n *(u16 *)((s32)s2 + 0x12) = 0xC00;\n }\n } else {\n a = func_80012A60(angle, 0);\n b = func_80012A60(angle, 0x800);\n if ((s16)a <= (s16)b) {\n *(u16 *)((s32)s2 + 0x12) = 0;\n } else {\n *(u16 *)((s32)s2 + 0x12) = 0x800;\n }\n }\n }\n func_80171990((u8 *)a0);\n}\n"}
|
||||
{"ts": "2026-09-10 21:12:27", "label": "s104_d5", "rung": "E", "calib": {"head": "f644ecb9d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC05_018/ov_SC05_018_jr_8017D604.c", "fn": "func_801837E8", "addr": 2149070824, "aliases": null, "header": false, "includers": 0, "nhash_before": "e7517d4e13cd1351e8d370f35ec75fe121591d96", "nhash_after": "0f2b8c264acc441d17eb016feede2076816f1699", "source": ".run/P36/agents/ov_SC05_018__func_801837E8/body.c", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.358, "objects": ["build/src/ov_SC05_018/ov_SC05_018_jr_8017D604.o"], "before_text": "void func_801837E8(s32 a0) {\n s32 state;\n s32 fv;\n\n state = *(u16 *)(a0 + 0x34);\n if (state == 1) {\n goto case1;\n }\n if (state < 2) {\n if (state == 0) {\n goto case0;\n }\n goto tail;\n }\n if (state == 2) {\n goto case2;\n }\n if (state == 3) {\n goto case3;\n }\n goto tail;\n\ncase0: {\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0xFC) = 0;\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n fv = rand();\n fv = (fv & 0x1F) + 0x1E;\n goto store1c;\n}\n\ncase1: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 + 6;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto randtail;\n}\n\ncase2: {\n register s32 p __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n s32 v0;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto tail;\n}\n\ncase3: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 - 3;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (*(s16 *)(a0 + 0xFC) >= 9) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = 0;\n}\n\nrandtail:\n fv = rand();\n fv = (fv & 0x3F) + 0x3C;\n\nstore1c:\n *(s32 *)(a0 + 0x1C) = fv;\n\ntail:\n if (!((u32)func_80029504() < 0x492)) {\n func_8012C218((void *)a0);\n }\n}\n", "after_text": "void func_801837E8(s32 a0) {\n s32 state;\n s32 fv;\n\n state = *(u16 *)(a0 + 0x34);\n if (state == 1) {\n goto case1;\n }\n if (state < 2) {\n if (state == 0) {\n goto case0;\n }\n goto tail;\n }\n if (state == 2) {\n goto case2;\n }\n if (state == 3) {\n goto case3;\n }\n goto tail;\n\ncase0: {\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0xFC) = 0;\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n fv = rand();\n fv = (fv & 0x1F) + 0x1E;\n goto store1c;\n}\n\ncase1: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 + 6;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto randtail;\n}\n\ncase2: {\n s32 p;\n p = *(s32 *)(a0 + 0x20);\n *(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto tail;\n}\n\ncase3: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 - 3;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (*(s16 *)(a0 + 0xFC) >= 9) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = 0;\n}\n\nrandtail:\n fv = rand();\n fv = (fv & 0x3F) + 0x3C;\n\nstore1c:\n *(s32 *)(a0 + 0x1C) = fv;\n\ntail:\n if (!((u32)func_80029504() < 0x492)) {\n func_8012C218((void *)a0);\n }\n}\n"}
|
||||
{"ts": "2026-09-10 21:12:56", "label": "s104_d5", "rung": "E", "calib": {"head": "f644ecb9d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_125/ov_SC03_125_jr_8017D604.c", "fn": "func_80180F0C", "addr": 2149060364, "aliases": null, "header": false, "includers": 0, "nhash_before": "e7517d4e13cd1351e8d370f35ec75fe121591d96", "nhash_after": "0f2b8c264acc441d17eb016feede2076816f1699", "source": "propagate:src/ov_SC05_018/ov_SC05_018_jr_8017D604.c:func_801837E8", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.237, "objects": ["build/src/ov_SC03_125/ov_SC03_125_jr_8017D604.o"], "before_text": "void func_80180F0C(s32 a0) {\n s32 state;\n s32 fv;\n\n state = *(u16 *)(a0 + 0x34);\n if (state == 1) {\n goto case1;\n }\n if (state < 2) {\n if (state == 0) {\n goto case0;\n }\n goto tail;\n }\n if (state == 2) {\n goto case2;\n }\n if (state == 3) {\n goto case3;\n }\n goto tail;\n\ncase0: {\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0xFC) = 0;\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n fv = rand();\n fv = (fv & 0x1F) + 0x1E;\n goto store1c;\n}\n\ncase1: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 + 6;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto randtail;\n}\n\ncase2: {\n register s32 p __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n s32 v0;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto tail;\n}\n\ncase3: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 - 3;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (*(s16 *)(a0 + 0xFC) >= 9) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = 0;\n}\n\nrandtail:\n fv = rand();\n fv = (fv & 0x3F) + 0x3C;\n\nstore1c:\n *(s32 *)(a0 + 0x1C) = fv;\n\ntail:\n if (!((u32)func_80029504() < 0x492)) {\n func_8012C218((void *)a0);\n }\n}\n", "after_text": "void func_80180F0C(s32 a0) {\n s32 state;\n s32 fv;\n\n state = *(u16 *)(a0 + 0x34);\n if (state == 1) {\n goto case1;\n }\n if (state < 2) {\n if (state == 0) {\n goto case0;\n }\n goto tail;\n }\n if (state == 2) {\n goto case2;\n }\n if (state == 3) {\n goto case3;\n }\n goto tail;\n\ncase0: {\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0xFC) = 0;\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n fv = rand();\n fv = (fv & 0x1F) + 0x1E;\n goto store1c;\n}\n\ncase1: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 + 6;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto randtail;\n}\n\ncase2: {\n s32 p;\n p = *(s32 *)(a0 + 0x20);\n *(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto tail;\n}\n\ncase3: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 - 3;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (*(s16 *)(a0 + 0xFC) >= 9) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = 0;\n}\n\nrandtail:\n fv = rand();\n fv = (fv & 0x3F) + 0x3C;\n\nstore1c:\n *(s32 *)(a0 + 0x1C) = fv;\n\ntail:\n if (!((u32)func_80029504() < 0x492)) {\n func_8012C218((void *)a0);\n }\n}\n"}
|
||||
{"ts": "2026-09-10 21:12:56", "label": "s104_d5", "rung": "E", "calib": {"head": "f644ecb9d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC04_020/ov_SC04_020_jr_8017D604.c", "fn": "func_80180BD0", "addr": 2149059536, "aliases": null, "header": false, "includers": 0, "nhash_before": "e7517d4e13cd1351e8d370f35ec75fe121591d96", "nhash_after": "0f2b8c264acc441d17eb016feede2076816f1699", "source": "propagate:src/ov_SC05_018/ov_SC05_018_jr_8017D604.c:func_801837E8", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.228, "objects": ["build/src/ov_SC04_020/ov_SC04_020_jr_8017D604.o"], "before_text": "void func_80180BD0(s32 a0) {\n s32 state;\n s32 fv;\n\n state = *(u16 *)(a0 + 0x34);\n if (state == 1) {\n goto case1;\n }\n if (state < 2) {\n if (state == 0) {\n goto case0;\n }\n goto tail;\n }\n if (state == 2) {\n goto case2;\n }\n if (state == 3) {\n goto case3;\n }\n goto tail;\n\ncase0: {\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0xFC) = 0;\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n fv = rand();\n fv = (fv & 0x1F) + 0x1E;\n goto store1c;\n}\n\ncase1: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 + 6;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto randtail;\n}\n\ncase2: {\n register s32 p __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus8)\n s32 v0;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto tail;\n}\n\ncase3: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 - 3;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (*(s16 *)(a0 + 0xFC) >= 9) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = 0;\n}\n\nrandtail:\n fv = rand();\n fv = (fv & 0x3F) + 0x3C;\n\nstore1c:\n *(s32 *)(a0 + 0x1C) = fv;\n\ntail:\n if (!((u32)func_80029504() < 0x492)) {\n func_8012C218((void *)a0);\n }\n}\n", "after_text": "void func_80180BD0(s32 a0) {\n s32 state;\n s32 fv;\n\n state = *(u16 *)(a0 + 0x34);\n if (state == 1) {\n goto case1;\n }\n if (state < 2) {\n if (state == 0) {\n goto case0;\n }\n goto tail;\n }\n if (state == 2) {\n goto case2;\n }\n if (state == 3) {\n goto case3;\n }\n goto tail;\n\ncase0: {\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0xFC) = 0;\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n fv = rand();\n fv = (fv & 0x1F) + 0x1E;\n goto store1c;\n}\n\ncase1: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 + 6;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto randtail;\n}\n\ncase2: {\n s32 p;\n p = *(s32 *)(a0 + 0x20);\n *(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto tail;\n}\n\ncase3: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 - 3;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (*(s16 *)(a0 + 0xFC) >= 9) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = 0;\n}\n\nrandtail:\n fv = rand();\n fv = (fv & 0x3F) + 0x3C;\n\nstore1c:\n *(s32 *)(a0 + 0x1C) = fv;\n\ntail:\n if (!((u32)func_80029504() < 0x492)) {\n func_8012C218((void *)a0);\n }\n}\n"}
|
||||
{"ts": "2026-09-10 21:12:57", "label": "s104_d5", "rung": "E", "calib": {"head": "f644ecb9d", "stamp": "15956e4a96c4"}, "tu": "src/ov_SC03_002/ov_SC03_002_jr_80181D78.c", "fn": "func_801824DC", "addr": 2149065948, "aliases": null, "header": false, "includers": 0, "nhash_before": "e7517d4e13cd1351e8d370f35ec75fe121591d96", "nhash_after": "0f2b8c264acc441d17eb016feede2076816f1699", "source": "propagate:src/ov_SC05_018/ov_SC05_018_jr_8017D604.c:func_801837E8", "verdict": "LEVER-FREE", "sites": [], "compiles": 1, "seconds": 0.131, "objects": ["build/src/ov_SC03_002/ov_SC03_002_jr_80181D78.o"], "before_text": "void func_801824DC(s32 a0) {\n s32 state;\n s32 fv;\n\n state = *(u16 *)(a0 + 0x34);\n if (state == 1) {\n goto case1;\n }\n if (state < 2) {\n if (state == 0) {\n goto case0;\n }\n goto tail;\n }\n if (state == 2) {\n goto case2;\n }\n if (state == 3) {\n goto case3;\n }\n goto tail;\n\ncase0: {\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0xFC) = 0;\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n fv = rand();\n fv = (fv & 0x1F) + 0x1E;\n goto store1c;\n}\n\ncase1: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 + 6;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto randtail;\n}\n\ncase2: {\n register s32 p __asm__(\"$2\"); // !FAKE: pin $2 \u2014 NEEDED DIFFERS (P36 rung B tus9)\n s32 v0;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto tail;\n}\n\ncase3: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 - 3;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (*(s16 *)(a0 + 0xFC) >= 9) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = 0;\n}\n\nrandtail:\n fv = rand();\n fv = (fv & 0x3F) + 0x3C;\n\nstore1c:\n *(s32 *)(a0 + 0x1C) = fv;\n\ntail:\n if (!((u32)func_80029504() < 0x492)) {\n func_8012C218((void *)a0);\n }\n}\n", "after_text": "void func_801824DC(s32 a0) {\n s32 state;\n s32 fv;\n\n state = *(u16 *)(a0 + 0x34);\n if (state == 1) {\n goto case1;\n }\n if (state < 2) {\n if (state == 0) {\n goto case0;\n }\n goto tail;\n }\n if (state == 2) {\n goto case2;\n }\n if (state == 3) {\n goto case3;\n }\n goto tail;\n\ncase0: {\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0xFC) = 0;\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n fv = rand();\n fv = (fv & 0x1F) + 0x1E;\n goto store1c;\n}\n\ncase1: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 + 6;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto randtail;\n}\n\ncase2: {\n s32 p;\n p = *(s32 *)(a0 + 0x20);\n *(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);\n if (func_8012BEE8(a0) == 0) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = *(u16 *)(a0 + 0x34) + 1;\n goto tail;\n}\n\ncase3: {\n s32 v0;\n s32 p;\n v0 = *(u16 *)(a0 + 0xFC);\n p = *(s32 *)(a0 + 0x20);\n v0 = v0 - 3;\n *(u16 *)(a0 + 0xFC) = v0;\n *(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;\n if (*(s16 *)(a0 + 0xFC) >= 9) {\n goto tail;\n }\n *(u16 *)(a0 + 0x34) = 0;\n}\n\nrandtail:\n fv = rand();\n fv = (fv & 0x3F) + 0x3C;\n\nstore1c:\n *(s32 *)(a0 + 0x1C) = fv;\n\ntail:\n if (!((u32)func_80029504() < 0x492)) {\n func_8012C218((void *)a0);\n }\n}\n"}
|
||||
|
||||
@@ -3193,11 +3193,9 @@ case1: {
|
||||
}
|
||||
|
||||
case2: {
|
||||
register s32 p __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 v0;
|
||||
v0 = *(u16 *)(a0 + 0xFC);
|
||||
s32 p;
|
||||
p = *(s32 *)(a0 + 0x20);
|
||||
*(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;
|
||||
*(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);
|
||||
if (func_8012BEE8(a0) == 0) {
|
||||
goto tail;
|
||||
}
|
||||
|
||||
@@ -4906,11 +4906,9 @@ case1: {
|
||||
}
|
||||
|
||||
case2: {
|
||||
register s32 p __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus8)
|
||||
s32 v0;
|
||||
v0 = *(u16 *)(a0 + 0xFC);
|
||||
s32 p;
|
||||
p = *(s32 *)(a0 + 0x20);
|
||||
*(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;
|
||||
*(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);
|
||||
if (func_8012BEE8(a0) == 0) {
|
||||
goto tail;
|
||||
}
|
||||
|
||||
@@ -4707,11 +4707,9 @@ case1: {
|
||||
}
|
||||
|
||||
case2: {
|
||||
register s32 p __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus8)
|
||||
s32 v0;
|
||||
v0 = *(u16 *)(a0 + 0xFC);
|
||||
s32 p;
|
||||
p = *(s32 *)(a0 + 0x20);
|
||||
*(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;
|
||||
*(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);
|
||||
if (func_8012BEE8(a0) == 0) {
|
||||
goto tail;
|
||||
}
|
||||
|
||||
@@ -6616,11 +6616,9 @@ case1: {
|
||||
}
|
||||
|
||||
case2: {
|
||||
register s32 p __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus8)
|
||||
s32 v0;
|
||||
v0 = *(u16 *)(a0 + 0xFC);
|
||||
s32 p;
|
||||
p = *(s32 *)(a0 + 0x20);
|
||||
*(u16 *)(p + 0x12) = *(u16 *)(p + 0x12) + v0;
|
||||
*(u16 *)(p + 0x12) += *(u16 *)(a0 + 0xFC);
|
||||
if (func_8012BEE8(a0) == 0) {
|
||||
goto tail;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user