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phase-36: S104 s104_e26 — func_8017E764 banked at 0 through the whole-object gate + propagated — $3 pin → 0: the early temp renamed to val (sched.c:2489-2490) + i = 0 moved up; the byte-needed volatile kept unmarked (decision 3)
This commit is contained in:
Drew T
@@ -0,0 +1,21 @@
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void func_801823BC(a0, a1)
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s32 a0;
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s32 a1;
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{
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extern void func_80049CAC(s32 a0, s32 a1);
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extern void func_8017EF68(s32 a0, s32 a1, s32 a2);
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extern s16 D_801AEB52[];
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extern s32 D_801B20E0;
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extern s32 D_801A158C;
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extern s32 D_801AEB1C;
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s16 *q;
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s32 *r;
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q = D_801AEB52;
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*q = a0;
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func_80049CAC((s32)q - 2, (s32)q - 78);
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D_801AEB1C = (s16)a1;
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r = (s32 *)((s32)q - 82);
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*r = 0;
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func_8017EF68((s32)&D_801B20E0, (s32)&D_801A158C, (s32)r);
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}
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@@ -0,0 +1,41 @@
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# func_801823BC (ov_SC06_000_jr_8017AE2C.c) — e28, P36 T7 S104
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**Score: 4 (sweep best 2) -> 0, zero levers** (the `$17` pin AND the launder asm both deleted; plain C). First `--try`.
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## (a) Residual
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COUNT +1 (29 vs 28): the store `*(s32 *)((s32)q - 82) = 0` came out absolute (`lui at,%hi(D_801AEB52-82); sw zero,..(at)`)
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where the target stores through the callee-saved register holding `&D_801AEB52` (`sw zero,-82(s1)`, in the `jal` delay
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slot, after `addiu a2,s1,-82`). The pin was only there because the launder needed q in a known register; the register
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itself (`$s1`) is what global alloc gives q anyway once the call argument keeps it live across the first call.
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## (b) Pass and decision (the e12 mechanism, same TU; e12 proved it on .cse dumps for func_80182560)
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cse1 `find_best_addr` (gcc-2.7.2 cse.c:2622): the free text's address `(plus (reg q) -82)` is not a REG, so `fold_rtx`
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runs first (cse.c:2662-2664), substitutes q's constant equivalent `(symbol_ref D_801AEB52)` and folds the address to
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`(const (plus sym -82))` — a CONSTANT address, never replaced again (cse.c:2656) -> `lui at; sw`. A REG address
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`(mem (reg r))`, `r = q - 41`, is not folded; the lookup of r's class finds `(plus (reg q) -82)` at the same ADDRESS_COST
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as a REG (1: mips.h:2895, mips.c:1652-1653) and a higher rtx cost, which the tie-break prefers (cse.c:2711-2721); the
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symbolic constant costs 2 (mips.c:1631) and loses. r stays live as the third call argument, so cse2 does not re-fold
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(e12's func_80184A68 (b)3: a derived pointer with no other live use is re-folded in cse2).
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Proven on bytes here (score 0); the dump reading is e12's (not re-dumped for this function).
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## (c) Move
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Name the derived pointer and pass it: `r = (s32 *)((s32)q - 82); *r = 0; func_8017EF68(&D_801B20E0, &D_801A158C, (s32)r);`
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(`r = (s32 *)(q - 41);` also scores 0 — scratch/v2.c.)
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## (d) Generator proposal
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When a launder/`la` pointer's constant-offset access comes out as `lui at; sw/lw %lo(SYM+k)(at)` where the target has
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`sw k(reg)`, and the same `p + k` is also passed to a later call, name `r = p + k`, access `*r` and pass `r`.
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## (e) What did not work
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The sweep's R4/R7/R9/R12 moves stay at 2 (ORDER): none of them turns the address into a REG. Nothing else was needed.
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## (f) Method
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Counting first + e12's sibling text closed it on the first try; the method worked as written (brief + neighbours).
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## (g) Structs
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A struct on the global would give CONSTANT field addresses (cse.c:2656), the opposite of the target; a struct pointer
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based at D_801AEB52 with fields at -2/-78/-82 is not expressible (negative offsets) — the base would move to
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D_801AEB52-82 and the offsets change. The deciding fact is REG vs `reg+const` address in find_best_addr, not aliasing.
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## Copies
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func_80182464 (same TU) closes with the identical text (its own pack). No other copy of the `q - 2, q - 78` call in src/.
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@@ -0,0 +1,19 @@
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void func_80182464(s32 a0, s32 a1)
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{
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extern void func_80049CAC(s32 a0, s32 a1);
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extern void func_8017EF68(s32 a0, s32 a1, s32 a2);
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extern s16 D_801AEBAA[];
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extern s32 D_801B20E0;
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extern s32 D_801A3A0C;
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extern s32 D_801AEB74;
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s16 *q;
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s32 *r;
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q = D_801AEBAA;
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*q = a0;
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func_80049CAC((s32)q - 2, (s32)q - 78);
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D_801AEB74 = (s16)a1;
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r = (s32 *)((s32)q - 82);
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*r = 0;
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func_8017EF68((s32)&D_801B20E0, (s32)&D_801A3A0C, (s32)r);
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}
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@@ -0,0 +1,41 @@
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# func_80182464 (ov_SC06_000_jr_8017AE2C.c) — e28, P36 T7 S104
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**Score: 4 (sweep best 2) -> 0, zero levers** (the `$17` pin AND the launder asm both deleted; plain C). First `--try`.
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## (a) Residual
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COUNT +1 (29 vs 28): the store `*(s32 *)((s32)q - 82) = 0` came out absolute (`lui at,%hi(D_801AEBAA-82); sw zero,..(at)`)
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where the target stores through the callee-saved register holding `&D_801AEBAA` (`sw zero,-82(s1)`, in the `jal` delay
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slot, after `addiu a2,s1,-82`). The pin was only there because the launder needed q in a known register; the register
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itself (`$s1`) is what global alloc gives q anyway once the call argument keeps it live across the first call.
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## (b) Pass and decision (the e12 mechanism, same TU; e12 proved it on .cse dumps for func_80182560)
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cse1 `find_best_addr` (gcc-2.7.2 cse.c:2622): the free text's address `(plus (reg q) -82)` is not a REG, so `fold_rtx`
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runs first (cse.c:2662-2664), substitutes q's constant equivalent `(symbol_ref D_801AEBAA)` and folds the address to
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`(const (plus sym -82))` — a CONSTANT address, never replaced again (cse.c:2656) -> `lui at; sw`. A REG address
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`(mem (reg r))`, `r = q - 41`, is not folded; the lookup of r's class finds `(plus (reg q) -82)` at the same ADDRESS_COST
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as a REG (1: mips.h:2895, mips.c:1652-1653) and a higher rtx cost, which the tie-break prefers (cse.c:2711-2721); the
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symbolic constant costs 2 (mips.c:1631) and loses. r stays live as the third call argument, so cse2 does not re-fold
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(e12's func_80184A68 (b)3: a derived pointer with no other live use is re-folded in cse2).
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Proven on bytes here (score 0); the dump reading is e12's (not re-dumped for this function).
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## (c) Move
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Name the derived pointer and pass it: `r = (s32 *)((s32)q - 82); *r = 0; func_8017EF68(&D_801B20E0, &D_801A3A0C, (s32)r);`
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(`r = (s32 *)(q - 41);` scored 0 on func_801823BC.)
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## (d) Generator proposal
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When a launder/`la` pointer's constant-offset access comes out as `lui at; sw/lw %lo(SYM+k)(at)` where the target has
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`sw k(reg)`, and the same `p + k` is also passed to a later call, name `r = p + k`, access `*r` and pass `r`.
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## (e) What did not work
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The sweep's R4/R7/R9/R12 moves stay at 2 (ORDER): none of them turns the address into a REG. Nothing else was needed.
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## (f) Method
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Counting first + e12's sibling text closed it on the first try; the method worked as written (brief + neighbours).
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## (g) Structs
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A struct on the global would give CONSTANT field addresses (cse.c:2656), the opposite of the target; a struct pointer
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based at D_801AEBAA with fields at -2/-78/-82 is not expressible (negative offsets) — the base would move to
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D_801AEBAA-82 and the offsets change. The deciding fact is REG vs `reg+const` address in find_best_addr, not aliasing.
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## Copies
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func_801823BC (same TU) closes with the identical text (its own pack). No other copy of the `q - 2, q - 78` call in src/.
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@@ -0,0 +1,35 @@
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void func_801842CC(s32 arg0)
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{
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s32 i;
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for (i = 0; i < 0x49; i += 0x18) {
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s32 e = func_80132EF4(arg0, 0x22);
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if (e != 0) {
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s32 t;
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s32 v;
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s32 d;
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s32 z;
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t = *(u16 *)(arg0 + 0x84) & 4;
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z = *(u16 *)(e + 0xE);
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d = i + t * 3 - 0x2A;
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do { // !FAKE: do-while — its LOOP notes are sched1 barriers (sched.c:2053-2080): the +6 load stays after d, the +E store before the sign extension (P36 S104 e28)
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v = *(u16 *)(e + 0x6);
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z += 0x28;
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*(u16 *)(e + 0xE) = z;
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} while (0);
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v -= d;
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*(u16 *)(e + 0x6) = v;
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v = *(u16 *)(e + 0xA);
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v -= 0x20;
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*(u16 *)(e + 0xA) = v;
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v = (s16)d;
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if (v >= 0) {
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v = v << 7;
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} else {
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v = -(v << 7);
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}
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*(u16 *)(e + 0x34) = v + 0x1000;
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*(s32 *)(e + 0x14) = 0xFFFE0000;
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*(s32 *)(e + 0x18) = 0x30000;
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}
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}
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}
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@@ -0,0 +1,78 @@
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# func_801842CC (ov_SC06_000_jr_8017AE2C.c) — e28, P36 T7 S104
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**Score: 24 free (sweep best 5) -> 0 with ZERO pins/asm and ONE marked `do { … } while (0)`** (step 8's allowed-but-marked
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construct). Tree: 3 levers (pin v1 + pin a0 + launder) -> 0 levers + 1 marked do-while. NOT a strict plain-C close: every
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do-while-free spelling I found stays at >= 21 (see (e)).
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The same text closes the class's two other copies (`--try` 0 each; rename + the copy's own constants):
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ov_SC03_024 `func_80182108` (identical) and ov_SC03_014 `func_801889B4` (`z -= 0x28`, `0xFFFD0000`) —
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scratch/copy_80182108_dw.c, scratch/copy_801889B4_dw.c.
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Alternative at 0 (kept for the coordinator's choice): the tree's shape with ONE pin, `register s32 v0 __asm__("v0")` on
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the reused variable, launder and the v1/a0 pins deleted — scratch/body_onepin.c (also 0 on both copies:
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scratch/copy_80182108.c, copy_801889B4.c). And two pins (v1, a0) + no launder: scratch/t4.c.
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## (a) Residual
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COUNT-equal register rotation in the loop body: free text x/(x&4) in `a0`, d in `v0`, the +E value in `v1`; the target has
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x in `v0`, d in `v1`, +E in `a0`, and (consequence) `sh v0,52(a1)` sinks below the `lui v0` constants. Plus
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`addu v0,v0,s0` vs the target's `addu v1,s0,v1`.
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## (b) Passes and decisions (PROVEN on dumps: scratch/dumps_free, dumps_c1, dumps_c2, dumps_e2, dumps_h1; localalloc_sim)
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1. **local-alloc** (eligibility local-alloc.c:472 = one block AND one death; qty order :1486-1507; find_free_reg lowest
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free). In the free text ONE variable `v0` holds x, x&4, the +6 value, the +A value and the sign-extended result: it
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dies in 4 places -> global. Block 2 then has two local qtys, d (33846) and +E (15000): d takes `$2`, +E `$3`, global
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gives v0 `$4`. The target needs a `$2` holder that local-alloc SEES.
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2. Giving x its own variable `t` makes THREE local qtys, t=q0, +E=q1, d=q2; the three-qty switch (it compares qty
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NUMBERS 0/1/2 while swapping POSITIONS, :1489-1500) orders them [t, d, +E] -> `$2/$3/$4`, the target's
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(localalloc_sim on dumps_h1: q0 37500 v0, q2 33846 v1, q1 20625 a0, 0 mismatches).
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3. **sched1** then breaks it. `priority()` (sched.c:1425) = max over LOG_LINKS of pred priority + cost - 1. With x in the
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same pseudo as the +6 load, that load carried REG_DEP_ANTI links to the x uses (priority 2) and stayed after the d
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chain; with `t` split it has no predecessor, priority 1, and is hoisted above the d chain (dumps_c2 trace T-11:
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"58 (2) 62 (1)" -> 58), overlapping t, so global cannot give the reused `v` `$2`; the subu then gets 2, the `sll d,16`
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ties the +E store at 2 and the store wins the potential-hazard tie (schedule_select sched.c:2616-2686, "insn 68 has a
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greater potential hazard"). Needs 1-2 (x its own single-death local) and 3 (x sharing the +6 load's pseudo) contradict
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in plain C.
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4. **The do-while**: its NOTE_INSN_LOOP_BEG/END are sched1 barriers (sched.c:2053-2080: the insn after a loop note gets a
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dependence on every earlier set/use, `reg_pending_sets_all`, `flush_pending_lists`). LOOP_BEG makes the +6 load depend
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on the d chain (stays after it); LOOP_END makes the +E store the barrier, so the sign extension and everything after
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it must follow the store. dumps_h1's block-2 trace is serialised to single-element ready lists. One note is not enough:
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a lone barrier before the +6 load (scratch/e1-e5.c) scores 2 — the barrier insn is then the LOAD, every later insn
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inherits its latency (+40 gets priority 3) and the +E store again ties the `sll` and wins by potential hazard.
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5. `addu v1,s0,v1`: expand_binop swaps a commutative op whose target equals op1 (optabs.c:409-418), so `v1 = s0 + v1`
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became `(plus v1 s0)`; one expression `d = i + t * 3 - 0x2A` keeps the counter first. The launder's only job was to keep
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combine from turning `(v0<<1) + v0` (disjoint bits of `x & 4`) into `or` (score 1 without it, scratch/t1.c); `t * 3`
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in one expression keeps `addu` — proven on bytes; which combine test declines the ior was NOT dumped.
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## (c) Moves (body.c)
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- x split into its own `t = *(u16 *)(arg0 + 0x84) & 4;` (the rest of the reused variable is `v`);
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- `v1 = v0 * 2; launder; v1 = v1 + v0; v1 = s0 + v1; v1 = v1 - 0x2A;` -> `d = i + t * 3 - 0x2A;`;
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- the +6 load and the +E update wrapped in a marked `do { v = *(u16 *)(e + 6); z += 0x28; *(u16 *)(e + 0xE) = z; } while (0);`
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- readability: `if (e != 0) { … }` instead of `continue`, `v = (s16)d;` instead of `<< 16`/`>> 16`, `v = -(v << 7);`,
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`*(u16 *)(e + 0x34) = v + 0x1000;` — each proven neutral on bytes (scratch/g3, g4, g8, g9, g10 -> h1 = body.c).
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- Not neutral (keep as written): `*(u16 *)(e + 6) = v - d;` (21), `*(u16 *)(e + 0xE) = z + 0x28;` inside the do (21),
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`*(u16 *)(e + 0xA) -= 0x20;` (30).
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## (d) Generator proposal
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When a register residual needs a variable SPLIT for local-alloc (a multi-death local, :472) but the split lets sched1
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hoist a load that the shared variable used to pin with anti-dependences, wrap [that load .. the next statement group the
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hazard tie reorders] in a marked `do { … } while (0)` — and try the two pins -> one pin on the reused variable as the
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lever-count fallback.
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## (e) What did not work (bytes)
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- 2160-body plain-C sweep (scratch/gen.py -> gen_results.txt): x split / fused, three d spellings, three +E spellings,
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+6 and +A updates inline / via temp, both sign-extension spellings, all 6 field-update orders, +E load before/after
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the x load: best 21. s16 `d` (d1-d5.c): 21-27. Single pin on v1 or a0 (t7/t8.c): 21.
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- do-while around the d chain only, empty do-while, do-while around the +6 load only (e1-e5.c): 2.
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- do-while around only the +40 with the +6 load before it (f3.c): 21.
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## (f) Method
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Counting first said "no missing instruction"; alloc_table.py was the wrong tool (the decider is local-alloc) —
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`tools/localalloc_sim.py` + the `.sched` trace settled it. The method has no row for "a variable reuse that the
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SCHEDULER needs (anti-dependences) but LOCAL-ALLOC forbids (multi-death)"; that contradiction is what the tree's pins,
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the one-pin fallback and the do-while each resolve.
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## (g) Structs
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Plausibly NO for this decision: typing `e` as an entity struct (`e->x -= d; e->y -= 0x20; e->z += 0x28; …`) produces the
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fresh-temp form (the sweep's inline `*(u16 *)(e + K) -= …` spellings: 21+). The aggregate channel (expr.c:4568-4577) only
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changes MEMORY dependences; here every load/store pair is already disambiguated by base+offset (memrefs_conflict_p) and
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the deciding links are a REGISTER anti-dependence and sched1's loop-note barrier. Not tested with a body-local struct.
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@@ -0,0 +1,17 @@
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void func_80185354(void *param_1)
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{
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s32 i;
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u8 *e;
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u32 vA, vB;
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for (i = 0; i < 200; i++) {
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e = D_801AED08 + i * 0x2C;
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((void (*)(void *, s32))func_80185520)(e, i);
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vA = rand() & 0x1F;
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*(u32 *)(e + 0x18) = (vA << 2) | ((vA << 0x12) | (vA << 10));
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vB = rand() & 7;
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*(u32 *)(e + 0x20) = vB;
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}
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func_8012BF4C((s32 *)param_1, 4);
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func_8012AD50(param_1);
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}
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@@ -0,0 +1,43 @@
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# func_80185354 (ov_SC06_000_jr_8017AE2C.c) — e28, P36 T7 S104
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**Score: 22 free (sweep best 18) -> 0, zero levers** (the `$16` pin deleted; plain C). Second `--try`.
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## (a) Residual
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COUNT +4 (43 vs 39) and one extra callee-saved register: the free text walks TWO pointers — `s2` = `e` (the call
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argument, stepped `+44`) and `s0` = `e + 32` (`addiu s0,s2,32`, stores at `-8(s0)`/`0(s0)`) — plus an extra `s3` for the
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parameter. The target walks ONE pointer `s0` (initialised `lui/addiu` to `D_801AED08`, stepped `+44` in the branch delay
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slot) and addresses both stores as `24(s0)`/`32(s0)`.
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## (b) Pass and decision
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loop.c strength reduction (`strength_reduce`, gcc-2.7.2 loop.c; givs recorded by `record_giv` :4341, merged by
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`combine_givs` :5494). In the free text `e` is itself a BIV (`e = e + 0x2C`); its field addresses `e+0x18`/`e+0x20` are
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DEST_ADDR givs of that biv, and the pass reduces one of them into a new register (`s0 = e + 32`) while `e` must survive
|
||||
for the call argument — two stepped registers. The tree's `$16` pin hid `e` from loop.c (a hard register is never a biv),
|
||||
which is why the pin was NEEDED. In the target, `e` is a GIV of the counter biv `i` (`D_801AED08 + i*0x2C`): the call
|
||||
argument and both field addresses are givs with the same multiplier, `combine_givs` folds them into ONE reduced register
|
||||
with constant offsets, and `i` stays as the call's second argument and the exit test (`slti v0,s1,200`).
|
||||
Proven on bytes (score 0); the `-dL` dump was NOT taken (the prediction from S103 c2/d16 closed on the first spelling).
|
||||
|
||||
## (c) Move
|
||||
Index the array by the loop counter instead of walking a pointer:
|
||||
`for (i = 0; i < 200; i++) { e = D_801AED08 + i * 0x2C; func_80185520(e, i); … }` (the do-while and `e += 0x2C` deleted).
|
||||
A do-while with the same indexed `e` (scratch/a3.c) scores 23 — the `for` (rotated loop, loop.c sees the canonical
|
||||
biv/giv shape) is part of the close; writing each access as `D_801AED08 + (i-1)*0x2C + K` (a2.c) scores 32.
|
||||
|
||||
## (d) Generator proposal
|
||||
When the residual shows two callee-saved registers stepped by the same stride (one `addiu sK,sJ,K` before the loop) and
|
||||
the tree pins the walked pointer, rewrite `p = BASE; do { … p += S; } while (++i < N)` as
|
||||
`for (i = 0; i < N; i++) { p = BASE + i * S; … }` — the pointer becomes a giv of the counter and combines into one.
|
||||
|
||||
## (e) What did not work
|
||||
The sweep's R4/R6/R7/R8/R9/R10/R12 moves reach 18-19: none turns the walked pointer into a counter giv.
|
||||
|
||||
## (f) Method
|
||||
S103 c2 / S104 d16-d18 in METHOD_S103.md named this exact class ("a walked destination pointer -> index the array by the
|
||||
loop counter"); counting first (+4, one extra `$s`) pointed straight at it. Worked as written.
|
||||
|
||||
## (g) Structs
|
||||
Yes, plausibly the ORIGINAL shape: `D_801AED08` is an array of 0x2C-byte records (`struct { u8 pad[0x18]; u32 f18;
|
||||
u32 pad1c; u32 f20; … } D_801AED08[200];`, see func_801853F0's `+0x1C/+0x20/+0x24` fields) and `&D_801AED08[i]` is
|
||||
exactly the indexed giv the close needs. A struct type would not change the pass decision beyond what the indexed form
|
||||
already does (the decisive fact is biv vs giv in loop.c, not aliasing); not tested with a body-local struct.
|
||||
+185
-185
@@ -1,7 +1,7 @@
|
||||
{
|
||||
"head": "6b2e585dd",
|
||||
"head": "32f641aca",
|
||||
"stamp": "15956e4a96c4",
|
||||
"generated": "2026-09-11 04:01",
|
||||
"generated": "2026-09-11 04:02",
|
||||
"aliases": [
|
||||
"main",
|
||||
"ov_SC03_014",
|
||||
@@ -21,207 +21,207 @@
|
||||
"main": {
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"identical": 85,
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"seconds": 8.579999999999998,
|
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"mean_s": 0.101
|
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"seconds": 7.531999999999999,
|
||||
"mean_s": 0.089
|
||||
},
|
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"ov_SC03_014": {
|
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"identical": 32,
|
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"seconds": 5.74,
|
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"mean_s": 0.179
|
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"seconds": 4.885999999999999,
|
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"mean_s": 0.153
|
||||
},
|
||||
"ov_SC03_015": {
|
||||
"objects": 32,
|
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"identical": 32,
|
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"seconds": 5.2860000000000005,
|
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"mean_s": 0.165
|
||||
"seconds": 4.711999999999999,
|
||||
"mean_s": 0.147
|
||||
},
|
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"ov_SC04_011": {
|
||||
"objects": 28,
|
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"identical": 28,
|
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"seconds": 4.6899999999999995,
|
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"mean_s": 0.167
|
||||
"seconds": 4.067,
|
||||
"mean_s": 0.145
|
||||
}
|
||||
},
|
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"per_object_seconds": {
|
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
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|
||||
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|
||||
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|
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|
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|
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||||
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|
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||||
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||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
},
|
||||
"ok": true,
|
||||
"seconds": 2.7
|
||||
"seconds": 2.4
|
||||
}
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -5117,16 +5117,18 @@ void func_8017E764(s32 param_1)
|
||||
}
|
||||
|
||||
ent = D_801202A0;
|
||||
i = 0;
|
||||
pos[0] = *(u16 *)(param_1 + 6);
|
||||
{
|
||||
register u16 *vp __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus7)
|
||||
u16 t;
|
||||
vp = (u16 *)&D_80126B66;
|
||||
t = *(volatile u16 *)vp;
|
||||
u16 tt;
|
||||
/* `val` is the loop's table-value temp reused here (both live in $v1 in the target): its second set keeps
|
||||
* this address load from sched1's birthing priority (sched.c:2469-2545), so it is scheduled above the pos[0]
|
||||
* store and global-alloc gives it $v1 (P36 S104 e26). */
|
||||
val = (s32)&D_80126B66;
|
||||
tt = *(volatile u16 *)val; /* a byte-needed volatile, kept as ordinary C (gate-1 decision 3): a volatile MEM fails combine's recog (combine.c:491 init_recog_no_volatile, recog.c:807), so the address stays in a register (la + lhu 0(reg)) (P36 S104 e26 minimum-lever) */
|
||||
pos[1] = *(u16 *)(param_1 + 0xA);
|
||||
pos[2] = t + 8;
|
||||
pos[2] = tt + 8;
|
||||
}
|
||||
i = 0;
|
||||
np = (u16 *)D_801152A8;
|
||||
t = (ratan2(*(s16 *)&D_80126B62 - *(s16 *)(param_1 + 0xA),
|
||||
*(s16 *)&D_80126B5E - *(s16 *)(param_1 + 6)) - 0x400) & 0xFFF;
|
||||
|
||||
Reference in New Issue
Block a user