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https://github.com/Druthulu/BFM-decomp
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phase-36: S104 banks — the R23(case-label)/R34/R35/R36 pass: 915 classes in 1,757 s, MATCH 16 (bank line above); d20's minimum-lever func_80180324 (8 → 2 marked dead branches) PARKED for Drew — an invented always-false condition is not covered by ruling (a)
This commit is contained in:
Drew T
@@ -0,0 +1,123 @@
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void func_80180324(void *ent, void *spr, u32 *q, u32 *ot)
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{
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extern u8 *D_800A5E60;
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Ft4_801833F0 *poly;
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Drm_801833F0 *dm;
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s32 vtx;
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u32 flags;
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s32 tp, abr, code, shift;
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u16 x;
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u32 y;
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s32 tpage, clut, cy;
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s32 su, sv, uu, vv;
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s32 e; /* the sprite's far texel edge, u then v: read only by the dead arms */
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u16 fl;
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s32 i; /* also the second loop's counter (one variable: $t3 in both loops) */
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u32 b;
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poly = (Ft4_801833F0 *)D_800A5E60;
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fl = *(u16 *)((s32)ent + 0x1E) & 0x8000;
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flags = *(u32 *)((s32)ent + 4);
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tp = (flags >> 24) & 3;
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shift = 2 - tp;
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x = *(u16 *)((s32)ent + 0x28) + (*(s16 *)((s32)spr + 4) >> shift);
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y = *(u16 *)((s32)ent + 0x2A) + *(u16 *)((s32)spr + 6);
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vtx = *(s32 *)((s32)ent + 0x20);
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D_800A5E60 += 0xF0;
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if (flags & 0x40000000) {
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code = 0x2E;
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abr = (flags >> 28) & 3;
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} else {
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code = 0x2C;
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abr = 1;
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}
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tpage = (tp << 7) | (abr << 5) | ((y & 0x100) >> 4) | ((x & 0x3C0) >> 6) |
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((y & 0x200) << 2);
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b = *(u8 *)((s32)ent + 0x27);
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cy = (b + 0x100) << 6;
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if (b < 0xE0) {
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clut = cy | 0x16;
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} else {
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clut = cy | 0x10;
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}
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{
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s32 t = ((x - ((tpage & 0xF) << 6)) << shift) +
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(*(u16 *)((s32)spr + 4) & ((1 << shift) - 1));
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e = t + *(u8 *)((s32)spr + 2) - 1;
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su = t;
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if (tpage & 0x200) su = e; // !FAKE: dead-branch su (u edge) — combine folds the always-false tpage bit via nonzero_bits (combine.c:8716/6803) into an unconditional jump (combine.c:2353), jump2 deletes the arm after flow (toplev.c:3142), leaving `t + spr[2] - 1` dead as in the target (P36 S104 d20 minimum-lever)
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}
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y &= 0xFFFF;
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if (tpage & 0x10) {
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y -= 0x100;
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sv = y;
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} else {
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sv = y;
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}
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e = sv + *(u8 *)((s32)spr + 3) - 1;
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if (tpage & 0x200) su = e; // !FAKE: dead-branch su (v edge) — same mechanism; keeps `sv + spr[3] - 1` (P36 S104 d20 minimum-lever)
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i = 1;
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uu = su;
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vv = sv;
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for (; i < 13; i += 2, poly++) {
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s32 k = (i - 1) * 4;
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poly->tag.len = 9;
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poly->code = code;
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poly->tpage = tpage;
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poly->u2 = su;
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poly->v2 = sv;
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poly->u0 = SR3_801833F0(vtx + k + 0x10) + uu;
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poly->v0 = SR3_801833F0(vtx + k + 0x12) + vv;
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poly->u1 = SR3_801833F0(vtx + i * 4 + 0x10) + uu;
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poly->v1 = SR3_801833F0(vtx + i * 4 + 0x12) + vv;
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/* k2 is recorded as a giv HERE, AFTER the u1/v1 mem giv - see (1). */
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{
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s32 k2 = (i + 1) * 4;
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poly->u3 = SR3_801833F0(vtx + k2 + 0x10) + uu;
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poly->v3 = SR3_801833F0(vtx + k2 + 0x12) + vv;
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}
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poly->clut = clut;
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poly->r0 = *(u8 *)((s32)ent + 0x24);
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poly->g0 = *(u8 *)((s32)ent + 0x25);
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poly->b0 = *(u8 *)((s32)ent + 0x26);
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poly->x0 = ((u16 *)q)[i * 2];
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poly->y0 = ((u16 *)q)[i * 2 + 1];
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poly->x1 = ((u16 *)q)[i * 2 + 2];
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poly->y1 = ((u16 *)q)[i * 2 + 3];
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poly->x2 = ((u16 *)q)[0];
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poly->y2 = ((u16 *)q)[1];
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poly->x3 = ((u16 *)q)[i * 2 + 4];
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poly->y3 = ((u16 *)q)[i * 2 + 5];
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if (fl != 0) {
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ADDPRIM_801833F0(&ot[*(s32 *)((s32)q + 0x34 + (i >> 1) * 4)], poly);
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} else {
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ADDPRIM_801833F0(ot, poly);
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}
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}
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poly[-1].x3 = ((u16 *)q)[2];
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poly[-1].y3 = ((u16 *)q)[3];
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poly[-1].u3 = su + SR3_801833F0(vtx + 0x10);
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poly[-1].v3 = sv + SR3_801833F0(vtx + 0x12);
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if (flags & 0x40000000) {
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dm = (Drm_801833F0 *)poly;
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if (fl != 0) {
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i = 0;
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D_800A5E60 += 0x30;
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do {
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i++;
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dm->tag.len = 1;
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dm->code0 = (abr << 5) | 0xE100000A;
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ADDPRIM_801833F0(&ot[*(volatile s32 *)((s32)q + 0x34)], dm);
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q = (u32 *)((s32)q + 4);
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dm++;
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} while (i < 6);
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} else {
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dm->code0 = (abr << 5) | 0xE100000A;
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D_800A5E60 += 8;
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dm->tag.len = 1;
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ADDPRIM_801833F0(ot, dm);
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}
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}
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}
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@@ -0,0 +1,116 @@
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# func_80180324 (ov_SC04_007) — agent d20, P36 T7 S104
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**Result: `--try` score 0 (328/328), on this function AND all ten other members of its family (table:
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`scratch/copies/TABLE.md`).** No register pin, no `asm` of any kind, no `volatile` added (the loop-2
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`*(volatile s32 *)` cast was already in body_free.c and is still needed: without it 7, see (e)).
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**It is NOT a lever-free close, and I do not claim one.** The body keeps two `if (tpage & 0x200) su = e;`
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statements. `tpage` never has bit 9 set, so each test is always false: an invented identically-zero
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condition, which step 6 refuses. Both are marked `// !FAKE: dead-branch` as the step-9 minimum-lever body.
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Lever count 8 → 2 (tree: 1 `$0` pin + 6 asm keepalives + the pre-existing volatile cast; now: 2
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C-level dead branches + the same volatile cast; 0 pins, 0 asm).
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Drew's ruling needed: is a C-level dead branch that reproduces a real late-dead branch in the original an
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acceptable marked lever, or should it go back to asm keepalives?
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## (a) The residual
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The lever-free text is 10 instructions short (318 vs 328):
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- the target computes `t + spr[2] - 1` and `sv + spr[3] - 1` (lbu/addu/addiu each, the second with its
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load-delay nop) and never reads either;
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- it keeps `move s3,a0` (su := t) in the lbu delay slot, and the chain reads `a0` (t), not `s3`;
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- it keeps the sv if/else as `beqz; j; addiu s2,a1,-256 | move s2,a1`, where the free text gets
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if-converted;
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- in the loop, the counter `i` / the 0xFFFFFF mask / the vtx+4 giv are permuted over t3/t4/t5, and
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sv/uu/vv/0xFF000000 are permuted over a1/s0/s1/s2.
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## (b) Mechanism: passes and decisions (every claim here tested on bytes unless it says otherwise)
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1. **Dead code survives only if its consumer disappears AFTER flow.** flow's final pass deletes dead sets
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(`flow.c:1478-1490`), and nothing re-runs flow later. combine (after flow) folds a test on a pseudo whose
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`nonzero_bits` (`combine.c:6803`, `simplify_comparison` `:8716`) prove it constant. That turns the
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conditional jump into `(set (pc) (label_ref))` (`combine.c:2353`; seen in `.combine`: jump_insn 164).
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jump2 (`toplev.c:3142`, after sched2) then deletes the unreachable arm. The chain that fed only that arm
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stays as dead code, byte-exact. Micro-reproduced (`scratch/micro/t3.c`) and on the real function.
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This REFUTES the family exemplar's note 1 (ov_SC02_028 `func_801833F0` header, "gcc-2.7.2 deletes any
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pure-C spelling").
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2. **The copy must follow the chain's read of t in sched1's order, in the same block.** If the copy comes
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first and t does not die in it, local-alloc's `optimize_reg_copy_1` (`local-alloc.c:700`) rewrites the
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chain to read su. Every separate-temp variant read `s3`/`s2`. The copy is placed last only if it wins
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sched1's tie:
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- `adjust_priority` boosts a "birthing" insn (`sched.c:2469`, `:2539`: dest set once and live after).
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With a fresh `ue`, the chain's final addiu is birthing and wins, and the copy lands above it.
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- Declaring ONE variable `e` for both edges (two live sets) un-boosts it. The tie then goes to
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`INSN_LUID` (`sched.c:2428`), so the copy, textually later, is scheduled last.
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- t then dies in the copy. `combine_regs` refuses to tie it to the global su (`local-alloc.c:1774`), so
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`move s3,a0` survives. sched2 moves it into the lbu delay slot.
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3. **sv if/else kept as j+else.** jump.c's `if (...) x = a; else x = b` → `x = b; if (...) x = a` rewrite
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(`jump.c:699`) needs a ONE-insn then-arm (`jump.c:748-749`). Writing the then-arm as
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`y -= 0x100; sv = y;` gives two insns in every pre-flow jump pass. cse's `(set REG0 REG1)` swap
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(`cse.c:7440`) plus flow then fold it back to one `addiu s2,a1,-256`.
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4. **Loop permutation t3/t4/t5.** `allocno_compare` (`global.c:587-600`) ranks by `floor_log2(refs)·refs/live`.
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`i` (9/114 → 2368) ranked below the hoisted 0xFFFFFF (13/111 → 3513). Using `i` as the second loop's
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counter too (the target has i and m in the SAME `$t3`, so they are one variable) gives 16/152 → 4210.
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i is then allocated first and takes t3. This also puts vtx (8/184 → 1304) back below the k2 giv
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(1320.8), so the tree's vtx keepalive becomes unnecessary.
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5. **a1/s0/s1/s2 permutation.** A v dead arm written as `sv = e` gives sv 8 refs → 1764, so sv takes a1
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before vv. Writing the v arm into `su` instead gives sv 7/135 → 1037. That drops sv below vv (1250),
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uu (1238.9) and the 0xFF000000 constant (1238.5), which is the target's order: vv=a1, uu=s0, const=s1,
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sv=s2, su=s3.
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## (c) The moves (from body_free.c, 43)
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- one `s32 e` holds both edge values: `e = t + w - 1; su = t; if (C) su = e;` and, after the tpage
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if/else, `e = sv + h - 1; if (C) su = e;` (C = `tpage & 0x200`, always false). 43 → 32.
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- loop 2's counter `m` replaced by `i` (declaration of `m` deleted). 32 → 18.
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- the v dead arm writes `su`, not `sv`. 18 → 1.
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- then-arm `y -= 0x100; sv = y;` (else `sv = y;`, the `(u16)` cast gone). 1 → 0.
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- conditions that also give 0: any pair drawn from {`tp & 4`, `tpage & 0x200`, `tpage & 0x400`,
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`tpage & 0x1000`} (13 of 256 pairs scored 0; `scratch/c2search.py`).
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## (d) Generator proposals
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- **G-a (natural, broad):** when a tree has `x = y + zr` (a `$0`-pin copy) in an else-arm whose then-arm is
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`x = y OP K`, rewrite the then-arm as `y OP= K; x = y;` and the else as `x = y`. The two-insn arm blocks
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jump.c:748's if-conversion; cse.c:7440 and flow fold it back to one insn.
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- **G-b (natural):** when a tree keeps `asm("" :: "r"(i))` density reads on a loop counter, and a LATER
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loop's counter lands in the same hard register in the target, merge the two counters into one variable
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(refs and live length add; global.c:595).
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- **G-c (lever-to-lever, marked):** when a tree keeps `asm("" :: "r"(expr))` for a value the target
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computes and never reads, replace it with `if (<test combine proves false>) X = expr;`. X is a variable
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set on the live path and live afterwards; enumerate X, and enumerate the test over bits a live pseudo
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provably lacks. Same lever count, but it moves the lever from asm to C and lets the other levers go.
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## (e) What did not work (byte evidence)
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- A fresh `ue`/`ve` per edge: the chain reads s3 (optimize_reg_copy_1), 60-87.
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- `su = C ? e : t` with C always true (`if (!C) su = t; else su = e;`): combine leaves
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`move v0,zero; bnez v0`, 60.
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- The same test on `fl` twice: cse shares the and-result and combine cannot fold both jumps (`move v1,zero`).
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Tests on `fl` also add refs to fl and change which pseudos spill.
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- The v arm writing `sv`/`vv`/`uu`/`y`, or a su/sv swap: 29-38.
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- `i = 1` before the dead branch with the branch holding the copies: a loop-entry test appears
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(slti/beqz), 96-141.
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- sv else-arm `(u16)y`, `(u32)(u16)y`, `y & 0xFFFF`: blocks the if-conversion but leaves
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`andi s2,a1,0xffff`, 1. combine only simplifies inside a LOG_LINK pair, and the else block has one insn.
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A fresh masked `yy` reshuffles the whole allocation (109-126). Ternary / `y -= ((c) ? 0x100 : 0)`: 29.
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Inverted test, `== 0` test or switch: the arms swap, 3.
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- Dropping the loop-2 volatile, or spelling that read as `((s32 *)q)[13]` + `q++`, a struct field, a local
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`z` pointer, `ot + …`, or indexing by the counter: 5-7. loop.c eliminates the q biv.
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## (f) Where the method fell short
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- Neither the method nor the cookbook explains how a dead value can survive, and the exemplar header said
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it cannot. The "DEAD CODE IS REAL" keepalive is a reproducible pass sequence (flow → combine fold →
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jump2), testable in a 10-line micro. A `.combine` grep for `(set (pc) (label_ref` would have shown it.
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- The allocation table misled until I matched pseudo numbers to variables by hand (declaration order).
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The tool should print variable names.
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- `pkill -f` killed my own shell once (the memory note is right). The coordinator's regen fleet was running
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(40 `--try` processes), so compiles took ~2 s each.
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## (g) Structs
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Struct typing does not plausibly change what keeps the two dead-branch levers. They exist because the
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target contains unread arithmetic, and only a consumer removed after flow (or an asm use) produces that.
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Tested: a UV pair as a local struct goes to the stack (stores kept); as a union it vanishes but leaves an
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orphan 48-byte frame (`scratch/micro/t4.c`). Neither is the target shape.
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For the pre-existing loop-2 volatile, a body-local `struct { u32 a[13]; s32 z; } *` field read scores 7,
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the same as the plain read: loop.c's biv elimination does not look at MEM_IN_STRUCT_P, so a struct is not
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the missing piece there either.
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The one struct question left open: the original likely had real flip/UV-edge code (a sprite RECT struct
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or flag field) whose test the compiler could prove false. Finding that field in the entity or sprite
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layout would turn the invented `tpage & 0x200` into the original's test.
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+185
-185
@@ -1,7 +1,7 @@
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{
|
||||
"head": "97e5d721b",
|
||||
"head": "2e05e1238",
|
||||
"stamp": "15956e4a96c4",
|
||||
"generated": "2026-09-10 23:47",
|
||||
"generated": "2026-09-10 23:48",
|
||||
"aliases": [
|
||||
"main",
|
||||
"ov_SC03_014",
|
||||
@@ -21,207 +21,207 @@
|
||||
"main": {
|
||||
"objects": 85,
|
||||
"identical": 85,
|
||||
"seconds": 10.692999999999998,
|
||||
"mean_s": 0.126
|
||||
"seconds": 9.173999999999998,
|
||||
"mean_s": 0.108
|
||||
},
|
||||
"ov_SC03_014": {
|
||||
"objects": 32,
|
||||
"identical": 32,
|
||||
"seconds": 7.435,
|
||||
"mean_s": 0.232
|
||||
"seconds": 6.347,
|
||||
"mean_s": 0.198
|
||||
},
|
||||
"ov_SC03_015": {
|
||||
"objects": 32,
|
||||
"identical": 32,
|
||||
"seconds": 6.612000000000001,
|
||||
"mean_s": 0.207
|
||||
"seconds": 6.3530000000000015,
|
||||
"mean_s": 0.199
|
||||
},
|
||||
"ov_SC04_011": {
|
||||
"objects": 28,
|
||||
"identical": 28,
|
||||
"seconds": 6.183000000000002,
|
||||
"mean_s": 0.221
|
||||
"seconds": 5.93,
|
||||
"mean_s": 0.212
|
||||
}
|
||||
},
|
||||
"per_object_seconds": {
|
||||
"build/src/800.o": 1.092,
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||||
"build/src/800_b.o": 0.105,
|
||||
"build/src/800_b_2.o": 0.443,
|
||||
"build/src/800_b_o0a.o": 0.139,
|
||||
"build/src/800_c.o": 0.284,
|
||||
"build/src/800b2.o": 0.139,
|
||||
"build/src/apicard1.o": 0.104,
|
||||
"build/src/apicard2.o": 0.153,
|
||||
"build/src/apicard3.o": 0.102,
|
||||
"build/src/apicard4.o": 0.106,
|
||||
"build/src/apicard5.o": 0.103,
|
||||
"build/src/apicard6.o": 0.121,
|
||||
"build/src/apicard7.o": 0.078,
|
||||
"build/src/boot.o": 0.129,
|
||||
"build/src/gap.o": 0.086,
|
||||
"build/src/libapi1.o": 0.103,
|
||||
"build/src/libapi2.o": 0.159,
|
||||
"build/src/800.o": 0.572,
|
||||
"build/src/800_b.o": 0.111,
|
||||
"build/src/800_b_2.o": 0.294,
|
||||
"build/src/800_b_o0a.o": 0.179,
|
||||
"build/src/800_c.o": 0.209,
|
||||
"build/src/800b2.o": 0.144,
|
||||
"build/src/apicard1.o": 0.107,
|
||||
"build/src/apicard2.o": 0.167,
|
||||
"build/src/apicard3.o": 0.088,
|
||||
"build/src/apicard4.o": 0.2,
|
||||
"build/src/apicard5.o": 0.172,
|
||||
"build/src/apicard6.o": 0.085,
|
||||
"build/src/apicard7.o": 0.1,
|
||||
"build/src/boot.o": 0.125,
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"build/src/ov_SC03_015/ov_SC03_015_jr_8015AE2C.o": 0.154,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_8015C32C.o": 0.665,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_8016AB6C.o": 0.364,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_80171B4C.o": 0.138,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_801734BC.o": 0.291,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_801789AC.o": 0.12,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_80178D40.o": 0.161,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_8017A4AC.o": 0.107,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.o": 0.216,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.o": 0.268,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_80184440.o": 0.094,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_jr_801848E4.o": 0.345,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_o0b.o": 0.072,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_o0c.o": 0.086,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_o0d.o": 0.092,
|
||||
"build/src/ov_SC03_015/ov_SC03_015_o0e.o": 0.098,
|
||||
"build/src/ov_SC04_011/ov_SC04_011.o": 0.162,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_after.o": 0.597,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8012ACE0.o": 0.497,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80135888.o": 0.102,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80135A4C.o": 0.08,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80135D20.o": 0.153,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.205,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.o": 0.14,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.128,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.107,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.241,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.112,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.235,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.14,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.116,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.112,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.174,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.589,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.35,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.125,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.279,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.082,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.129,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.135,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.155,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.755,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.062,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.126
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801380E0.o": 0.212,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8013C98C.o": 0.139,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8013F350.o": 0.131,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8013FFD8.o": 0.083,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80140608.o": 0.225,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015444C.o": 0.118,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80154C24.o": 0.279,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801588CC.o": 0.187,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80159C84.o": 0.089,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015A3C8.o": 0.113,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015AE2C.o": 0.121,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8015C32C.o": 0.553,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8016AB6C.o": 0.345,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80171B4C.o": 0.16,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801734BC.o": 0.257,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_801789AC.o": 0.083,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_80178D40.o": 0.135,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017A4AC.o": 0.09,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017AE2C.o": 0.16,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_jr_8017D494.o": 0.683,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0b.o": 0.077,
|
||||
"build/src/ov_SC04_011/ov_SC04_011_o0c.o": 0.099
|
||||
},
|
||||
"ok": true,
|
||||
"seconds": 3.8
|
||||
"seconds": 8.7
|
||||
}
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -7598,13 +7598,12 @@ void CdReadSectorReadyCB(u8 reason) {
|
||||
XRECT dead;
|
||||
u32 *q;
|
||||
XRECT *r;
|
||||
register s32 i __asm__("$18"); // !FAKE: pin $18 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 i;
|
||||
s32 n, pos, res, b;
|
||||
s32 tmp;
|
||||
s32 k80;
|
||||
s32 one;
|
||||
s32 dst;
|
||||
s32 cnt;
|
||||
s32 dst4;
|
||||
|
||||
if (reason != 1) goto endReason;
|
||||
@@ -7753,8 +7752,8 @@ void CdReadSectorReadyCB(u8 reason) {
|
||||
break;
|
||||
case 4:
|
||||
if (p->words < 0x801) {
|
||||
cnt = (p->words + 3) / 4;
|
||||
func_80043994(lzss_sectorStagingBuf, cnt);
|
||||
i = (p->words + 3) / 4;
|
||||
func_80043994(lzss_sectorStagingBuf, i);
|
||||
if (func_8002FC64(p->words, lzss_sectorStagingBuf) == 0) goto stageFail;
|
||||
p->count++;
|
||||
if (p->flags != 0) goto phaseDone;
|
||||
|
||||
@@ -694,7 +694,7 @@ extern s32 func_8004787C(s32 a0);
|
||||
|
||||
void func_80183790(s32 a0) {
|
||||
s32 sum1;
|
||||
register s32 sum2 __asm__("$17"); // !FAKE: pin $17 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 sum2;
|
||||
s32 frac;
|
||||
s32 threshold;
|
||||
s32 ret;
|
||||
@@ -707,8 +707,7 @@ void func_80183790(s32 a0) {
|
||||
|
||||
sum1 = D_801C7748 + D_8018ABA4;
|
||||
frac = sum1 & 0xFFF;
|
||||
sum2 = D_801C774A;
|
||||
sum2 += D_8018ABA6;
|
||||
sum2 = D_801C774A + D_8018ABA6;
|
||||
|
||||
threshold = -(sum1 * 1536) / 12288 - 0x22;
|
||||
|
||||
|
||||
@@ -3897,12 +3897,11 @@ extern s8 D_801B42D8;
|
||||
void func_801826F0(s32 *param_1)
|
||||
{
|
||||
int new_var;
|
||||
register s32 p __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 p;
|
||||
s32 r;
|
||||
p = (s32) (&D_801B42D8);
|
||||
r = param_1[0x2c / 4];
|
||||
new_var = r;
|
||||
p += new_var;
|
||||
p = (s32) (&D_801B42D8) + new_var;
|
||||
*((s8 *) p) = 0;
|
||||
((void (*)(void)) func_80146C3C)();
|
||||
}
|
||||
|
||||
@@ -2838,7 +2838,7 @@ extern void func_80181D3C(void *a0);
|
||||
void func_80181D78(s32 a0) {
|
||||
s32 r;
|
||||
s32 r2;
|
||||
register s32 *self __asm__("$16"); // !FAKE: pin $16 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 *self, *self2, *self3;
|
||||
u16 arr[6];
|
||||
|
||||
extern s32 rand(void);
|
||||
@@ -2947,8 +2947,8 @@ void func_80181D78(s32 a0) {
|
||||
func_801821B4((s32)a0);
|
||||
return;
|
||||
case 6:
|
||||
self = (s32 *)(a0 + 4);
|
||||
r = func_8012B6D4((s16 *)self, (s16 *)(*(s32 *)(a0 + 0x64) + 4));
|
||||
self2 = (s32 *)(a0 + 4);
|
||||
r = func_8012B6D4((s16 *)self2, (s16 *)(*(s32 *)(a0 + 0x64) + 4));
|
||||
r2 = func_8012B608(*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12), r, 8);
|
||||
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) += r2;
|
||||
func_8012B178((s32)a0, (s32)0xFFFA0000);
|
||||
@@ -2962,8 +2962,8 @@ void func_80181D78(s32 a0) {
|
||||
*(s32 *)(a0 + 0x1C) = 0x10;
|
||||
break;
|
||||
case 7:
|
||||
self = (s32 *)(a0 + 4);
|
||||
r = func_8012B6D4((s16 *)self, (s16 *)(*(s32 *)(a0 + 0x64) + 4));
|
||||
self3 = (s32 *)(a0 + 4);
|
||||
r = func_8012B6D4((s16 *)self3, (s16 *)(*(s32 *)(a0 + 0x64) + 4));
|
||||
r2 = func_8012B608(*(s16 *)(*(s32 *)(a0 + 0x20) + 0x12), r, 8);
|
||||
*(u16 *)(*(s32 *)(a0 + 0x20) + 0x12) += r2;
|
||||
func_8012B178((s32)a0, (s32)0xFFFA0000);
|
||||
|
||||
@@ -3433,9 +3433,8 @@ s32 a0;
|
||||
s16 s0;
|
||||
s32 obj;
|
||||
s32 ang0;
|
||||
s32 ang1;
|
||||
s32 x;
|
||||
register s32 m1 __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 m1;
|
||||
s32 m2;
|
||||
s16 d;
|
||||
s32 q;
|
||||
@@ -3494,11 +3493,11 @@ L474:
|
||||
}
|
||||
x = ratan2(-*(s16 *)(a0 + 0xE), *(s16 *)(a0 + 6)) - 0x400;
|
||||
m2 = x & 0xFFF;
|
||||
ang1 = m2;
|
||||
m1 = m2;
|
||||
if (x & 0x800) {
|
||||
ang1 = m2 | 0xF000;
|
||||
m1 = m2 | 0xF000;
|
||||
}
|
||||
x = ang1 - ang0;
|
||||
x = m1 - ang0;
|
||||
m2 = x & 0xFFF;
|
||||
d = m2;
|
||||
if (x & 0x800) {
|
||||
|
||||
@@ -2981,8 +2981,7 @@ extern void func_8012CAE4(void *a0);
|
||||
|
||||
void func_8017F920(s32 a0) {
|
||||
s32 v0;
|
||||
s32 v1;
|
||||
register s32 addr __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 addr;
|
||||
|
||||
addr = (s32)&D_8019C7EC;
|
||||
*(s32 *)(a0 + 0x78) = addr;
|
||||
@@ -3006,8 +3005,8 @@ void func_8017F920(s32 a0) {
|
||||
*(s32 *)(a0 + 0x58) = D_8019C7F4 | 0x60000000;
|
||||
}
|
||||
|
||||
v1 = *(s32 *)(a0 + 0x20);
|
||||
*(s32 *)(v1 + 0x4) |= 0x8040;
|
||||
addr = *(s32 *)(a0 + 0x20);
|
||||
*(s32 *)(addr + 0x4) |= 0x8040;
|
||||
*(u16 *)(a0 + 0x5C) = 0xCC00;
|
||||
func_8012A828(a0, (void *)&D_8019D200);
|
||||
|
||||
|
||||
@@ -4678,8 +4678,7 @@ extern s32 func_8012C588(s32 a0, s32 a1);
|
||||
|
||||
void func_8017F9CC(s32 a0) {
|
||||
s32 v0;
|
||||
s32 v1;
|
||||
register s32 addr __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus8)
|
||||
s32 addr;
|
||||
|
||||
addr = (s32)&D_8018547C;
|
||||
*(s32 *)(a0 + 0x78) = addr;
|
||||
@@ -4703,8 +4702,8 @@ void func_8017F9CC(s32 a0) {
|
||||
*(s32 *)(a0 + 0x58) = D_80185484 | 0x60000000;
|
||||
}
|
||||
|
||||
v1 = *(s32 *)(a0 + 0x20);
|
||||
*(s32 *)(v1 + 0x4) |= 0x8040;
|
||||
addr = *(s32 *)(a0 + 0x20);
|
||||
*(s32 *)(addr + 0x4) |= 0x8040;
|
||||
*(s8 *)(a0 + 0xC0) = 1;
|
||||
*(s32 *)(a0 + 0xB4) = 1;
|
||||
func_8012A828(a0, (void *)&D_80181594);
|
||||
|
||||
@@ -2998,8 +2998,7 @@ extern void func_8012A828(s32 a0, void *a1);
|
||||
|
||||
void func_80180958(s32 a0) {
|
||||
s32 v0;
|
||||
s32 v1;
|
||||
register s32 addr __asm__("$3"); // !FAKE: pin $3 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 addr;
|
||||
|
||||
addr = (s32)&D_801A52E4;
|
||||
*(s32 *)(a0 + 0x78) = addr;
|
||||
@@ -3023,8 +3022,8 @@ void func_80180958(s32 a0) {
|
||||
*(s32 *)(a0 + 0x58) = D_801A52EC | 0x60000000;
|
||||
}
|
||||
|
||||
v1 = *(s32 *)(a0 + 0x20);
|
||||
*(s32 *)(v1 + 0x4) |= 0x8040;
|
||||
addr = *(s32 *)(a0 + 0x20);
|
||||
*(s32 *)(addr + 0x4) |= 0x8040;
|
||||
*(u16 *)(a0 + 0x5C) = 0xCC00;
|
||||
func_8012A828(a0, (void *)&D_801A5CF8);
|
||||
|
||||
|
||||
@@ -3287,8 +3287,7 @@ extern u16 func_80148800(s32 *a0);
|
||||
void func_8017F304(s32 a0) {
|
||||
Blk8_80126940_8017D6D0_8017F48C sp10;
|
||||
u8 t;
|
||||
register s16 lo __asm__("$4"); // !FAKE: pin $4 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s16 hi;
|
||||
s16 lo;
|
||||
|
||||
if (func_80148800(&D_80126B58) & 3) {
|
||||
t = (*(u8 *)(a0 + 5) + 1) & 1;
|
||||
@@ -3302,9 +3301,9 @@ void func_8017F304(s32 a0) {
|
||||
if (sp10.v[0] < lo) {
|
||||
sp10.v[0] = lo;
|
||||
}
|
||||
hi = -0x10c0;
|
||||
if (sp10.v[0] > hi) {
|
||||
sp10.v[0] = hi;
|
||||
lo = -0x10c0;
|
||||
if (sp10.v[0] > lo) {
|
||||
sp10.v[0] = lo;
|
||||
}
|
||||
func_8017F53C(a0, sp10.v);
|
||||
}
|
||||
|
||||
@@ -3749,7 +3749,6 @@ void func_8017E71C(void *a0) {
|
||||
if (s1 != 0) {
|
||||
s32 sx;
|
||||
s32 pan;
|
||||
s32 vol;
|
||||
|
||||
v[0] = *(u16 *)(s0 + 0x6);
|
||||
v[1] = *(u16 *)(s0 + 0xA);
|
||||
@@ -3759,15 +3758,14 @@ void func_8017E71C(void *a0) {
|
||||
sx = (s16)*(u16 *)&sxy;
|
||||
pan = (sx + 0xA0) / 0x14;
|
||||
if (sx < 0) {
|
||||
vol = (sx >> 1) + 0x7F;
|
||||
v1 = (sx >> 1) + 0x7F;
|
||||
} else {
|
||||
vol = 0x7F - (sx >> 1);
|
||||
v1 = 0x7F - (sx >> 1);
|
||||
}
|
||||
if ((u32)(pan & 0xFFFF) < 0x10) {
|
||||
s32 row = vol - 0x2F;
|
||||
__asm__("" : "=r"(row) : "0"(row)); // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus10)
|
||||
s32 row = v1 - 0x2F;
|
||||
if ((u32)(row & 0xFFFF) < 0x51) {
|
||||
func_8002D4C8(s1, (vol | 0x3000 | (pan << 8)) & 0xFFFF);
|
||||
func_8002D4C8(s1, (v1 | 0x3000 | (pan << 8)) & 0xFFFF);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -3950,8 +3950,7 @@ void func_80189F24(s16 *arg0, s32 arg1)
|
||||
u8 sp10[4];
|
||||
s32 size;
|
||||
s32 prod;
|
||||
register s32 h __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 w;
|
||||
s32 h;
|
||||
|
||||
if (D_801E67A0[D_800B99DA & 0xF] == 0) {
|
||||
size = 0x60;
|
||||
@@ -3961,10 +3960,10 @@ void func_80189F24(s16 *arg0, s32 arg1)
|
||||
|
||||
arg1++;
|
||||
prod = size * arg1;
|
||||
w = prod / 32;
|
||||
h = w / 2;
|
||||
sp10[0] = w;
|
||||
sp10[1] = w;
|
||||
size = prod / 32;
|
||||
h = size / 2;
|
||||
sp10[0] = size;
|
||||
sp10[1] = size;
|
||||
sp10[2] = h;
|
||||
sp10[3] = 0;
|
||||
|
||||
|
||||
@@ -3589,9 +3589,8 @@ extern s32 D_801E1158;
|
||||
void func_8017E1F0(s32 param_)
|
||||
{
|
||||
s32 s1;
|
||||
register s32 ent __asm__("$16"); // !FAKE: pin $16 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
register s32 i __asm__("$18"); // !FAKE: pin $18 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 k;
|
||||
s32 ent;
|
||||
s32 i;
|
||||
struct {
|
||||
s16 m[16];
|
||||
s16 out[4];
|
||||
@@ -3658,10 +3657,10 @@ void func_8017E1F0(s32 param_)
|
||||
frm.f07 = 0x7FFF;
|
||||
*(u16 *)(s1 + 0x108) = 0;
|
||||
func_8012EC04(s1, tmp, (s32 *)frm.m);
|
||||
k = 0;
|
||||
while (k < 4) {
|
||||
func_8012F14C((s32)frm.m, (s32)&D_80193448[k * 4], (s32)frm.out);
|
||||
frm.idx = k;
|
||||
i = 0;
|
||||
while (i < 4) {
|
||||
func_8012F14C((s32)frm.m, (s32)&D_80193448[i * 4], (s32)frm.out);
|
||||
frm.idx = i;
|
||||
frm.ax = frm.out[0];
|
||||
frm.ay = frm.out[1];
|
||||
frm.az = frm.out[2];
|
||||
@@ -3675,7 +3674,7 @@ void func_8017E1F0(s32 param_)
|
||||
*(s16 *)(ent + 0xA) = frm.out[1];
|
||||
*(s16 *)(ent + 0xE) = frm.out[2];
|
||||
}
|
||||
k++;
|
||||
i++;
|
||||
}
|
||||
func_8002D4C8(0x953, 0);
|
||||
cnt = *(s32 *)(s1 + 0xE0) + 1;
|
||||
@@ -5002,29 +5001,27 @@ extern u8 D_801936C8[];
|
||||
|
||||
void func_801809A8(s32 a0)
|
||||
{
|
||||
s32 s0 = a0;
|
||||
s32 v1;
|
||||
|
||||
if (func_8012C354(a0, &D_80193688) != 0) {
|
||||
*(u8 *)(s0 + 0xC0) = 1;
|
||||
*(s32 *)(s0 + 0xB4) = -1;
|
||||
*(s16 *)(s0 + 0xAE) = -1;
|
||||
*(u8 *)(s0 + 0x75) = 8;
|
||||
func_8012A828(s0, &D_801936C8);
|
||||
__asm__("" : "=r"(s0) : "0"(s0)); // !FAKE: launder — NEEDED DIFFERS (P36 rung B tus9)
|
||||
if (*(s16 *)(s0 + 0x70) != 0) {
|
||||
*(s16 *)(s0 + 2) = 4;
|
||||
*(u8 *)(a0 + 0xC0) = 1;
|
||||
*(s32 *)(a0 + 0xB4) = -1;
|
||||
*(s16 *)(a0 + 0xAE) = -1;
|
||||
*(u8 *)(a0 + 0x75) = 8;
|
||||
func_8012A828(a0, &D_801936C8);
|
||||
if (*(s16 *)(a0 + 0x70) != 0) {
|
||||
*(s16 *)(a0 + 2) = 4;
|
||||
} else {
|
||||
*(s16 *)(s0 + 2) = 1;
|
||||
*(u32 *)(*(s32 *)(s0 + 0x20) + 4) |= 0x80000000;
|
||||
func_8012B2CC(s0);
|
||||
v1 = func_8012C658(0x346, 1, s0);
|
||||
*(s16 *)(a0 + 2) = 1;
|
||||
*(u32 *)(*(s32 *)(a0 + 0x20) + 4) |= 0x80000000;
|
||||
func_8012B2CC(a0);
|
||||
v1 = func_8012C658(0x346, 1, a0);
|
||||
if (v1 != 0) {
|
||||
*(s16 *)(v1 + 6) = -0x660;
|
||||
*(s16 *)(v1 + 0xA) = -0x682;
|
||||
*(s16 *)(v1 + 0xE) = 0x80;
|
||||
}
|
||||
v1 = func_8012C658(0x346, 1, s0);
|
||||
v1 = func_8012C658(0x346, 1, a0);
|
||||
if (v1 != 0) {
|
||||
*(s16 *)(v1 + 6) = -0xA60;
|
||||
*(s16 *)(v1 + 0xA) = -0x882;
|
||||
|
||||
@@ -3704,8 +3704,7 @@ void func_80180DCC(void *a0)
|
||||
void *s3 = a0;
|
||||
void *s2;
|
||||
void *p;
|
||||
s32 v1;
|
||||
register s32 v0 __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus9)
|
||||
s32 v0;
|
||||
s32 bits;
|
||||
s32 s0;
|
||||
s32 s1;
|
||||
@@ -3725,9 +3724,9 @@ void func_80180DCC(void *a0)
|
||||
}
|
||||
s1 = func_80012A60(s0, 0x400);
|
||||
v0 = func_80012A60(s0, 0xC00);
|
||||
v1 = (s16)s1;
|
||||
bits = (s16)s1;
|
||||
v0 = (s16)v0;
|
||||
v0 = (v0 < v1);
|
||||
v0 = (v0 < bits);
|
||||
if (v0 != 0) {
|
||||
goto TRUE1;
|
||||
}
|
||||
@@ -3739,9 +3738,9 @@ TRUE1:
|
||||
ELSE:
|
||||
s1 = func_80012A60(s0, 0);
|
||||
v0 = func_80012A60(s0, 0x800);
|
||||
v1 = (s16)s1;
|
||||
bits = (s16)s1;
|
||||
v0 = (s16)v0;
|
||||
v0 = (v0 < v1);
|
||||
v0 = (v0 < bits);
|
||||
if (v0 != 0) {
|
||||
goto TRUE2;
|
||||
}
|
||||
|
||||
@@ -4512,7 +4512,6 @@ void func_8017FCA8(s32 a0)
|
||||
s16 clamped;
|
||||
s16 va;
|
||||
s16 vb;
|
||||
register s32 sc __asm__("$2"); // !FAKE: pin $2 — NEEDED DIFFERS (P36 rung B tus10)
|
||||
|
||||
cur = *(PosFCA8 *) D_80126940;
|
||||
ret = func_8012E544(0x306);
|
||||
@@ -4535,8 +4534,8 @@ void func_8017FCA8(s32 a0)
|
||||
*(s16 *) (a0 + 0x20) = va;
|
||||
vb = ((clamped * 111) / 0x300) - 0x70;
|
||||
*(s16 *) (a0 + 0x30) = vb;
|
||||
sc = ((clamped * 800) / 0x300) + 0x190;
|
||||
*(s32 *) (a0 + 0x14) = (s16) sc;
|
||||
ret = ((clamped * 800) / 0x300) + 0x190;
|
||||
*(s32 *) (a0 + 0x14) = (s16) ret;
|
||||
} else {
|
||||
target = *(PosFCA8 *) D_80126940;
|
||||
}
|
||||
@@ -6234,13 +6233,12 @@ extern void func_80182038(s32 param_1);
|
||||
extern void func_8018247C(void);
|
||||
|
||||
void func_80182DF0(s32 arg0) {
|
||||
register s32 s0 __asm__("$16") = arg0; // !FAKE: pin $16 — NEEDED DIFFERS (P36 rung B tus10)
|
||||
|
||||
*(s16 *)(s0 + 0x52) = (rand() & 3) * 2 - 3;
|
||||
if (func_8012BEE8(s0) != 0) {
|
||||
func_80182038(s0);
|
||||
*(s16 *)(arg0 + 0x52) = (rand() & 3) * 2 - 3;
|
||||
if (func_8012BEE8(arg0) != 0) {
|
||||
func_80182038(arg0);
|
||||
}
|
||||
((void (*)(s32))func_8018247C)(s0);
|
||||
((void (*)(s32))func_8018247C)(arg0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -8,23 +8,22 @@ extern void func_8012A828(s32 a0, void *a1);
|
||||
extern s32 D_801DF700;
|
||||
extern s32 D_8018EFDC;
|
||||
void func_801860E4(void *a0) {
|
||||
register s32 s0 __asm__("$16") = (s32)a0; // !FAKE: pin $16 — NEEDED DIFFERS (P36 rung B headers2)
|
||||
s32 s1;
|
||||
s32 v0;
|
||||
v0 = ((s32 (*)(void))func_8012C1B8)();
|
||||
s1 = v0;
|
||||
*(s32 *)((s8 *)s0 + 0x20) = v0;
|
||||
*(s32 *)((s8 *)a0 + 0x20) = v0;
|
||||
if (v0 == 0) {
|
||||
func_8012CAE4((void *)s0);
|
||||
func_8012CAE4((void *)a0);
|
||||
} else {
|
||||
func_8001C214(s1, (s32)&D_801DF700);
|
||||
func_8001D0E8(s1, 0x800, 0x800);
|
||||
func_8012A828(s0, &D_8018EFDC);
|
||||
*(s32 *)((s8 *)s0 + 0x14) = 0xFFFC0000;
|
||||
*(s32 *)((s8 *)s0 + 0x48) = 0x20000;
|
||||
*(s32 *)((s8 *)s0 + 0x44) = 0;
|
||||
*(s32 *)((s8 *)s0 + 0x4C) = 0;
|
||||
*(s16 *)((s8 *)s0 + 0xDC) = 0x40;
|
||||
*(u16 *)((s8 *)s0 + 0x2) = *(u16 *)((s8 *)s0 + 0x2) + 1;
|
||||
func_8012A828(a0, &D_8018EFDC);
|
||||
*(s32 *)((s8 *)a0 + 0x14) = 0xFFFC0000;
|
||||
*(s32 *)((s8 *)a0 + 0x48) = 0x20000;
|
||||
*(s32 *)((s8 *)a0 + 0x44) = 0;
|
||||
*(s32 *)((s8 *)a0 + 0x4C) = 0;
|
||||
*(s16 *)((s8 *)a0 + 0xDC) = 0x40;
|
||||
*(u16 *)((s8 *)a0 + 0x2) = *(u16 *)((s8 *)a0 + 0x2) + 1;
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user