2. Read the batch; launch `tools/workflows/worker_wave.js` with `args={draftDir:".run/drafts-wave", targets:<batch array PASTED VERBATIM>}`.
3.`.venv/bin/python tools/orchestrator.py finish --drafts .run/drafts-wave --commit` — **BACKGROUNDED + `dangerouslyDisableSandbox`** (foreground make build/git get sandbox-killed exit 144). Prints `{banked, near, verified, fleet_pct, …}`.
4.**Distill EVERY wave that has `verified` banks** — `tools/workflows/distill.js``args={draftsDir:".run/drafts-wave", verified:<array>}`. This is an idiom-MINING pass (more aggressive than the conservative ×134 run): each new gcc quirk → cookbook → feeds forward to bigger reach-1 fns AND occasionally cracks a reach-134 **wall** (×134 bonus, like the Phase-18 pin idiom).
5. Loop (~17 waves for all 420). close-rate should stay HIGH (small fns) → no pool rotation; if it drops <0.15 ×2 and rotates off `reach1`, re-route by setting `"pool":"reach1"` in `.run/auto/orch_state.json`.
> Generated by `tools/backlog.py render` from `.run/backlog.jsonl`. These are functions the Phase-21 automation got **close** on but did NOT byte-match. The whole-binary byte-gate is the sole arbiter (G3/P9): **byte-matches bank and are NOT listed here** — only genuine near-misses/blockers are. Ranked by hand-session priority: **reach** (×N propagation leverage) → **closeness** (match_one mismatch count, lower = closer) → **size**. Each row's `best_draft` is the closest C the machine reached — resume from there.
**Open near-misses:** 100 · by status {'near': 62, 'failed': 38} · by class {'WAVE': 24, 'struct': 13, 'schedule': 22, 'plumbing': 12, 'regalloc-order': 22, 'remat': 2, 'other': 2, 'iv-combine': 3}
**Open near-misses:** 115 · by status {'near': 72, 'failed': 43} · by class {'WAVE': 20, 'plumbing': 15, 'schedule': 28, 'struct': 15, 'regalloc-order': 27, 'remat': 2, 'other': 5, 'iv-combine': 2, 'loop-guard': 1}
| # | addr | reach | class | nins | status | closeness | where it stuck | best draft |
| 20 | func_80171C64 | 134 | regalloc-order | 24 | near | 1 | unknown — first draft, param_1 must land in $s1 and (param_2 & 0xFF) in $s0 across the func_80171EC8 call | `.run/backlog_drafts/func_80171C64.c` |
| 21 | func_8016F0E4 | 134 | plumbing | 26 | near | 1 | none — MATCH (26 ins); natural C form, param_1 auto-allocated to $s0 | `.run/backlog_drafts/func_8016F0E4.c` |
| 27 | func_80147364 | 134 | remat | 30 | near | 4 | none — MATCH (30 ins). Lever: hoist &D_80126B58 into a local ptr `u8 *p=&D_80126B58;` so gcc | `.run/backlog_drafts/func_80147364.c` |
| 28 | func_80140D68 | 134 | schedule | 65 | near | 5 | 5-ins near-miss — gcc hoists `lui 0xff00` (the 0xFF000000 mask) one slot too early in the first AddPrim block, so the D_800B9A02 index value lands in $v1 instead of $a1 and *param_1 is read late (idx 35-43). Structure + regs otherwise byte-exact (frame eliminated via struct-array D_800AE7BC, &D_800B9A02 held in $a2 via the pB $6 pin, param_1+8 grouping fixes the rest). Pure sched1 list-order residual -> permuter candidate (try reg-hint + reorder around the lui 0xff00 / lw 0($a0) pair). | `.run/backlog_drafts/func_80140D68.c` |
| 29 | func_80175820 | 134 | schedule | 55 | near | 6 | body byte-IDENTICAL; only residual is the phantom 0x10 leaf frame — target schedules `addiu $sp,-0x10` into the load-delay slot at insn 26 (after the D_8011F7C0 load) and `addiu $sp,0x10` before `jr ra`. With the frame forced (reserved local + anchor) gcc emits the prologue adjust at insn 0 instead of the delay slot (§5 frame-scheduling class); pins block the permuter, no C lever found to move it. Frameless form left here = body byte-exact, 2 frame insns short. | `.run/backlog_drafts/func_80175820.c` |
| 41 | func_8014ADE0 | 134 | schedule | 139 | near | 19 | 16 ins off — all compiler-internal ties: (1) 0xAAA8 const lands $v0 vs target $v1; | `.run/backlog_drafts/func_8014ADE0.c` |
| 42 | func_8016191C | 134 | plumbing | 24 | near | 20 | none — MATCH (24 ins). early-return-per-arm: each arm sets $v0 directly + j-tail merges | `.run/backlog_drafts/func_8016191C.c` |
| 43 | func_8014FE60 | 134 | regalloc-order | 95 | near | 20 | none — MATCH (permuter closed the final bothzero-block regalloc/schedule residual: moving `a = in[2]` before the +0x7E read-modify-write flips the 0x7FFF constant into $v1 and computes return-0 in $v0) | `.run/backlog_drafts/func_8014FE60.c` |
| 50 | func_8014D2A0 | 134 | other | 80 | near | 27 | none — MATCH (80 ins, relocation-masked); loop-guard idiom per engine_core DEFINE_func_80164ACC | `.run/backlog_drafts/func_8014D2A0.c` |
| 51 | func_80177AD4 | 134 | iv-combine | 34 | near | 28 | cc1 combine_givs will NOT fold the halfword RMW (lhu;sh) into the byte-store biv. Target uses ONE IV at p+0x20 (byte at 0, halfword RMW at -2); our cc1 either (a) merges into ONE IV but bases it at the LOWEST offset = the halfword (+0x1e), so every load/store offset is shifted (0/2 vs -2/0) and byte-differs; or (b, this draft) keeps the byte biv at the correct +0x20 base but SPAWNS a 2nd IV (+0x1e) for the RMW halfword -> +1 addiu + schedule shift (28 mismatched, mostly the 2nd-IV addiu and a 1-row delay-slot schedule shift). Probe-confirmed: even with both fields as forward non-negative struct members, the halfword RMW never folds into the byte biv (a non-RMW byte/halfword pair DOES merge). Genuine gcc-2.7.2 giv-combination divergence, not source-typeable. Matches the Phase-20 §20 verdict (independently re-derived). STUB. | `.run/backlog_drafts/func_80177AD4.c` |
| 52 | func_801777BC | 134 | schedule | 59 | near | 29 | body byte-matches; residual ~3 ins = prologue instruction-scheduling (final `sll t8,16` / `lw param_7` / `addu t0,a0,0xC` ordering around the blez guard) + the loop-counter copy `addu t3,v0` — pure gcc sched/regalloc tie-break, permuter-blocked by the register __asm__ pins | `.run/backlog_drafts/func_801777BC.c` |
| 54 | func_80144B14 | 134 | schedule | 34 | near | 31 | none — MATCH (34 ins). Two stack structs (s16[3] each) passed by addr to | `.run/backlog_drafts/func_80144B14.c` |
| 55 | func_801778A8 | 134 | iv-combine | 38 | near | 38 | gcc spawns 2 IVs (byte giv @+0xc, halfword RMW giv @+0xa); target combines both into ONE IV at +0xc reaching the halfword at -2($a3). A struct collapses to 1 IV but anchors at the struct base (+0xa) not +0xc; raw byte+halfword RMW never combines. Same combine_givs-refuses-halfword-RMW wall as sibling func_80177AD4 (§20, stubbed). Floor 33-off; not source-steerable (combine runs pre-regalloc, pins/order don't move it). | `.run/backlog_drafts/func_801778A8.c` |
| 56 | func_80177EA4 | 134 | regalloc-order | 56 | near | 45 | structure/branch-polarity/block-order/IV all match (56=56 ins); residual is gcc loop-invariant HOISTING — move_movables threshold=62 vs my loop insn_count=46 hoists 5 constants (0x3000000,0x74808080,6,1) to prologue regs while the target re-materializes them INLINE each iteration (only the 0xFFFFFF mask is hoisted in both). To match, the loop-pass insn_count would need >=60 so threshold*1*1 < insn_count after the first hoist; clean C producing the identical final logic yields 46. Pins free regs (more hoisting), barriers/volatile/for-vs-do-while don't raise insn_count. ~45 masked-mismatches all cascade from the 5 hoisted-vs-inline constants + their register reassignment. | `.run/backlog_drafts/func_80177EA4.c` |
| 78 | func_80147F78 | 134 | schedule | 48 | failed | | TWO residuals remain. (1) FRAME: target frame is 0x60 = exactly 64 bytes (16 words) of LIVE local vars on top of the 4 saved regs (s0,s1,s2,ra) + 0x10 arg area; my body has no locals so frame is 0x20. Reproducing 64B of live local needs an address-escaped local buffer, but the target has only the 3 visible jals (no 4th call to receive &buf), so I cannot make a 16-word local survive -O2 dead-store-elim without emitting an extra instruction. (2) RELOAD SCHEDULE: target reloads D_80127090/94/98 from memory (folded lui%hi;lw%lo) with the FIRST reload HOISTED up between store90 and store94 (free non-volatile scheduling); a "memory" clobber barrier (below) forces the folded reloads but pins them strictly AFTER all three stores. The natural source is almost certainly a 16-word local buffer that ALIASES the globals (non-volatile reloads, freely scheduled) — same construct that also explains the 0x60 frame. Closest faithful body kept below; folded reload bytes are correct, frame + hoist are the gap. | `.run/backlog_drafts/func_80147F78.c` |
| 79 | func_80151C54 | 134 | plumbing | 52 | failed | | none — MATCH (52 ins). Branch-polarity §3-T4: BD60 arm is fall-through (if !=1 && ==0x11), BC44 is else. | `.run/backlog_drafts/func_80151C54.c` |
| 90 | func_80173CB4 | 134 | schedule | 90 | failed | | none — MATCH (switch form keeps cases unmerged; final block: reuse one temp for the D_8012750C test + the func_8013767C result -> $a0 alloc; invert if to !=0 for branch polarity + store order) | `.run/backlog_drafts/func_80173CB4.c` |
| 91 | func_8014C6F4 | 134 | regalloc-order | 91 | failed | | 19-off loop tie-break — target compiles the search as a while/for (pre-guard sltu;beqz present) with the found pointer snapshotted to $v0 split from the IV in $a0 and the +4 sunk into both call-arg delay slots; do-while is instruction-count-exact (91=91) but lacks the pre-guard, while every for/while form costs +4 ins (merge stays in $a0). §10 schedule/regalloc residual. | `.run/backlog_drafts/func_8014C6F4.c` |
| 5 | func_8016BF50 | 134 | schedule | 22 | near | 0 | none — MATCH; short buf[3] keeps all 3 stores live + hoisting *(int*)(p+0x34) into a local | `.run/backlog_drafts/func_8016BF50.c` |
| 38 | func_80140D68 | 134 | schedule | 65 | near | 5 | 5-ins near-miss — gcc hoists `lui 0xff00` (the 0xFF000000 mask) one slot too early in the first AddPrim block, so the D_800B9A02 index value lands in $v1 instead of $a1 and *param_1 is read late (idx 35-43). Structure + regs otherwise byte-exact (frame eliminated via struct-array D_800AE7BC, &D_800B9A02 held in $a2 via the pB $6 pin, param_1+8 grouping fixes the rest). Pure sched1 list-order residual -> permuter candidate (try reg-hint + reorder around the lui 0xff00 / lw 0($a0) pair). | `.run/backlog_drafts/func_80140D68.c` |
| 39 | func_80175820 | 134 | schedule | 55 | near | 6 | body byte-IDENTICAL; only residual is the phantom 0x10 leaf frame — target schedules `addiu $sp,-0x10` into the load-delay slot at insn 26 (after the D_8011F7C0 load) and `addiu $sp,0x10` before `jr ra`. With the frame forced (reserved local + anchor) gcc emits the prologue adjust at insn 0 instead of the delay slot (§5 frame-scheduling class); pins block the permuter, no C lever found to move it. Frameless form left here = body byte-exact, 2 frame insns short. | `.run/backlog_drafts/func_80175820.c` |
| 47 | func_8014ADE0 | 134 | schedule | 139 | near | 19 | 16 ins off — all compiler-internal ties: (1) 0xAAA8 const lands $v0 vs target $v1; | `.run/backlog_drafts/func_8014ADE0.c` |
| 48 | func_8016191C | 134 | plumbing | 24 | near | 20 | none — MATCH (24 ins). early-return-per-arm: each arm sets $v0 directly + j-tail merges | `.run/backlog_drafts/func_8016191C.c` |
| 49 | func_8014FE60 | 134 | regalloc-order | 95 | near | 20 | none — MATCH (permuter closed the final bothzero-block regalloc/schedule residual: moving `a = in[2]` before the +0x7E read-modify-write flips the 0x7FFF constant into $v1 and computes return-0 in $v0) | `.run/backlog_drafts/func_8014FE60.c` |
| 58 | func_80144B14 | 134 | schedule | 34 | near | 31 | none — MATCH (34 ins). Two stack structs (s16[3] each) passed by addr to | `.run/backlog_drafts/func_80144B14.c` |
| 59 | func_801778A8 | 134 | iv-combine | 38 | near | 38 | gcc spawns 2 IVs (byte giv @+0xc, halfword RMW giv @+0xa); target combines both into ONE IV at +0xc reaching the halfword at -2($a3). A struct collapses to 1 IV but anchors at the struct base (+0xa) not +0xc; raw byte+halfword RMW never combines. Same combine_givs-refuses-halfword-RMW wall as sibling func_80177AD4 (§20, stubbed). Floor 33-off; not source-steerable (combine runs pre-regalloc, pins/order don't move it). | `.run/backlog_drafts/func_801778A8.c` |
| 68 | func_80148094 | 134 | regalloc-order | 213 | near | 107 | ~39/213 residual (LCS), all in the sVar1>=0x201 clamp blocks: $v0/$v1 mflo regalloc swap + coupled branch-polarity/join-placement (bnez<->beqz) + 2 delay-slot fills (addiu s1,v0,0x400 into 80013F3C slot; sll s1,16 in-place into 2nd ratan2 slot) + early_ret a2-vs-s5 -> permuter/grinder territory | `.run/backlog_drafts/func_80148094.c` |
| 69 | func_8014EA4C | 134 | loop-guard | 183 | near | 142 | body byte-identical; residual is the §20 IV-final-value loop guard — target emits an | `.run/backlog_drafts/func_8014EA4C.c` |
| 70 | func_801412A8 | 134 | regalloc-order | 198 | near | 154 | 154-mismatch near-miss (198/198 ins, structure+branches exact). Two irreducible gcc residuals: (1) HEAD: held &D_800B9A02 ptr must be init-at-decl to stay in a reg across all 4 prims (correct 198-ins), but that forces gcc to materialize the address at fn entry (2 ins before the branches) vs target's in-body materialization -> shifts the head regalloc cascade; in-body assign re-materializes per-use (172 ins, wrong count) even with the $9 pin. (2) BODY: gcc OFFSET-FOLDS the 4x-unrolled prim stores (p[0..3], p+=4 -> sw at 16/20/24/28 from a fixed base) instead of ADVANCING $t6 (addiu $t6,0x10; sw at 0/4/8/12) like the target; no C form (post-inc, char* advance, =r/0 barrier, r-only barrier) triggers the register-advance. Pins landed p1->$t6/uVar4->$t0/iVar1->$a0/pidx->$t1 (head 0-1,8,14,16-19 exact). | `.run/backlog_drafts/func_801412A8.c` |
| 71 | func_801571C4 | 134 | schedule | 198 | near | 183 | prologue instruction SCHEDULE + frame-layout residual. Body + loop are byte-exact and | `.run/backlog_drafts/func_801571C4.c` |
| 72 | func_8014EE14 | 134 | schedule | 248 | near | 205 | body structurally matched (97 reloc-masked, mostly +1-offset branch artifacts). 3 real residuals, | `.run/backlog_drafts/func_8014EE14.c` |
| 89 | func_80147F78 | 134 | schedule | 48 | failed | | TWO residuals remain. (1) FRAME: target frame is 0x60 = exactly 64 bytes (16 words) of LIVE local vars on top of the 4 saved regs (s0,s1,s2,ra) + 0x10 arg area; my body has no locals so frame is 0x20. Reproducing 64B of live local needs an address-escaped local buffer, but the target has only the 3 visible jals (no 4th call to receive &buf), so I cannot make a 16-word local survive -O2 dead-store-elim without emitting an extra instruction. (2) RELOAD SCHEDULE: target reloads D_80127090/94/98 from memory (folded lui%hi;lw%lo) with the FIRST reload HOISTED up between store90 and store94 (free non-volatile scheduling); a "memory" clobber barrier (below) forces the folded reloads but pins them strictly AFTER all three stores. The natural source is almost certainly a 16-word local buffer that ALIASES the globals (non-volatile reloads, freely scheduled) — same construct that also explains the 0x60 frame. Closest faithful body kept below; folded reload bytes are correct, frame + hoist are the gap. | `.run/backlog_drafts/func_80147F78.c` |
| 90 | func_80151C54 | 134 | plumbing | 52 | failed | | none — MATCH (52 ins). Branch-polarity §3-T4: BD60 arm is fall-through (if !=1 && ==0x11), BC44 is else. | `.run/backlog_drafts/func_80151C54.c` |
| 101 | func_80173CB4 | 134 | schedule | 90 | failed | | none — MATCH (switch form keeps cases unmerged; final block: reuse one temp for the D_8012750C test + the func_8013767C result -> $a0 alloc; invert if to !=0 for branch polarity + store order) | `.run/backlog_drafts/func_80173CB4.c` |
| 102 | func_8014C6F4 | 134 | regalloc-order | 91 | failed | | 19-off loop tie-break — target compiles the search as a while/for (pre-guard sltu;beqz present) with the found pointer snapshotted to $v0 split from the IV in $a0 and the +4 sunk into both call-arg delay slots; do-while is instruction-count-exact (91=91) but lacks the pre-guard, while every for/while form costs +4 ins (merge stays in $a0). §10 schedule/regalloc residual. | `.run/backlog_drafts/func_8014C6F4.c` |
| 112 | func_80144090 | 134 | schedule | 154 | failed | | corner-block store/CSE schedule — gcc groups P+2/P-2 (share s>>6) vs target alternates P+2,P+4,P-2,P+0; plus otz*4 (sll $a0,$s5,2) scheduled late not into the D_800B9A02-load delay slot. Structure/regalloc all match (pins+array-of-struct %lo-fold+branch-polarity+mult-grouping landed; 144->52). Residual is §10 schedule tie-break, not source-steerable. | `.run/backlog_drafts/func_80144090.c` |
| 113 | func_8014F74C | 134 | other | 174 | failed | | none — MATCH (174 ins). Keys: sibling func_8014FA70 template; in/out/sp20 u8[8] short-trio bufs (lwl/lwr/swl/swr unaligned copies); load each a0 field once into b0/b1/b2 (stored to both sp20+out, reused in the 0x146-add block); 3-way memcpy branch on s1 (0x2000->D_801152A8, 0x4000->D_801152B0, else->D_800D3918); goto-form cmp-chain; final `""::: "memory"` barrier blocks gcc store-flag fold of (in4==out4)<<15 back to a branch | `.run/backlog_drafts/func_8014F74C.c` |
| 115 | func_80144B9C | 134 | other | 770 | failed | | -O0 cluster fn (prologue 21F0A003, fp-frame, all locals spilled+reloaded, load-delay nops). match_one compiles -O2 so it CANNOT match this; needs its own per-file -O0 split (Makefile CC1FLAGS:=-O0), like ov_SC01_077_o0.c. Body below is the faithful -O0 source; gate via whole-binary -O0 build only. | `.run/backlog_drafts/func_80144B9C.c` |
2. Read the batch; launch `tools/workflows/worker_wave.js` with `args={draftDir:".run/drafts-wave", targets:<batch array PASTED VERBATIM>}`.
3. On completion: `.venv/bin/python tools/orchestrator.py finish --drafts .run/drafts-wave --commit` — **BACKGROUNDED + `dangerouslyDisableSandbox`** (foreground make build/git get sandbox-killed exit 144). Prints `{banked, near, verified, fleet_pct, …}`.
4. **Distill EVERY wave that has `verified` banks:**`tools/workflows/distill.js``args={draftsDir:".run/drafts-wave", verified:<array>}` (the idiom-mining step).
5. Loop (~17 waves for all 420). close-rate should stay HIGH (small fns) → the orchestrator won't rotate off `reach1`; if it ever does (close-rate <0.15 ×2 → rotates to tractable walls), re-route: set `pool":"reach1"` in `.run/auto/orch_state.json`.
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Drew T