mirror/BFM-decomp
1
0
Fork 0
mirror of https://github.com/Druthulu/BFM-decomp synced 2026-10-07 01:18:49 -04:00
Code Issues Packages Projects Releases Wiki Activity

fix(phase-29): PsyQ MATRIX name hazard — the true 32B layout now owns the canonical name (R22 140/140)

Browse Source 
Oracle (G1, Ghidra types get, /LIBGTE.H, psyq400.gdt): MATRIX = 32 bytes (short m[3][3] @+0x00,
long t[3] @+0x14, 2B pad after m); SVECTOR = 8B; VECTOR = 16B (long vx,vy,vz,pad).

- HAZARD CONFIRMED: the fleet-wide name `MATRIX` held {s32 m[3][3]; s32 t[3]} = 48 BYTES, not a PsyQ
  type at all, while THREE other names (MATRIX_c1, MATRIX_c2, MATRIX2) held the true 32B layout. The
  canonical name carried an invention; any future reader assuming PsyQ semantics would be misled.
- FIXED by pure consistent rename across 205 files: 48B invention -> MATRIX_L48 (KEPT — ~131 files are
  byte-correct against it, and "fixing" it to 32B would change sizeof/array stride hence codegen);
  the true 32B layout now owns MATRIX. R22 clean-fleet 140/140 BYTE-IDENTICAL.
- VECTOR left UNCHANGED on purpose: ours is 12B vs PsyQ 16B (missing trailing pad). I first called it
  dead — wrong, it has 1 live use (engine_core.h gte_ldlv0((VECTOR*)sp)). Offsets already agree so a
  fix is likely byte-neutral, but it is a LAYOUT change and bundling it with a rename would make an
  R22 failure ambiguous. Own R22-gated commit, later.
- engine_types.h gains an oracle-sourced GROUND-TRUTH block: real PsyQ layouts, which of our names are
  true vs invented, why MATRIX_L48 must not be "corrected", and the draft-time rule (address-suffix
  anything you invent — 7 of the 8 collisions this fleet accumulated were bare generic names).
- SCOPE HELD: renamed + documented; did NOT force existing code onto real PsyQ definitions.
This commit is contained in:
Drew T
2026-07-23 21:35:07 -06:00
parent 8223bfc3a4
commit d1a1d756e0
205 changed files with 609 additions and 561 deletions
Download Patch File Download Diff File Expand all files Collapse all files
phase-ends/CURRENT_PHASE.md
+22
View File
@@ -1931,3 +1931,25 @@ conditional) · main-EXE/B9 + GLM/B6 + resident's 14 walls (P30) · behemoths B7
> FAILED); read the GATE's own output, never the wrapper's exit code (`| tail` masked a 103/140 failure as
> "exit 0"; a session fork later reported a GREEN run as "exit -1"); R14 applies to my own 3-line scripts —
> two produced false evidence before any project tool did.
- **✅ 2026-07-23 (SESSION-14 cont.) — PsyQ primitive-type CORRECTNESS: the `MATRIX` name hazard fixed.**
**Oracle-sourced (G1, Ghidra `types get`, /LIBGTE.H, psyq400.gdt):** `MATRIX` = **32B** (`short m[3][3]`
@+0x00, `long t[3]` @**+0x14** — 2B pad after m) · `SVECTOR` = 8B · `VECTOR` = **16B** (`long vx,vy,vz,pad`).
**THE HAZARD, CONFIRMED AND FIXED:** the fleet-wide name `MATRIX` held `{s32 m[3][3]; s32 t[3]}` = **48B,
NOT a PsyQ type**, while THREE other names (`MATRIX_c1`, `MATRIX_c2`, `MATRIX2`) held the true 32B layout.
Swapped by pure consistent rename across **205 files**: the 48B invention → **`MATRIX_L48`** (kept — ~131
files are byte-correct against it; "fixing" it to 32B would change sizeof/stride and therefore codegen),
and the true layout now owns **`MATRIX`**. **R22 clean-fleet 140/140 byte-identical.**
**`VECTOR` left UNCHANGED deliberately:** ours is 12B vs PsyQ's 16B (missing the trailing `pad`), and I
first called it dead — **WRONG, it has 1 live use** (`engine_core.h` `gte_ldlv0((VECTOR*)sp)`). vx/vy/vz
offsets already agree so a fix is likely byte-neutral, but it is a LAYOUT change and must not be bundled
with a rename (an R22 failure would then be ambiguous about which caused it). Own commit, later.
**`engine_types.h` now carries an oracle-sourced GROUND-TRUTH block** documenting the real layouts, which
of our names are true vs invented, and the draft-time rule (address-suffix anything you invent — 7 of the
8 collisions were bare generic names). SCOPE HELD: renamed + documented; did NOT force code onto real
PsyQ definitions.
**⚠️ EXIT-CODE TRAP, THIRD VARIANT TODAY:** this R22 was reported by the harness as **"failed, exit 1"** —
the exit came from my own trailing `grep -c '^\[FAIL\]'`, which returns 1 when it matches NOTHING. The
failure signal WAS the success. Today the wrapper status has been wrong three separate ways: `| tail`
masked a real 103/140 failure as exit 0; a session fork reported a green run as exit -1; and now
grep-no-match reported a green run as exit 1. **Read the gate's own output. Never the wrapper's status.**
src/ov_SC01_000/ov_SC01_000_jr_8017AE2C.c
+3 -3
View File
@@ -3078,7 +3078,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801A5694;
extern SV4 D_801A569C;
@@ -3086,7 +3086,7 @@ extern SV4 D_801A569C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A569C) */
@@ -3124,7 +3124,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A569C)) */
src/ov_SC01_000/ov_SC01_000_jr_8017BEBC.c
+2 -2
View File
@@ -3235,7 +3235,7 @@ INCLUDE_ASM("asm/ov_SC01_000/nonmatchings/ov_SC01_000_jr_8017BEBC", func_8017D1F
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3248,7 +3248,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D290(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC01_001/ov_SC01_001_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801ED924;
extern SV4 D_801ED92C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801ED92C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801ED92C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801ED92C)) */
src/ov_SC01_001/ov_SC01_001_jr_8017BEBC.c
+2 -2
View File
@@ -3215,7 +3215,7 @@ INCLUDE_ASM("asm/ov_SC01_001/nonmatchings/ov_SC01_001_jr_8017BEBC", func_8017D09
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3228,7 +3228,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D13C(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC01_004/ov_SC01_004_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_8019008C;
extern SV4 D_80190094;
@@ -3084,7 +3084,7 @@ extern SV4 D_80190094;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80190094) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80190094)) */
src/ov_SC01_005/ov_SC01_005_jr_8017AE2C.c
+3 -3
View File
@@ -3077,7 +3077,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801CD7EC;
extern SV4 D_801CD7F4;
@@ -3085,7 +3085,7 @@ extern SV4 D_801CD7F4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CD7F4) */
@@ -3123,7 +3123,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CD7F4)) */
src/ov_SC01_006/ov_SC01_006_jr_8017AE2C.c
+3 -3
View File
@@ -3077,7 +3077,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801CD7EC;
extern SV4 D_801CD7F4;
@@ -3085,7 +3085,7 @@ extern SV4 D_801CD7F4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CD7F4) */
@@ -3123,7 +3123,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CD7F4)) */
src/ov_SC01_008/ov_SC01_008_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801A329C;
extern SV4 D_801A32A4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801A32A4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A32A4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A32A4)) */
src/ov_SC01_009/ov_SC01_009_jr_8017AE2C.c
+3 -3
View File
@@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801F30FC;
extern SV4 D_801F3104;
@@ -3078,7 +3078,7 @@ extern SV4 D_801F3104;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801F3104) */
@@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801F3104)) */
src/ov_SC01_074/ov_SC01_074_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_8019BB7C;
extern SV4 D_8019BB84;
@@ -3084,7 +3084,7 @@ extern SV4 D_8019BB84;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019BB84) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019BB84)) */
src/ov_SC01_074/ov_SC01_074_jr_8017BE9C.c
+2 -2
View File
@@ -3344,7 +3344,7 @@ INCLUDE_ASM("asm/ov_SC01_074/nonmatchings/ov_SC01_074_jr_8017BE9C", func_8017DE0
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3357,7 +3357,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017DE88(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC01_080/ov_SC01_080_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C59AC;
extern SV4 D_801C59B4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801C59B4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C59B4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C59B4)) */
src/ov_SC01_084/ov_SC01_084_jr_8017AE2C.c
+3 -3
View File
@@ -3084,7 +3084,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C7454;
extern SV4 D_801C745C;
@@ -3092,7 +3092,7 @@ extern SV4 D_801C745C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C745C) */
@@ -3130,7 +3130,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C745C)) */
src/ov_SC02_000/ov_SC02_000_jr_8017AE2C.c
+3 -3
View File
@@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801E7F84;
extern SV4 D_801E7F8C;
@@ -3082,7 +3082,7 @@ extern SV4 D_801E7F8C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E7F8C) */
@@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E7F8C)) */
src/ov_SC02_003/ov_SC02_003_jr_8017AE2C.c
+3 -3
View File
@@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801E7F84;
extern SV4 D_801E7F8C;
@@ -3082,7 +3082,7 @@ extern SV4 D_801E7F8C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E7F8C) */
@@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E7F8C)) */
src/ov_SC02_004/ov_SC02_004_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801961D4;
extern SV4 D_801961DC;
@@ -3084,7 +3084,7 @@ extern SV4 D_801961DC;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801961DC) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801961DC)) */
src/ov_SC02_005/ov_SC02_005_jr_8017AE2C.c
+3 -3
View File
@@ -3078,7 +3078,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801E424C;
extern SV4 D_801E4254;
@@ -3086,7 +3086,7 @@ extern SV4 D_801E4254;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E4254) */
@@ -3124,7 +3124,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E4254)) */
src/ov_SC02_011/ov_SC02_011_jr_8017AE2C.c
+3 -3
View File
@@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801EB12C;
extern SV4 D_801EB134;
@@ -3078,7 +3078,7 @@ extern SV4 D_801EB134;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EB134) */
@@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EB134)) */
src/ov_SC02_015/ov_SC02_015_jr_8017AE2C.c
+3 -3
View File
@@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801902AC;
extern SV4 D_801902B4;
@@ -3082,7 +3082,7 @@ extern SV4 D_801902B4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801902B4) */
@@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801902B4)) */
src/ov_SC02_016/ov_SC02_016_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801B3EC4;
extern SV4 D_801B3ECC;
@@ -3084,7 +3084,7 @@ extern SV4 D_801B3ECC;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B3ECC) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B3ECC)) */
src/ov_SC02_016/ov_SC02_016_jr_8017DC70.c
+2 -2
View File
@@ -3245,7 +3245,7 @@ INCLUDE_ASM("asm/ov_SC02_016/nonmatchings/ov_SC02_016_jr_8017DC70", func_8017EE6
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3258,7 +3258,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017EF84(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC02_017/ov_SC02_017_jr_8017AE2C.c
+3 -3
View File
@@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801EF6EC;
extern SV4 D_801EF6F4;
@@ -3078,7 +3078,7 @@ extern SV4 D_801EF6F4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EF6F4) */
@@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EF6F4)) */
src/ov_SC02_021/ov_SC02_021_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_80192C5C;
extern SV4 D_80192C64;
@@ -3084,7 +3084,7 @@ extern SV4 D_80192C64;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80192C64) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80192C64)) */
src/ov_SC02_026/ov_SC02_026_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801D009C;
extern SV4 D_801D00A4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801D00A4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D00A4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D00A4)) */
src/ov_SC02_026/ov_SC02_026_jr_8017C180.c
+2 -2
View File
@@ -3260,7 +3260,7 @@ INCLUDE_ASM("asm/ov_SC02_026/nonmatchings/ov_SC02_026_jr_8017C180", func_8017D6D
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3273,7 +3273,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D780(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC02_027/ov_SC02_027_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801D9E0C;
extern SV4 D_801D9E14;
@@ -3084,7 +3084,7 @@ extern SV4 D_801D9E14;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D9E14) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D9E14)) */
src/ov_SC02_027/ov_SC02_027_jr_8017D898.c
+2 -2
View File
@@ -3313,7 +3313,7 @@ INCLUDE_ASM("asm/ov_SC02_027/nonmatchings/ov_SC02_027_jr_8017D898", func_8017F85
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3326,7 +3326,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017F918(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC02_028/ov_SC02_028_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801D2DAC;
extern SV4 D_801D2DB4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801D2DB4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D2DB4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D2DB4)) */
src/ov_SC02_028/ov_SC02_028_jr_8017D898.c
+2 -2
View File
@@ -3369,7 +3369,7 @@ INCLUDE_ASM("asm/ov_SC02_028/nonmatchings/ov_SC02_028_jr_8017D898", func_8017F8F
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3382,7 +3382,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017F9AC(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC02_031/ov_SC02_031_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801B7524;
extern SV4 D_801B752C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801B752C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B752C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B752C)) */
src/ov_SC02_035/ov_SC02_035_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801BE854;
extern SV4 D_801BE85C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801BE85C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801BE85C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801BE85C)) */
src/ov_SC02_035/ov_SC02_035_jr_8017BEBC.c
+2 -2
View File
@@ -3246,7 +3246,7 @@ INCLUDE_ASM("asm/ov_SC02_035/nonmatchings/ov_SC02_035_jr_8017BEBC", func_8017D13
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3259,7 +3259,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D1D0(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC02_039/ov_SC02_039_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801A0C04;
extern SV4 D_801A0C0C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801A0C0C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A0C0C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A0C0C)) */
src/ov_SC02_041/ov_SC02_041_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801B8F7C;
extern SV4 D_801B8F84;
@@ -3084,7 +3084,7 @@ extern SV4 D_801B8F84;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B8F84) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B8F84)) */
src/ov_SC02_041/ov_SC02_041_jr_8017BEBC.c
+2 -2
View File
@@ -3348,7 +3348,7 @@ INCLUDE_ASM("asm/ov_SC02_041/nonmatchings/ov_SC02_041_jr_8017BEBC", func_8017E37
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3361,7 +3361,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017E414(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_001/ov_SC03_001_jr_8017AE2C.c
+3 -3
View File
@@ -3074,7 +3074,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801EE5FC;
extern SV4 D_801EE604;
@@ -3082,7 +3082,7 @@ extern SV4 D_801EE604;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EE604) */
@@ -3120,7 +3120,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EE604)) */
src/ov_SC03_002/ov_SC03_002_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801CB67C;
extern SV4 D_801CB684;
@@ -3084,7 +3084,7 @@ extern SV4 D_801CB684;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CB684) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CB684)) */
src/ov_SC03_003/ov_SC03_003_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_8018F984;
extern SV4 D_8018F98C;
@@ -3084,7 +3084,7 @@ extern SV4 D_8018F98C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8018F98C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8018F98C)) */
src/ov_SC03_006/ov_SC03_006_jr_8017AE2C.c
+3 -3
View File
@@ -3071,7 +3071,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801F72FC;
extern SV4 D_801F7304;
@@ -3079,7 +3079,7 @@ extern SV4 D_801F7304;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801F7304) */
@@ -3117,7 +3117,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801F7304)) */
src/ov_SC03_007/ov_SC03_007_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801E9C54;
extern SV4 D_801E9C5C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801E9C5C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E9C5C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E9C5C)) */
src/ov_SC03_010/ov_SC03_010_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_8019FEB4;
extern SV4 D_8019FEBC;
@@ -3084,7 +3084,7 @@ extern SV4 D_8019FEBC;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019FEBC) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019FEBC)) */
src/ov_SC03_011/ov_SC03_011_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801A214C;
extern SV4 D_801A2154;
@@ -3084,7 +3084,7 @@ extern SV4 D_801A2154;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A2154) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A2154)) */
src/ov_SC03_012/ov_SC03_012_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_80194F6C;
extern SV4 D_80194F74;
@@ -3084,7 +3084,7 @@ extern SV4 D_80194F74;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80194F74) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80194F74)) */
src/ov_SC03_013/ov_SC03_013_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801AD23C;
extern SV4 D_801AD244;
@@ -3084,7 +3084,7 @@ extern SV4 D_801AD244;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801AD244) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801AD244)) */
src/ov_SC03_014/ov_SC03_014_jr_8017AE2C.c
+3 -3
View File
@@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801EA7BC;
extern SV4 D_801EA7C4;
@@ -3078,7 +3078,7 @@ extern SV4 D_801EA7C4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EA7C4) */
@@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EA7C4)) */
src/ov_SC03_014/ov_SC03_014_jr_8017EB7C.c
+2 -2
View File
@@ -3574,7 +3574,7 @@ INCLUDE_ASM("asm/ov_SC03_014/nonmatchings/ov_SC03_014_jr_8017EB7C", func_80183A5
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3587,7 +3587,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_80183B58(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_015/ov_SC03_015_jr_8017AE2C.c
+3 -3
View File
@@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801EA7BC;
extern SV4 D_801EA7C4;
@@ -3078,7 +3078,7 @@ extern SV4 D_801EA7C4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EA7C4) */
@@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EA7C4)) */
src/ov_SC03_015/ov_SC03_015_jr_8017EB7C.c
+2 -2
View File
@@ -3555,7 +3555,7 @@ INCLUDE_ASM("asm/ov_SC03_015/nonmatchings/ov_SC03_015_jr_8017EB7C", func_80183A5
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3568,7 +3568,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_80183B58(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_023/ov_SC03_023_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_80198B94;
extern SV4 D_80198B9C;
@@ -3084,7 +3084,7 @@ extern SV4 D_80198B9C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80198B9C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80198B9C)) */
src/ov_SC03_024/ov_SC03_024_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C112C;
extern SV4 D_801C1134;
@@ -3084,7 +3084,7 @@ extern SV4 D_801C1134;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C1134) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C1134)) */
src/ov_SC03_024/ov_SC03_024_jr_8017DF84.c
+2 -2
View File
@@ -3433,7 +3433,7 @@ INCLUDE_ASM("asm/ov_SC03_024/nonmatchings/ov_SC03_024_jr_8017DF84", func_80180E6
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3446,7 +3446,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_80180EA8(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_028/ov_SC03_028_jr_8017AE2C.c
+5 -5
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX_c1: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801EB464;
extern SV4 D_801EB46C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801EB46C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801EB46C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_c1, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801EB46C)) */
@@ -3571,7 +3571,7 @@ INCLUDE_ASM("asm/ov_SC03_028/nonmatchings/ov_SC03_028_jr_8017AE2C", func_8017FE1
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3584,7 +3584,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017FF68(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_029/ov_SC03_029_jr_8017AE2C.c
+3 -3
View File
@@ -3070,7 +3070,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801D943C;
extern SV4 D_801D9444;
@@ -3078,7 +3078,7 @@ extern SV4 D_801D9444;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D9444) */
@@ -3116,7 +3116,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D9444)) */
src/ov_SC03_030/ov_SC03_030_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801E1A34;
extern SV4 D_801E1A3C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801E1A3C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801E1A3C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801E1A3C)) */
src/ov_SC03_031/ov_SC03_031_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C5E34;
extern SV4 D_801C5E3C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801C5E3C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C5E3C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C5E3C)) */
src/ov_SC03_089/ov_SC03_089_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C66EC;
extern SV4 D_801C66F4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801C66F4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C66F4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C66F4)) */
src/ov_SC03_089/ov_SC03_089_jr_8017CA80.c
+2 -2
View File
@@ -3380,7 +3380,7 @@ INCLUDE_ASM("asm/ov_SC03_089/nonmatchings/ov_SC03_089_jr_8017CA80", func_80181B1
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3393,7 +3393,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_80181BCC(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_090/ov_SC03_090_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801CBB54;
extern SV4 D_801CBB5C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801CBB5C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CBB5C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CBB5C)) */
src/ov_SC03_090/ov_SC03_090_jr_8017CA80.c
+2 -2
View File
@@ -3380,7 +3380,7 @@ INCLUDE_ASM("asm/ov_SC03_090/nonmatchings/ov_SC03_090_jr_8017CA80", func_80181C8
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3393,7 +3393,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_80181D30(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_091/ov_SC03_091_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801D2224;
extern SV4 D_801D222C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801D222C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D222C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D222C)) */
src/ov_SC03_091/ov_SC03_091_jr_80182268.c
+2 -2
View File
@@ -2758,7 +2758,7 @@ INCLUDE_ASM("asm/ov_SC03_091/nonmatchings/ov_SC03_091_jr_80182268", func_80182A9
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -2771,7 +2771,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_80182B48(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_092/ov_SC03_092_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801B2DEC;
extern SV4 D_801B2DF4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801B2DF4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B2DF4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B2DF4)) */
src/ov_SC03_093/ov_SC03_093_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801CC25C;
extern SV4 D_801CC264;
@@ -3084,7 +3084,7 @@ extern SV4 D_801CC264;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801CC264) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801CC264)) */
src/ov_SC03_093/ov_SC03_093_jr_8017D898.c
+2 -2
View File
@@ -3276,7 +3276,7 @@ INCLUDE_ASM("asm/ov_SC03_093/nonmatchings/ov_SC03_093_jr_8017D898", func_8017EE3
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3289,7 +3289,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017EF20(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_094/ov_SC03_094_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801D309C;
extern SV4 D_801D30A4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801D30A4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801D30A4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801D30A4)) */
src/ov_SC03_094/ov_SC03_094_jr_8017BEBC.c
+2 -2
View File
@@ -3264,7 +3264,7 @@ INCLUDE_ASM("asm/ov_SC03_094/nonmatchings/ov_SC03_094_jr_8017BEBC", func_8017D63
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3277,7 +3277,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D6D0(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_095/ov_SC03_095_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_8019BC94;
extern SV4 D_8019BC9C;
@@ -3084,7 +3084,7 @@ extern SV4 D_8019BC9C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019BC9C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019BC9C)) */
src/ov_SC03_095/ov_SC03_095_jr_8017BEBC.c
+2 -2
View File
@@ -3252,7 +3252,7 @@ INCLUDE_ASM("asm/ov_SC03_095/nonmatchings/ov_SC03_095_jr_8017BEBC", func_8017D2A
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3265,7 +3265,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D390(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_096/ov_SC03_096_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_8019A74C;
extern SV4 D_8019A754;
@@ -3084,7 +3084,7 @@ extern SV4 D_8019A754;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019A754) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019A754)) */
src/ov_SC03_096/ov_SC03_096_jr_8017BEBC.c
+2 -2
View File
@@ -3246,7 +3246,7 @@ INCLUDE_ASM("asm/ov_SC03_096/nonmatchings/ov_SC03_096_jr_8017BEBC", func_8017D13
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3259,7 +3259,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D238(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_097/ov_SC03_097_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801AA7D4;
extern SV4 D_801AA7DC;
@@ -3084,7 +3084,7 @@ extern SV4 D_801AA7DC;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801AA7DC) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801AA7DC)) */
src/ov_SC03_097/ov_SC03_097_jr_8017D898.c
+2 -2
View File
@@ -3379,7 +3379,7 @@ INCLUDE_ASM("asm/ov_SC03_097/nonmatchings/ov_SC03_097_jr_8017D898", func_8017F48
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3392,7 +3392,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017F53C(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_098/ov_SC03_098_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C5444;
extern SV4 D_801C544C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801C544C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C544C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C544C)) */
src/ov_SC03_098/ov_SC03_098_jr_8017D898.c
+2 -2
View File
@@ -3270,7 +3270,7 @@ INCLUDE_ASM("asm/ov_SC03_098/nonmatchings/ov_SC03_098_jr_8017D898", func_8017ECC
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3283,7 +3283,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017ED60(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_099/ov_SC03_099_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801BF114;
extern SV4 D_801BF11C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801BF11C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801BF11C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801BF11C)) */
src/ov_SC03_099/ov_SC03_099_jr_8017BEBC.c
+2 -2
View File
@@ -3252,7 +3252,7 @@ INCLUDE_ASM("asm/ov_SC03_099/nonmatchings/ov_SC03_099_jr_8017BEBC", func_8017D2A
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3265,7 +3265,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D364(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_100/ov_SC03_100_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C839C;
extern SV4 D_801C83A4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801C83A4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C83A4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C83A4)) */
src/ov_SC03_100/ov_SC03_100_jr_8017D898.c
+2 -2
View File
@@ -3260,7 +3260,7 @@ INCLUDE_ASM("asm/ov_SC03_100/nonmatchings/ov_SC03_100_jr_8017D898", func_8017EC8
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3273,7 +3273,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017ED90(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_101/ov_SC03_101_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_8019DC64;
extern SV4 D_8019DC6C;
@@ -3084,7 +3084,7 @@ extern SV4 D_8019DC6C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019DC6C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019DC6C)) */
src/ov_SC03_101/ov_SC03_101_jr_8017CA80.c
+2 -2
View File
@@ -3303,7 +3303,7 @@ INCLUDE_ASM("asm/ov_SC03_101/nonmatchings/ov_SC03_101_jr_8017CA80", func_8017E0B
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3316,7 +3316,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017E174(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_102/ov_SC03_102_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801B98DC;
extern SV4 D_801B98E4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801B98E4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B98E4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B98E4)) */
src/ov_SC03_102/ov_SC03_102_jr_8017BEBC.c
+2 -2
View File
@@ -3260,7 +3260,7 @@ INCLUDE_ASM("asm/ov_SC03_102/nonmatchings/ov_SC03_102_jr_8017BEBC", func_8018055
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3273,7 +3273,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_80180628(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_103/ov_SC03_103_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C4A94;
extern SV4 D_801C4A9C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801C4A9C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C4A9C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C4A9C)) */
src/ov_SC03_103/ov_SC03_103_jr_8017C294.c
+2 -2
View File
@@ -3274,7 +3274,7 @@ INCLUDE_ASM("asm/ov_SC03_103/nonmatchings/ov_SC03_103_jr_8017C294", func_8017E36
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3287,7 +3287,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017E40C(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_104/ov_SC03_104_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801C002C;
extern SV4 D_801C0034;
@@ -3084,7 +3084,7 @@ extern SV4 D_801C0034;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801C0034) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801C0034)) */
src/ov_SC03_104/ov_SC03_104_jr_8017CA80.c
+2 -2
View File
@@ -3320,7 +3320,7 @@ INCLUDE_ASM("asm/ov_SC03_104/nonmatchings/ov_SC03_104_jr_8017CA80", func_8018152
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3333,7 +3333,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_801815DC(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_105/ov_SC03_105_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801B95BC;
extern SV4 D_801B95C4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801B95C4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B95C4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B95C4)) */
src/ov_SC03_105/ov_SC03_105_jr_8017C8D0.c
+2 -2
View File
@@ -3254,7 +3254,7 @@ INCLUDE_ASM("asm/ov_SC03_105/nonmatchings/ov_SC03_105_jr_8017C8D0", func_8017E18
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3267,7 +3267,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017E33C(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_108/ov_SC03_108_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801A18AC;
extern SV4 D_801A18B4;
@@ -3084,7 +3084,7 @@ extern SV4 D_801A18B4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A18B4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A18B4)) */
src/ov_SC03_109/ov_SC03_109_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_8019A2BC;
extern SV4 D_8019A2C4;
@@ -3084,7 +3084,7 @@ extern SV4 D_8019A2C4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_8019A2C4) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_8019A2C4)) */
src/ov_SC03_109/ov_SC03_109_jr_8017C180.c
+2 -2
View File
@@ -3246,7 +3246,7 @@ INCLUDE_ASM("asm/ov_SC03_109/nonmatchings/ov_SC03_109_jr_8017C180", func_8017D3C
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3259,7 +3259,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017D48C(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_110/ov_SC03_110_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801A2064;
extern SV4 D_801A206C;
@@ -3084,7 +3084,7 @@ extern SV4 D_801A206C;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A206C) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A206C)) */
src/ov_SC03_110/ov_SC03_110_jr_8017D898.c
+2 -2
View File
@@ -3262,7 +3262,7 @@ INCLUDE_ASM("asm/ov_SC03_110/nonmatchings/ov_SC03_110_jr_8017D898", func_8017EB1
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3275,7 +3275,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017EBFC(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_111/ov_SC03_111_jr_8017AE2C.c
+3 -3
View File
@@ -3076,7 +3076,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801B956C;
extern SV4 D_801B9574;
@@ -3084,7 +3084,7 @@ extern SV4 D_801B9574;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801B9574) */
@@ -3122,7 +3122,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801B9574)) */
src/ov_SC03_112/ov_SC03_112_jr_8017AE2C.c
+3 -3
View File
@@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801ACDCC;
extern SV4 D_801ACDD4;
@@ -3083,7 +3083,7 @@ extern SV4 D_801ACDD4;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801ACDD4) */
@@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801ACDD4)) */
src/ov_SC03_113/ov_SC03_113_jr_8017AE2C.c
+3 -3
View File
@@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801A595C;
extern SV4 D_801A5964;
@@ -3083,7 +3083,7 @@ extern SV4 D_801A5964;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A5964) */
@@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A5964)) */
src/ov_SC03_113/ov_SC03_113_jr_8017C294.c
+2 -2
View File
@@ -3295,7 +3295,7 @@ INCLUDE_ASM("asm/ov_SC03_113/nonmatchings/ov_SC03_113_jr_8017C294", func_8017F15
// @class: schedule
// @stuck: none — MATCH (102 ins). MATRIX_c1(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// @stuck: none — MATCH (102 ins). MATRIX(0x20:m@0,t@0x14)+SVECTOR in/out stack layout; the only
// lever past struct-layout was source order: emit m1.t[2] BEFORE svec_in.vx/vy so the two `sh
// zero` stores schedule into the t[2] load-delay slot (after the a1 setup), not after t[1].
@@ -3308,7 +3308,7 @@ extern void func_80049CAC(s32 a0, s32 a1);
extern void func_8012F14C(s32);
void func_8017F1FC(s32 param_1, s16 *param_2) {
MATRIX_c1 m1;
MATRIX m1;
SVECTOR svec_in;
SVECTOR svec_out;
src/ov_SC03_114/ov_SC03_114_jr_8017AE2C.c
+3 -3
View File
@@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_801A95F4;
extern SV4 D_801A95FC;
@@ -3083,7 +3083,7 @@ extern SV4 D_801A95FC;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_801A95FC) */
@@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_801A95FC)) */
src/ov_SC03_115/ov_SC03_115_jr_8017AE2C.c
+3 -3
View File
@@ -3075,7 +3075,7 @@ extern void RotTransSV(void *a0, void *a1, void *a2);
/* short-only (align 2) struct -> the 8-byte struct copy emits lwl/lwr/swl/swr */
/* PSX MATRIX: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
/* PSX MATRIX_L48: 3x3 short rotation + pad + 3 long translation (offset 0x14) */
extern SV4 D_80194F4C;
extern SV4 D_80194F54;
@@ -3083,7 +3083,7 @@ extern SV4 D_80194F54;
void func_8017BA3C(s32 param_1, s32 param_2)
{
SV4 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4 v1; /* sp+0x38 : RotTransSV arg0 */
SV4 svec; /* sp+0x40 : func_8012F214 out */
SV4 buf1; /* sp+0x48 : RotTransSV arg1 (-> D_80194F54) */
@@ -3121,7 +3121,7 @@ void func_8017BA3C(s32 param_1, s32 param_2)
s32 func_8017BB34(s32 param_1, s32 param_2)
{
SV4_8017BB34 v0; /* sp+0x10 : func_80049CAC arg0 */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX, t[] at sp+0x2c */
MTX_8017BB34 mtx; /* sp+0x18 : MATRIX_L48, t[] at sp+0x2c */
SV4_8017BB34 v1; /* sp+0x38 : RotTransSV arg0 */
SV4_8017BB34 svec; /* sp+0x40 */
SV4_8017BB34 buf1; /* sp+0x48 : RotTransSV arg1 (-> (*(SV4_8017BB34*)&D_80194F54)) */

Some files were not shown because too many files have changed in this diff Show More