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feat: added more instructions

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Ran-j
2025-04-15 14:42:41 -03:00
parent acc6afca78
commit b21c7bbb82
6 changed files with 999 additions and 109 deletions
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ps2xRecomp/include/ps2recomp/code_generator.h
+34
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@@ -26,6 +26,40 @@ namespace ps2recomp
std::string translateVUInstruction(const Instruction &inst);
std::string translateFPUInstruction(const Instruction &inst);
std::string translateCOP0Instruction(const Instruction &inst);
std::string translateSpecialInstruction(const Instruction &inst);
// MMI instruction translations
std::string translateQFSRV(const Instruction &inst);
std::string translatePCPYLD(const Instruction &inst);
std::string translatePCPYUD(const Instruction &inst);
std::string translatePMADDW(const Instruction &inst);
std::string translatePMADDH(const Instruction &inst);
std::string translatePHMADH(const Instruction &inst);
std::string translatePMULTH(const Instruction &inst);
std::string translatePDIVW(const Instruction &inst);
std::string translatePDIVBW(const Instruction &inst);
std::string translatePEXEH(const Instruction &inst);
std::string translatePREVH(const Instruction &inst);
std::string translatePEXEW(const Instruction &inst);
std::string translatePROT3W(const Instruction &inst);
// SPECIAL instructions
std::string translateSYNC(const Instruction &inst);
std::string translateEI(const Instruction &inst);
std::string translateDI(const Instruction &inst);
std::string translateDSLL(const Instruction &inst);
std::string translateDSRL(const Instruction &inst);
std::string translateDSRA(const Instruction &inst);
std::string translateDSLLV(const Instruction &inst);
std::string translateDSRLV(const Instruction &inst);
std::string translateDSRAV(const Instruction &inst);
std::string translateDSLL32(const Instruction &inst);
std::string translateDSRL32(const Instruction &inst);
std::string translateDSRA32(const Instruction &inst);
std::string translateDADD(const Instruction &inst);
std::string translateDADDU(const Instruction &inst);
std::string translateDSUB(const Instruction &inst);
std::string translateDSUBU(const Instruction &inst);
std::string generateJumpTableSwitch(const Instruction &inst, uint32_t tableAddress,
const std::vector<JumpTableEntry> &entries);
ps2xRecomp/include/ps2recomp/instructions.h
+38 -12
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@@ -280,24 +280,50 @@ namespace ps2recomp
MMI3_PEXCW = 0x1E,
};
// COP0 (System Control) function codes
enum Cop0Functions
// COP0 (rs field)
enum COP0Format
{
COP0_MF = 0x00,
COP0_MT = 0x04,
COP0_CO = 0x10 // COProcessor commands
COP0_MF = 0x00, // Move From COP0
COP0_MT = 0x04, // Move To COP0
COP0_CO = 0x10 // COP0 operation
};
// COP0 CO (COProcessor) function codes
enum Cop0CoFunctions
{
COP0_CO_TLBR = 0x01,
COP0_CO_TLBWI = 0x02,
COP0_CO_TLBWR = 0x06,
COP0_CO_TLBP = 0x08,
COP0_CO_ERET = 0x18,
COP0_CO_EI = 0x38,
COP0_CO_DI = 0x39
COP0_CO_TLBR = 0x01, // TLB Read
COP0_CO_TLBWI = 0x02, // TLB Write Indexed
COP0_CO_TLBWR = 0x06, // TLB Write Random
COP0_CO_TLBP = 0x08, // TLB Probe
COP0_CO_ERET = 0x18, // Return from Exception
COP0_CO_EI = 0x38, // Enable Interrupts
COP0_CO_DI = 0x39 // Disable Interrupts
};
enum COP0Reg
{
COP0_REG_INDEX = 0, // Index into TLB array
COP0_REG_RANDOM = 1, // Randomly generated index into TLB array
COP0_REG_ENTRYLO0 = 2, // Low half of TLB entry for even-numbered virtual pages
COP0_REG_ENTRYLO1 = 3, // Low half of TLB entry for odd-numbered virtual pages
COP0_REG_CONTEXT = 4, // TLB miss handler pointer
COP0_REG_PAGEMASK = 5, // TLB page size mask
COP0_REG_WIRED = 6, // Controls which TLB entries are affected by random replacement
COP0_REG_BADVADDR = 8, // Virtual address of most recent address-related exception
COP0_REG_COUNT = 9, // Timer count
COP0_REG_ENTRYHI = 10, // High half of TLB entry
COP0_REG_COMPARE = 11, // Timer compare value
COP0_REG_STATUS = 12, // Processor status and control
COP0_REG_CAUSE = 13, // Cause of last exception
COP0_REG_EPC = 14, // Exception program counter
COP0_REG_PRID = 15, // Processor identification and revision
COP0_REG_CONFIG = 16, // Configuration register
COP0_REG_BADPADDR = 23, // Bad physical address
COP0_REG_DEBUG = 24, // Debug register
COP0_REG_PERF = 25, // Performance counter
COP0_REG_TAGLO = 28, // Low bits of cache tag
COP0_REG_TAGHI = 29, // High bits of cache tag
COP0_REG_ERROREPC = 30 // Error exception program counter
};
// COP1 (FPU) function codes
ps2xRecomp/include/ps2recomp/r5900_decoder.h
+4 -1
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@@ -36,14 +36,17 @@ namespace ps2recomp
void decodeSpecial(Instruction &inst) const;
void decodeRegimm(Instruction &inst) const;
void decodeMMI(Instruction &inst) const;
void decodeCOP0(Instruction& inst) const;
void decodeCOP1(Instruction &inst) const;
void decodeCOP2(Instruction &inst) const;
void decodeMMI(Instruction &inst) const;
void decodeMMI0(Instruction &inst) const;
void decodeMMI1(Instruction &inst) const;
void decodeMMI2(Instruction &inst) const;
void decodeMMI3(Instruction &inst) const;
void decodePMFHL(Instruction &inst) const;
};
ps2xRecomp/src/code_generator.cpp
+841 -76
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File diff suppressed because it is too large Load Diff
ps2xRuntime/include/ps2_runtime.h
+82 -8
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@@ -8,8 +8,17 @@
#include <functional>
#include <immintrin.h> // For SSE/AVX instructions
#define PS2_RAM_SIZE 0x2000000 // 32MB
#define PS2_SCRATCHPAD_SIZE 0x4000 // 16KB
constexpr uint32_t PS2_RAM_BASE = 0x00000000;
constexpr uint32_t PS2_RAM_SIZE = 32 * 1024 * 1024; // 32MB
constexpr uint32_t PS2_SCRATCHPAD_BASE = 0x70000000;
constexpr uint32_t PS2_SCRATCHPAD_SIZE = 16 * 1024; // 16KB
constexpr uint32_t PS2_IO_BASE = 0x10000000;
constexpr uint32_t PS2_IO_SIZE = 0x10000; // 64KB
constexpr uint32_t PS2_VU0_CODE_BASE = 0x11000000;
constexpr uint32_t PS2_VU0_DATA_BASE = 0x11004000;
constexpr uint32_t PS2_VU1_CODE_BASE = 0x11008000;
constexpr uint32_t PS2_VU1_DATA_BASE = 0x1100C000;
constexpr uint32_t PS2_GS_BASE = 0x12000000;
// PS2 CPU context (R5900)
struct R5900Context
@@ -19,10 +28,13 @@ struct R5900Context
// Program Counter Hi/Lo registers (64-bit)
uint32_t pc;
uint64_t insn_count;
uint32_t hi; // High result register
uint32_t lo; // Low result register
uint32_t sa; // Shift amount register
uint32_t lo1, hi1; // For MULT1/DIV1 instructions
// 128-bit registers for SIMD operations
__m128i r128[32];
@@ -42,19 +54,81 @@ struct R5900Context
uint32_t cop0_cause; // Cause register
uint32_t cop0_epc; // Exception PC
uint32_t cop0_prid;
uint32_t cop0_index;
uint32_t cop0_random;
uint32_t cop0_entrylo0;
uint32_t cop0_entrylo1;
uint32_t cop0_context;
uint32_t cop0_pagemask;
uint32_t cop0_wired;
uint32_t cop0_badvaddr;
uint32_t cop0_count;
uint32_t cop0_entryhi;
uint32_t cop0_compare;
uint32_t cop0_config;
uint32_t cop0_badpaddr;
uint32_t cop0_debug;
uint32_t cop0_perf;
uint32_t cop0_taglo;
uint32_t cop0_taghi;
uint32_t cop0_errorepc;
// FPU registers (COP1)
float f[32];
uint32_t fcr0; // Implementation/revision register
uint32_t fcr31; // Control/status register
// Branch delay slot tracking
bool in_delay_slot;
uint32_t branch_target;
R5900Context()
{
// Zero all registers
for (int i = 0; i < 32; i++)
{
r[i] = _mm_setzero_si128();
f[i] = 0.0f;
vu0_vf[i] = _mm_setzero_ps();
}
// Function call stack for profiling and debugging
uint32_t call_stack[16];
int call_stack_depth;
pc = 0;
insn_count = 0;
lo = hi = lo1 = hi1 = 0;
sa = 0;
// Reset COP0 registers
cop0_index = 0;
cop0_random = 47; // Start at maximum value
cop0_entrylo0 = 0;
cop0_entrylo1 = 0;
cop0_context = 0;
cop0_pagemask = 0;
cop0_wired = 0;
cop0_badvaddr = 0;
cop0_count = 0;
cop0_entryhi = 0;
cop0_compare = 0;
cop0_status = 0x400000; // BEV set, ERL clear, kernel mode
cop0_cause = 0;
cop0_epc = 0;
cop0_prid = 0x00002e20; // CPU ID for R5900
cop0_config = 0;
cop0_badpaddr = 0;
cop0_debug = 0;
cop0_perf = 0;
cop0_taglo = 0;
cop0_taghi = 0;
cop0_errorepc = 0;
// Reset COP1/VU0 state
fcr31 = 0;
vu0_q = 0.0f;
vu0_i = 0.0f;
vu0_status = 0;
// Set the FPU registers to predictable but non-zero values
for (int i = 0; i < 32; i++)
{
f[i] = static_cast<float>(i);
}
}
};
// PS2 GS (Graphics Synthesizer) registers
ps2xRuntime/src/ps2_memory.cpp
-12
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@@ -3,18 +3,6 @@
#include <cstring>
#include <stdexcept>
constexpr uint32_t PS2_RAM_BASE = 0x00000000;
constexpr uint32_t PS2_RAM_SIZE = 32 * 1024 * 1024; // 32MB
constexpr uint32_t PS2_SCRATCHPAD_BASE = 0x70000000;
constexpr uint32_t PS2_SCRATCHPAD_SIZE = 16 * 1024; // 16KB
constexpr uint32_t PS2_IO_BASE = 0x10000000;
constexpr uint32_t PS2_IO_SIZE = 0x10000; // 64KB
constexpr uint32_t PS2_VU0_CODE_BASE = 0x11000000;
constexpr uint32_t PS2_VU0_DATA_BASE = 0x11004000;
constexpr uint32_t PS2_VU1_CODE_BASE = 0x11008000;
constexpr uint32_t PS2_VU1_DATA_BASE = 0x1100C000;
constexpr uint32_t PS2_GS_BASE = 0x12000000;
PS2Memory::PS2Memory()
: m_rdram(nullptr), m_scratchpad(nullptr)
{