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https://github.com/open-goal/jak-project
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goalc/arm: adds and subtracts
This commit is contained in:
Tyler Wilding
+110
-45
@@ -652,83 +652,146 @@ InstructionARM64 jmp_r64(Register reg) {
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// INTEGER MATH
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//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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// NOTE: ARM can actually handle 12-bit immediate values, so if it's actually worth it, we
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// could leverage these instructions for more than just 8-bit values
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InstructionARM64 sub_gpr64_imm8s(Register reg, int64_t imm) {
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// You cannot subtract or add with a negative immediate in ARM
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// therefore depending on the value of the immediate, we use a different instruction
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ASSERT(reg.is_gpr(instr_set));
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if (imm < 0) {
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return add_gpr64_imm8s(reg, std::abs(imm));
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}
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// https://www.scs.stanford.edu/~zyedidia/arm64/sub_addsub_imm.html
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// - SUB <Xd>, <Xn>, #imm12 {, LSL #12}
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// - using a shift of 0 here (last bit in the base)
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return InstructionARM64(Base(0b1101000100, 10), Imm12(imm), Rn(reg.id()), Rd(reg.id()));
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return sub_gpr64_imm(reg, imm);
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}
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// NOTE: ARM can actually handle 12-bit immediate values, so if it's actually worth it, we
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// could leverage these instructions for more than just 8-bit values
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InstructionARM64 add_gpr64_imm8s(Register reg, int64_t imm) {
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// You cannot subtract or add with a negative immediate in ARM
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// therefore depending on the value of the immediate, we use a different instruction
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ASSERT(reg.is_gpr(instr_set));
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if (imm < 0) {
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return sub_gpr64_imm8s(reg, abs(imm));
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}
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// https://www.scs.stanford.edu/~zyedidia/arm64/add_addsub_imm.html
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// ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
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return InstructionARM64(Base(0b1001000100, 10), Imm12(imm), Rn(reg.id()), Rd(reg.id()));
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return add_gpr64_imm(reg, imm);
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}
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InstructionARM64 sub_gpr64_imm32s(Register reg, int64_t imm) {
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// ARM64 does not support this kind of single-instruction
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ASSERT_MSG(false, "sub_gpr64_imm32s not supported on ARM64");
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return InstructionARM64(0b0);
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return sub_gpr64_imm(reg, imm);
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}
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InstructionARM64 add_gpr64_imm32s(Register reg, int64_t imm) {
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// ARM64 does not support this kind of single-instruction
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ASSERT_MSG(false, "sub_gpr64_imm32s not supported on ARM64");
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return InstructionARM64(0b0);
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return add_gpr64_imm(reg, imm);
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}
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// Checks whether or not an immediate can be represented in 12 unsigned bits, either:
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// - plain [0-4095] immediate
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// - imm << 12 (some multiple of 4096)
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std::tuple<bool, u16, bool> can_encode_single_imm12(u64 imm) {
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if (imm < 4096) {
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return {true, static_cast<u16>(imm), false};
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}
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if ((imm & 0xFFF) == 0) { // divisible by 4096
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uint32_t upper = imm >> 12;
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if (upper < 4096) {
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return {true, static_cast<uint16_t>(upper), true};
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}
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}
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return {false, 0, false};
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}
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// Given a larger than u12 immediate, decompose it into multiple (shifted or not)
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// immediates that can be used to emit multiple instructions to produce the desired outcome
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std::vector<std::tuple<u16, bool>> decompose_into_imm12_chunks(u64 imm) {
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std ::vector<std::tuple<u16, bool>> result;
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u32 upper = imm >> 12;
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while (upper > 0) {
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u16 chunk = (upper > 4095) ? 4095 : static_cast<u16>(upper);
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result.emplace_back(chunk, true);
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upper -= chunk;
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}
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u16 lower = imm & 0xFFF;
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if (lower > 0) {
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result.emplace_back(lower, false);
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}
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return result;
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}
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InstructionARM64 add_gpr64_imm(Register reg, int64_t imm) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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ASSERT(reg.is_gpr(instr_set));
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if (imm < 0) {
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sub_gpr64_imm(reg, std::abs(imm));
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}
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// Check to see if we can represent this subtraction in a single instruction
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// if not, then we need to emit multiple partial instructions
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const auto [is_single_instr, imm12, needs_shift] = can_encode_single_imm12(imm);
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if (is_single_instr) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/add_addsub_imm.html
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// ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
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return InstructionARM64(Base(0b100100010, 9), Sh(needs_shift ? 1 : 0), Imm12(imm12),
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Rd(reg.id()), Rn(reg.id()));
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} else {
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const auto chunks = decompose_into_imm12_chunks(imm);
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std::vector<InstructionARM64> instrs;
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for (const auto& [_imm12, _needs_shift] : chunks) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/add_addsub_imm.html
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// ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
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instrs.emplace_back(InstructionARM64(Base(0b100100010, 9), Sh(_needs_shift ? 1 : 0),
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Imm12(_imm12), Rd(reg.id()), Rn(reg.id())));
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}
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return InstructionARM64(instrs);
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}
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}
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InstructionARM64 sub_gpr64_imm(Register reg, int64_t imm) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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ASSERT(reg.is_gpr(instr_set));
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if (imm < 0) {
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add_gpr64_imm(reg, std::abs(imm));
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}
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// Check to see if we can represent this subtraction in a single instruction
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// if not, then we need to emit multiple partial instructions
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const auto [is_single_instr, imm12, needs_shift] = can_encode_single_imm12(imm);
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if (is_single_instr) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/sub_addsub_imm.html
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// SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
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return InstructionARM64(Base(0b110100010, 9), Sh(needs_shift ? 1 : 0), Imm12(imm12),
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Rd(reg.id()), Rn(reg.id()));
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} else {
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const auto chunks = decompose_into_imm12_chunks(imm);
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std::vector<InstructionARM64> instrs;
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for (const auto& [_imm12, _needs_shift] : chunks) {
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// https://www.scs.stanford.edu/~zyedidia/arm64/sub_addsub_imm.html
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// SUB <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
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instrs.emplace_back(InstructionARM64(Base(0b110100010, 9), Sh(_needs_shift ? 1 : 0),
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Imm12(_imm12), Rd(reg.id()), Rn(reg.id())));
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}
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return InstructionARM64(instrs);
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}
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}
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InstructionARM64 add_gpr64_gpr64(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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// https://www.scs.stanford.edu/~zyedidia/arm64/add_addsub_shift.html
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// ADD <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
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return InstructionARM64(Base(0b10001011000, 11), Rd(dst.id()), Imm6(0), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 sub_gpr64_gpr64(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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// https://www.scs.stanford.edu/~zyedidia/arm64/sub_addsub_shift.html
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// SUB <Xd>, <Xn>, <Xm>{, <shift> #<amount>}
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return InstructionARM64(Base(0b11001011000, 11), Rd(dst.id()), Imm6(0), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 imul_gpr32_gpr32(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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// https://www.scs.stanford.edu/~zyedidia/arm64/mul_madd.html
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// MUL <Wd>, <Wn>, <Wm>
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return InstructionARM64(Base(0b0001101100000000011111, 22), Rd(dst.id()), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 imul_gpr64_gpr64(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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// https://www.scs.stanford.edu/~zyedidia/arm64/mul_madd.html
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// MUL <Xd>, <Xn>, <Xm>
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return InstructionARM64(Base(0b1001101100000000011111, 22), Rd(dst.id()), Rn(dst.id()),
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Rm(src.id()));
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}
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InstructionARM64 idiv_gpr32(Register reg) {
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// divides on x86 are annoying, its one of many that involve hard-coded register src/destinations,
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// deal with it last
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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}
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InstructionARM64 unsigned_div_gpr32(Register reg) {
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// divides on x86 are annoying, its one of many that involve hard-coded register src/destinations,
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// deal with it last
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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}
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@@ -743,13 +806,15 @@ InstructionARM64 cdq() {
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}
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InstructionARM64 movsx_r64_r32(Register dst, Register src) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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// https://www.scs.stanford.edu/~zyedidia/arm64/sxtw_sbfm.html
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// SXTW <Xd>, <Wn>
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return InstructionARM64(Base(0b1001001101000000011111, 22), Rd(dst.id()), Rn(src.id()));
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}
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InstructionARM64 cmp_gpr64_gpr64(Register a, Register b) {
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ASSERT_MSG(false, "not yet implemented");
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return InstructionARM64(0b0);
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// https://www.scs.stanford.edu/~zyedidia/arm64/cmp_subs_addsub_ext.html
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// CMP <Xn|SP>, <R><m>{, <extend> {#<amount>}}
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return InstructionARM64(Base(0b11101011001000000000000000011111, 32), Rn(a.id()), Rn(b.id()));
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}
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//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -1,6 +1,7 @@
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#pragma once
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#include <cstring>
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#include <span>
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#include <variant>
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#include "common/common_types.h"
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@@ -44,19 +45,33 @@ constexpr u32 Base(u32 value, u32 width) {
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return value << (32 - width);
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}
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constexpr Field Sh(u32 x) {
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ASSERT(x >= 0 && x <= ((2 ^ 1) - 1));
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return Field{(x & 1) << 22};
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}
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constexpr Field Shift(u32 x) {
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ASSERT(x >= 0 && x <= ((2 ^ 2) - 1));
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return Field{(x & 1) << 22};
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}
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constexpr Field Rd(u32 x) {
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ASSERT(x >= 0 && x <= ((2 ^ 5) - 1));
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return Field{(x & 31) << 0};
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}
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constexpr Field Rt(u32 x) {
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ASSERT(x >= 0 && x <= ((2 ^ 5) - 1));
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return Field{(x & 31) << 0};
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}
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constexpr Field Rn(u32 x) {
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ASSERT(x >= 0 && x <= ((2 ^ 5) - 1));
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return Field{(x & 31) << 5};
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}
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constexpr Field Rm(u32 x) {
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ASSERT(x >= 0 && x <= ((2 ^ 5) - 1));
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return Field{(x & 31) << 16};
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}
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@@ -111,10 +126,10 @@ struct InstructionARM64 : InstructionImpl<InstructionARM64> {
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//
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// To do so, the instruction can optionally include multiple encodings
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// all of which are emitted at once.
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static constexpr int kMaxInstrs = 4;
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static constexpr int kMaxInstrs = 64;
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u32 encodings[kMaxInstrs]{};
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uint8_t count = 0;
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u8 count = 0;
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InstructionARM64() = delete;
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@@ -131,7 +146,7 @@ struct InstructionARM64 : InstructionImpl<InstructionARM64> {
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constexpr InstructionARM64(const Instrs&... instrs)
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requires(std::is_same_v<Instrs, InstructionARM64> && ...)
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{
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uint8_t idx = 0;
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u8 idx = 0;
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auto append = [&](const InstructionARM64& i) {
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for (uint8_t j = 0; j < i.count; ++j) {
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encodings[idx++] = i.encodings[j];
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@@ -141,6 +156,16 @@ struct InstructionARM64 : InstructionImpl<InstructionARM64> {
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count = idx;
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}
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InstructionARM64(std::span<const InstructionARM64> instrs) {
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u8 idx = 0;
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for (const auto& i : instrs) {
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for (uint8_t j = 0; j < i.count; ++j) {
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encodings[idx++] = i.encodings[j];
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}
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}
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count = idx;
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}
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uint8_t emit(uint8_t* buffer) const {
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if (count == 1 && encodings[0] == 0) {
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return 0;
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