kdiv is a signed 16 bit value in the DEV_CTL1 register. Commit
53990cf9d5 ("clk: imx: pll14xx: consolidate rate calculation") changed
the kdiv variable from a short int to just int. When the value read from
the DIV_CTL1 register is assigned directly to an int the sign of the value
is lost resulting in incorrect results when the value is negative. Adding
a s16 cast to the register value fixes the issue.
Fixes: 53990cf9d5 ("clk: imx: pll14xx: consolidate rate calculation")
Signed-off-by: Kevin Groeneveld <kgroeneveld@lenbrook.com>
Link: https://lore.kernel.org/r/20221210203835.9714-1-kgroeneveld@lenbrook.com
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Pull one more Renesas clk driver update from Geert Uytterhoeven:
- Disable R-Car H3 ES1.*, as it was only available to an internal
development group and needed a lot of quirks and workarounds.
* tag 'renesas-clk-for-v6.3-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*
Compiling clock driver with CONFIG_UBSAN enabled shows the following trace:
UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15
shift exponent 131072 is too large for 32-bit type 'long unsigned int'
CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0
Stack : ...
Call Trace:
[<80009a58>] show_stack+0x38/0x118
[<8045ce04>] dump_stack_lvl+0x60/0x80
[<80458868>] ubsan_epilogue+0x10/0x54
[<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190
[<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0
[<804bb774>] clk_core_is_enabled+0x34/0x90
[<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4
[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
[<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
[<80aad900>] clk_disable_unused+0x78/0x120
[<80002030>] do_one_initcall+0x54/0x1f0
[<80a922a4>] kernel_init_freeable+0x280/0x31c
[<808047c4>] kernel_init+0x20/0x118
[<80003e58>] ret_from_kernel_thread+0x14/0x1c
Shifting a value (131032) larger than the type (32 bit unsigned integer)
is undefined behaviour in C.
The problem is in 'mt7621_gate_is_enabled()' function which is using the
'BIT()' kernel macro with the bit index for the clock gate to check if the
bit is set. When the clock gates structure is created driver is already
setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra
'BIT()' mask here. Removing it solve the problem and makes this function
correct. However when clock gating is correctly working, the kernel starts
disabling those clocks that are not requested. Some drivers for this SoC
are older than this clock driver itself. So to avoid the kernel to disable
clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL'
flag on gates initialization code.
Fixes: 48df7a26f4 ("clk: ralink: add clock driver for mt7621 SoC")
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Randconfig testing revealed multiple issues with this driver:
ERROR: modpost: missing MODULE_LICENSE() in drivers/clk/imx/clk-imxrt1050.o
ERROR: modpost: "imx_clk_hw_pllv3" [drivers/clk/imx/clk-imxrt1050.ko] undefined!
ERROR: modpost: "imx_clk_hw_pfd" [drivers/clk/imx/clk-imxrt1050.ko] undefined!
Export the necessary symbols from the core clk driver and add the
license and author tags. To find this type of problem more easily
in the future, also enable building on other platforms, as we do for
the other i.MX clk drivers.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20221215165836.2136448-1-arnd@kernel.org
Acked-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
In the previous commits that added CLK_OPS_PARENT_ENABLE, support for
this flag was only added to rate change operations (rate setting and
reparent) and disabling unused subtree. It was not added to the
clock gate related operations. Any hardware driver that needs it for
these operations will either see bogus results, or worse, hang.
This has been seen on MT8192 and MT8195, where the imp_ii2_* clk
drivers set this, but dumping debugfs clk_summary would cause it
to hang.
Prepare parent on prepare and enable parent on enable dependencies are
already handled automatically by the core as part of its sequencing.
Whether the case for "enable parent on prepare" should be supported by
this flag or not is not clear, and thus ignored for now.
This change solely fixes the handling of clk_core_is_enabled, i.e.
enabling the parent clock when reading the hardware state. Unfortunately
clk_core_is_enabled is called in a variety of places, sometimes with
the enable clock already held. To avoid deadlocking, the core will
ignore readouts and just return false if CLK_OPS_PARENT_ENABLE is set
but the parent isn't currently enabled.
Fixes: fc8726a2c0 ("clk: core: support clocks which requires parents enable (part 2)")
Fixes: a4b3518d14 ("clk: core: support clocks which requires parents enable (part 1)")
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230103092330.494102-1-wenst@chromium.org
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Pull i.MX clk driver updates from Abel Vesa:
- Free the imx_uart_clocks even if imx_register_uart_clocks returns early
- Get the stdout clocks count from device tree
- Drop the clock count argument from imx_register_uart_clocks.
- Keep the uart clocks on i.MX93 for when earlycon is used
- Fix SPDX comment in i.MX6SLL clocks bindings header
- Drop some unnecessary spaces from i.MX8ULP clocks bindings header
- Add a new clk-gpr-mux clock type and use it on i.MX6Q to add ENET ref
clocks
- Add the imx_obtain_fixed_of_clock for allowing to add a clock that is
not configured via devicetree
- Fix the ENET1 gate configuration for i.MX6UL according to the
reference manual
- Add ENET refclock mux support for i.MX6UL
* tag 'clk-imx-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx6ul: add ethernet refclock mux support
clk: imx6ul: fix enet1 gate configuration
clk: imx: add imx_obtain_fixed_of_clock()
clk: imx6q: add ethernet refclock mux support
clk: imx: add clk-gpr-mux driver
dt-bindings: imx8ulp: clock: no spaces before tabs
clk: imx6sll: add proper spdx license identifier
clk: imx: imx93: invoke imx_register_uart_clocks
clk: imx: remove clk_count of imx_register_uart_clocks
clk: imx: get stdout clk count from device tree
clk: imx: avoid memory leak
R-Car H3 ES1.* was only available to an internal development group and
needed a lot of quirks and workarounds. These become a maintenance
burden now, so our development group decided to remove upstream support
for this SoC. Public users only have ES2 onwards.
In addition to the ES1 specific removals, a check for it was added
preventing the machine to boot further. It may otherwise inherit wrong
clock settings from ES2 which could damage the hardware.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230202092332.2504-1-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add ethernet refclock mux support and set it to internal clock by
default. This configuration will not affect existing boards.
clock tree before this patch:
fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
|- pll6_enet
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
after this patch:
fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ...
`--<> enet1_ref_pad |- pll6_enet
fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ...
`--<> enet2_ref_pad
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Acked-by: Lee Jones <lee@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230131084642.709385-17-o.rempel@pengutronix.de
According to the "i.MX 6UltraLite Applications Processor Reference Manual,
Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root
of PLL6. It is controlling ENET1 separately.
So, instead of this picture (implementation before this patch):
fec1 <- enet_ref (divider) <---------------------------,
|- pll6_enet (gate)
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
we should have this one (after this patch):
fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
|- pll6_enet
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
With this fix, the RMII reference clock will be turned off, after
setting network interface down on each separate interface
(ip l s dev eth0 down). Which was not working before, on system with both
FECs enabled.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de
Almost(?) every i.MX variant has clk mux for ethernet (rgmii/rmii) reference
clock located in the GPR1 register. So far this clk is configured in
different ways:
- mach-imx6q is doing mux configuration based on ptp vs enet_ref clk
comparison.
- mach-imx7d is setting mux to PAD for all boards
- mach-imx6ul is setting mux to internal clock for all boards.
Since we have imx7d and imx6ul board variants which do not work with
configurations forced by kernel mach code, we need to implement this clk
mux properly as part of the clk framework. Which is done by this patch.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230131084642.709385-2-o.rempel@pengutronix.de
Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
ethernet subsystem clocks.
The drivers are based on clk-mt7981.c which can be found in MediaTek's
SDK sources. To be fit for upstream inclusion the driver has been split
into clock domains and the infracfg part has been significantly
de-bloated by removing all the 1:1 factors (aliases).
Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
[sboyd@kernel.org: Add module license]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This driver is registered early in clk_mt8192_top_init_early() and
then again in clk_mt8192_top_probe(): the difference between the
two is that the early one is probed with CLK_OF_DECLARE_DRIVER and
the latter is regularly probed as a platform_driver.
Knowing that it is not necessary for this platform to register the
TOP_CSW_F26M_D2 clock that early, move it to top_divs and register
it with the others during platform_driver probe for topckgen;
While at it, since the only reason why the early probe existed was
to register that clock, remove that entirely - leaving this driver
to use only platform_driver.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-15-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Split the giant clock driver for MT8173 into smaller drivers and
make it possible to build the non boot critical clock controller
drivers as modules by adding remove functions and both module
description and license where needed.
While at it, also change a mtk_register_reset_controller() call
to mtk_register_reset_controller_with_dev() in mt8173-infracfg.
Some spare code style cleanups were also performed.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230120092053.182923-11-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This driver is using CLK_OF_DECLARE() for all clocks: while this
definitely works, it's not preferred as this makes it impossible
to compile non boot critical clock drivers as modules and to take
advantage of clock controller Runtime PM.
As a preparation for a larger cleanup, migrate all of the clock
controller drivers for MT8173 to platform_driver and use the
common mtk_clk_simple_probe() where possible; while at it, also
add proper error handling to the various probe functions.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230120092053.182923-9-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Commit e4c23e19aa ("clk: mediatek: Register clock gate with device")
introduces a helper function for the sole purpose of propagating a
struct device pointer to the clk API when registering the mtk-gate
clocks to take advantage of Runtime PM when/where needed and where
a power domain is defined in devicetree.
Function mtk_clk_register_gates() then becomes a wrapper around the
new mtk_clk_register_gates_with_dev() function that will simply pass
NULL as struct device: this is essential when registering drivers
with CLK_OF_DECLARE instead of as a platform device, as there will
be no struct device to pass... but we can as well simply have only
one function that always takes such pointer as a param and pass NULL
when unavoidable.
This commit removes the mtk_clk_register_gates() wrapper and renames
mtk_clk_register_gates_with_dev() to the former and all of the calls
to either of the two functions were fixed in all drivers in order to
reflect this change; also, to improve consistency with other kernel
functions, the pointer to struct device was moved as the first param.
Since a lot of MediaTek clock drivers are actually registering as a
platform device, but were still registering the mtk-gate clocks
without passing any struct device to the clock framework, they've
been changed to pass a valid one now, as to make all those platforms
able to use runtime power management where available.
While at it, some much needed indentation changes were also done.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20230120092053.182923-4-angelogioacchino.delregno@collabora.com
Tested-by: Mingming Su <mingming.su@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Pull Allwinner clk driver updates from Jernej Skrabec:
- add D1 CAN bus gates and resets
- mark D1 CPUX clock as critical
- reuse D1 driver for R528/T113
- cleanup sunxi-ng kconfig
- fix sunxi-ng kernel-doc issues
- model H3/H5 DRAM clock as fixed clock
* tag 'sunxi-clk-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: d1: Add CAN bus gates and resets
dt-bindings: clock: Add D1 CAN bus gates and resets
clk: sunxi-ng: d1: Mark cpux clock as critical
clk: sunxi-ng: d1: Allow building for R528/T113
clk: sunxi-ng: Move SoC driver conditions to dependencies
clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependencies
clk: sunxi-ng: Avoid computing the rate twice
clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clock
clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issues
