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Shazad Hussain
2eb4cdcd5a arm64: dts: qcom: sa8540p-ride: enable pcie2a node 
Add the pcie2a, pcie2a_phy, and respective tlmm nodes that are needed to
get pcie 2a controller enabled on Qdrive3.

This patch enables 4GB 64bit memory space for PCIE_2A to have BAR
allocations of 64bit pref mem needed on this Qdrive3 platform with dual
SoCs for root port and switch NT-EP. Hence this ranges property is
overridden in sa8540p-ride.dts only.

Moved tlmm node at the end as it tends to become rahter long.

Link: https://lore.kernel.org/lkml/Y49k1k8ayI9%2FrK+R@hovoldconsulting.com/
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213095922.11649-1-quic_shazhuss@quicinc.com
 2023-01-10 22:22:10 -06:00
Krzysztof Kozlowski
3bd21131d8 arm64: dts: qcom: sdm845: order top-level nodes alphabetically 
Order top-level nodes like memory, reserved-memory, opp-table-cpu
alphabetically for easier code maintenance.  No functional change (same
dtx_diff, except phandle changes).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221212100232.138519-2-krzysztof.kozlowski@linaro.org
 2023-01-10 22:15:47 -06:00
Krzysztof Kozlowski
41d31fa487 arm64: dts: qcom: sc7180: order top-level nodes alphabetically 
Order top-level nodes like memory, reserved-memory, opp-table-cpu
alphabetically for easier code maintenance.  No functional change (same
dtx_diff).

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221212100232.138519-1-krzysztof.kozlowski@linaro.org
 2023-01-10 22:15:47 -06:00
Rob Herring
9293c3e85a arm64: dts: qcom: sc7280: Fix CPU nodes compatible string 
'arm,kryo' is not documented and is not an Arm Ltd thing either as that
is Qualcomm branding. The correct compatible is 'qcom,kryo'.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207211327.2848665-1-robh@kernel.org
 2023-01-10 22:09:38 -06:00
Konrad Dybcio
0d89bfbcd6 arm64: dts: qcom: sm8450-nagara: Configure SLG51000 PMIC 
Nagara devices use the Dialog SLG51000 PMIC for powering some camera
sensors. Add the required nodes to support it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-7-konrad.dybcio@linaro.org
 2023-01-10 22:06:04 -06:00
Konrad Dybcio
e9090691e4 arm64: dts: qcom: sm8450-nagara: Enable PMIC RESIN+PON 
Enable the power and volume up buttons, connected to PON and RESIN
respectively.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-6-konrad.dybcio@linaro.org
 2023-01-10 22:06:04 -06:00
Konrad Dybcio
40430a7c48 arm64: dts: qcom: sm8450-nagara: Set up camera regulators 
Set up gpio-controlled fixed regulators for camera on PDX223 and fix
up the existing ones in common and PDX224 trees.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-5-konrad.dybcio@linaro.org
 2023-01-10 22:06:04 -06:00
Konrad Dybcio
7b25576978 arm64: dts: qcom: sm8450-nagara: Add GPIO keys 
With PMIC GPIOs now available, set up required pin settings and add
gpio-keys.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-4-konrad.dybcio@linaro.org
 2023-01-10 22:06:04 -06:00
Konrad Dybcio
4c5ab70d11 arm64: dts: qcom: sm8450-nagara: Add GPIO line names for PMIC GPIOs 
Sony ever so graciously provides GPIO line names in their downstream
kernel (though sometimes they are not 100% accurate and you can judge
that by simply looking at them and with what drivers they are used).

Add these to the PDX223&224 DTSIs to better document the hardware.

Diff between 223 and 224:
pm8350b
< 			  "CAM_PWR_LD_EN",
> 			  "NC",

pm8350c
<			  "RGBC_IR_PWR_EN",
> 			  "NC",

Which is due to different camera power wiring on 223 and lack of a
ToF sensor on 224.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-3-konrad.dybcio@linaro.org
 2023-01-10 22:06:04 -06:00
Konrad Dybcio
25deb75e99 arm64: dts: qcom: sm8450-nagara: Include PMIC DTSIs 
Now that SPMI is finally in place, include the DTSIs of PMICs present
on Nagara.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-2-konrad.dybcio@linaro.org
 2023-01-10 22:06:04 -06:00
Vinod Koul
f891f86e47 arm64: dts: qcom: sm8450: add spmi node 
Add the spmi bus as found in the SM8450 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Adjusted unit address]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-1-konrad.dybcio@linaro.org
 2023-01-10 22:05:47 -06:00
Neil Armstrong
433477c3bf arm64: dts: qcom: sm8550: add QCrypto nodes 
Add the QCE and Crypto BAM DMA nodes.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-qce-v1-0-fe750dfa90f6@linaro.org
 2023-01-10 12:45:27 -06:00
Neil Armstrong
377972ac74 arm64: dts: qcom: sm8550: add I2C Master Hub nodes 
Add the I2C Master Hub wrapper and I2C serial engines nodes.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-gpi-qup-v1-0-86a60cf3e57d@linaro.org
 2023-01-10 12:45:23 -06:00
Abel Vesa
71342fb91e arm64: dts: qcom: Add base SM8550 MTP dts 
Add dts file for Qualcomm MTP platform which uses SM8550 SoC.

Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-11-abel.vesa@linaro.org
 2023-01-10 12:27:28 -06:00
Neil Armstrong
4e7b112617 arm64: dts: qcom: Add PMR735d pmic dtsi 
Add nodes for PMR735d in separate dtsi file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-10-abel.vesa@linaro.org
 2023-01-10 12:27:28 -06:00
Neil Armstrong
e9c0a4e484 arm64: dts: qcom: Add PMK8550 pmic dtsi 
Add nodes for PMK8550 in separate dtsi file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-9-abel.vesa@linaro.org
 2023-01-10 12:27:28 -06:00
Neil Armstrong
d6056ec543 arm64: dts: qcom: Add PM8550vs pmic dtsi 
Add nodes for PM8550vs in separate dtsi file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-8-abel.vesa@linaro.org
 2023-01-10 12:27:28 -06:00
Neil Armstrong
8ba6d5d8f1 arm64: dts: qcom: Add PM8550ve pmic dtsi 
Add nodes for PM8550ve in separate dtsi file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-7-abel.vesa@linaro.org
 2023-01-10 12:27:28 -06:00
Neil Armstrong
9543f989c2 arm64: dts: qcom: Add PM8550b pmic dtsi 
Add nodes for PM8550b in separate dtsi file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-6-abel.vesa@linaro.org
 2023-01-10 12:27:28 -06:00
Neil Armstrong
2e9686d194 arm64: dts: qcom: Add PM8550 pmic dtsi 
Add nodes for PM8550 in separate dtsi file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-5-abel.vesa@linaro.org
 2023-01-10 12:27:28 -06:00
Neil Armstrong
89565d8f54 arm64: dts: qcom: Add pm8010 pmic dtsi 
Add nodes for pm8010 in separate dtsi file.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-4-abel.vesa@linaro.org
 2023-01-10 12:27:28 -06:00
Abel Vesa
ffc50b2d38 arm64: dts: qcom: Add base SM8550 dtsi 
Add base dtsi for SM8550 SoC and includes base description of
CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
interconnect, thermal sensor, cpu cooling maps and SMMU nodes
which helps boot to shell with console on boards with this SoC.

Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-3-abel.vesa@linaro.org
 2023-01-10 12:27:27 -06:00
Bjorn Andersson
19d2810822 Merge branch '20230104093450.3150578-2-abel.vesa@linaro.org' into arm64-for-6.3 
Merge the TCSR clock binding, to gain the Devicetree include file.
 2023-01-10 12:27:27 -06:00
Abel Vesa
d220193c50 dt-bindings: clock: Add SM8550 TCSR CC clocks 
Add bindings documentation for clock TCSR driver on SM8550.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104093450.3150578-2-abel.vesa@linaro.org
 2023-01-10 12:24:40 -06:00
Bjorn Andersson
ee7ccd5fe8 Merge branch 'icc-sm8550-immutable' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.3 
Merge the immutable SM8550 interconnect branch, to gain the include file
from the binding.
 2023-01-10 12:21:27 -06:00
Dmitry Baryshkov
b7f4f6971d arm64: dts: qcom: sm8450: Add compat qcom,sm8450-dsi-ctrl 
Add silicon specific compatible qcom,sm8450-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sm8450 against the yaml documentation.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230110055433.734188-3-dmitry.baryshkov@linaro.org
 2023-01-10 11:22:41 -06:00
Dmitry Baryshkov
b0b8b34a8d arm64: dts: qcom: sm8150: Add compat qcom,sm8150-dsi-ctrl 
Add silicon specific compatible qcom,sm8150-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sm8150 against the yaml documentation.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230110055433.734188-2-dmitry.baryshkov@linaro.org
 2023-01-10 11:22:41 -06:00
Krzysztof Kozlowski
0cbc0b1c58 arm64: dts: qcom: sdm845: do not customize SPI0 pin drive/bias 
Each board should define pin drive/bias for used busses.  All boards
using SPI0 (db845c and cheza) already do it, so drop the bias/drive
strength from SoC DTSI.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222151319.122398-4-krzysztof.kozlowski@linaro.org
 2023-01-10 09:27:45 -06:00
Krzysztof Kozlowski
d05e342882 arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema 
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222151319.122398-3-krzysztof.kozlowski@linaro.org
 2023-01-10 09:27:45 -06:00
Krzysztof Kozlowski
e501144737 arm64: dts: qcom: sdm845-xiaomi-beryllium: fix audio codec interrupt pin name 
The pin config entry should have a string, not number, for the GPIO used
as WCD9340 audio codec interrupt.

Fixes: dd6459a089 ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts")
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222151319.122398-2-krzysztof.kozlowski@linaro.org
 2023-01-10 09:27:29 -06:00
Krzysztof Kozlowski
740862bb5f arm64: dts: qcom: sdm845-db845c: fix audio codec interrupt pin name 
The pin config entry should have a string, not number, for the GPIO used
as WCD9340 audio codec interrupt.

Fixes: 89a32a4e76 ("arm64: dts: qcom: db845c: add analog audio support")
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222151319.122398-1-krzysztof.kozlowski@linaro.org
 2023-01-10 09:27:29 -06:00
Quentin Schulz
8a0721dae6 arm64: dts: qcom: msm8998-fxtec: fix touchscreen reset GPIO polarity 
The reset line is active low for the Goodix touchscreen controller so
let's fix the polarity in the Device Tree node.

Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221103-upstream-goodix-reset-v3-8-0975809eb183@theobroma-systems.com
 2023-01-10 09:26:25 -06:00
Krzysztof Kozlowski
fce310a2d2 arm64: dts: qcom: sm8450: align PSCI domain names with DT schema 
Bindings expect power domains to follow generic naming pattern:

  sm8450-qrd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
    'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-6-krzysztof.kozlowski@linaro.org
 2023-01-02 08:06:52 -06:00
Krzysztof Kozlowski
a9371962c3 arm64: dts: qcom: sm8350: align PSCI domain names with DT schema 
Bindings expect power domains to follow generic naming pattern:

  sm8350-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
    'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-5-krzysztof.kozlowski@linaro.org
 2023-01-02 08:06:52 -06:00
Krzysztof Kozlowski
56d590022b arm64: dts: qcom: sm8250: align PSCI domain names with DT schema 
Bindings expect power domains to follow generic naming pattern:

  sm8250-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
    'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-4-krzysztof.kozlowski@linaro.org
 2023-01-02 08:06:52 -06:00
Krzysztof Kozlowski
5ca4569055 arm64: dts: qcom: sm8150: align PSCI domain names with DT schema 
Bindings expect power domains to follow generic naming pattern:

  sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
    'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-3-krzysztof.kozlowski@linaro.org
 2023-01-02 08:06:52 -06:00
Krzysztof Kozlowski
0c8bfc7f3b arm64: dts: qcom: sm6375: align PSCI domain names with DT schema 
Bindings expect power domains to follow generic naming pattern:

  sm6375-sony-xperia-murray-pdx225.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
    'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-2-krzysztof.kozlowski@linaro.org
 2023-01-02 08:06:52 -06:00
Krzysztof Kozlowski
ac39297135 arm64: dts: qcom: sc8280xp: align PSCI domain names with DT schema 
Bindings expect power domains to follow generic naming pattern:

  sc8280xp-crd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
    'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-1-krzysztof.kozlowski@linaro.org
 2023-01-02 08:06:52 -06:00
Krzysztof Kozlowski
b9ae6ddede arm64: dts: qcom: sm8450: disable by default Soundwire and VA-macro 
Soundwire is a bus and VA-macro requires a supply, thus both are
expected to be explicitly enabled and populated by board DTS.  The
HDK8450 already enables Soundwire devices, except swr4 which as a result
of this commit will stay disabled.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102123734.478433-1-krzysztof.kozlowski@linaro.org
 2023-01-02 08:04:11 -06:00
Krzysztof Kozlowski
9e8e9be6c4 arm64: dts: qcom: use generic node name for CS35L41 speaker 
Node names should be generic so use consistently speaker-amp for CS35L41
speaker amplifier.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154255.43499-5-krzysztof.kozlowski@linaro.org
 2022-12-29 11:15:14 -06:00
Krzysztof Kozlowski
539a992368 arm64: dts: qcom: sm8450: re-order GCC clocks 
Bindings expect GCC clocks in other order:

  sm8450-hdk.dtb: clock-controller@100000: clock-names:1: 'sleep_clk' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154255.43499-4-krzysztof.kozlowski@linaro.org
 2022-12-29 11:15:14 -06:00
Krzysztof Kozlowski
42db0f72f7 arm64: dts: qcom: sm8250: drop unused clock-frequency from va-macro 
Neither qcom,sm8250-lpass-va-macro bindings nor the driver use
"clock-frequency" property.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154255.43499-3-krzysztof.kozlowski@linaro.org
 2022-12-29 11:15:13 -06:00
Krzysztof Kozlowski
496b308f09 arm64: dts: qcom: msm8996: align bus node names with DT schema 
The node names should be generic and the bindings expect "bus" for
simple-bus nodes:

  msm8996-mtp.dtb: agnoc@0: $nodename:0: 'agnoc@0' does not match '^bus(@[0-9a-f]+)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154255.43499-1-krzysztof.kozlowski@linaro.org
 2022-12-29 11:15:13 -06:00
Marijn Suijten
f3b770f7a8 arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEs 
Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware
connected to them, leaving the rest disabled to save on power.  For
this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to
be connected to Serial Engines on GPU DMA 1 / QUP 1.  Beyond this
downstream only defines a UART console available on Serial Engine 4
which also resides on QUP 0.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216233408.1283581-4-marijn.suijten@somainline.org
 2022-12-29 11:10:37 -06:00
Marijn Suijten
72621d0443 arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines 
Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines.
QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap
in the middle (ranging from 5-9 with SPI 7 missing).  Both QUPs have 5
I2C Serial Engines.

[Marijn: Add iommus, reword patch description, reorder all properties,
 sort based on address, use QCOM_GPI_ constants, drop dma cells from 5
 to 3]

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216233408.1283581-3-marijn.suijten@somainline.org
 2022-12-29 11:09:42 -06:00
Martin Botka
075a6aef55 arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial Engines 
Add pin setup for SPI/I2C Serial Engines that are supported under the
Qualcomm Universal Peripheral found on SM6125.

[Un-nest pins, remove duplicate pins= properties, follow new node naming
 conventions, fix qup_14 -> qup14 function typo]

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216233408.1283581-2-marijn.suijten@somainline.org
 2022-12-29 11:09:42 -06:00
Marijn Suijten
a9f6a13da4 arm64: dts: qcom: sm6125-seine: Clean up gpio-keys (volume down) 
- Remove autorepeat (leave key repetition to userspace);
- Remove unneeded status = "okay" (this is the default);
- Remove unneeded linux,input-type <EV_KEY> (this is the default for
  gpio-keys);
- Allow the interrupt line for this button to be disabled;
- Use a full, descriptive node name;
- Set proper bias on the GPIO via pinctrl;
- Sort properties;
- Replace deprecated gpio-key,wakeup property with wakeup-source.

Fixes: 82e1783890 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222192443.119103-1-marijn.suijten@somainline.org
 2022-12-29 11:09:17 -06:00
Martin Botka
581734f754 arm64: dts: qcom: sm6125: Add GPI DMA nodes 
Add nodes for GPI DMA hosts on SM6125.

[Marijn: reorder properties, use sdm845 fallback compatible, disable by
 default, use 3 instead of 5 dma cells]

Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222194600.139854-3-marijn.suijten@somainline.org
 2022-12-29 11:09:09 -06:00
AngeloGioacchino Del Regno
ac54563c27 arm64: dts: qcom: sm6125: Add IOMMU context to DWC3 
Add an IOMMU context to the USB DWC3 controller, required to get USB
functionality upon enablement of apps_smmu.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222193254.126925-5-marijn.suijten@somainline.org
 2022-12-29 11:07:58 -06:00
Marijn Suijten
60f6c86fb4 arm64: dts: qcom: sm6125: Add apps_smmu with streamID to SDHCI 1/2 nodes 
When enabling the APPS SMMU the mainline driver reconfigures the SMMU
from its bootloader configuration, losing the stream mapping for (among
which) the SDHCI hardware and breaking its ADMA feature.  This feature
can be disabled with:

    sdhci.debug_quirks=0x40

But it is of course desired to have this feature enabled and working
through the SMMU.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222193254.126925-4-marijn.suijten@somainline.org
 2022-12-29 11:07:58 -06:00